Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9607 |
1 |
|
T3 |
219 |
|
T10 |
1 |
|
T6 |
1 |
| others[1] |
505 |
1 |
|
T4 |
1 |
|
T31 |
15 |
|
T49 |
5 |
| others[2] |
488 |
1 |
|
T16 |
1 |
|
T20 |
1 |
|
T31 |
9 |
| others[3] |
807 |
1 |
|
T19 |
1 |
|
T12 |
1 |
|
T31 |
13 |
| false |
229 |
1 |
|
T31 |
5 |
|
T49 |
2 |
|
T24 |
1 |
| true |
2144 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9404 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T26 |
1 |
| others[1] |
278 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T31 |
13 |
| others[2] |
251 |
1 |
|
T31 |
8 |
|
T43 |
1 |
|
T44 |
1 |
| others[3] |
427 |
1 |
|
T16 |
1 |
|
T20 |
1 |
|
T31 |
15 |
| false |
128 |
1 |
|
T31 |
3 |
|
T43 |
1 |
|
T122 |
1 |
| true |
3292 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9391 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
264 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T31 |
7 |
| others[2] |
250 |
1 |
|
T31 |
9 |
|
T46 |
1 |
|
T43 |
1 |
| others[3] |
438 |
1 |
|
T23 |
1 |
|
T31 |
19 |
|
T21 |
1 |
| false |
114 |
1 |
|
T16 |
1 |
|
T31 |
3 |
|
T44 |
2 |
| true |
3323 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9897 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
830 |
1 |
|
T5 |
1 |
|
T31 |
18 |
|
T49 |
23 |
| others[2] |
835 |
1 |
|
T31 |
20 |
|
T49 |
10 |
|
T43 |
1 |
| others[3] |
1273 |
1 |
|
T19 |
1 |
|
T31 |
33 |
|
T49 |
10 |
| false |
394 |
1 |
|
T1 |
1 |
|
T31 |
6 |
|
T49 |
4 |
| true |
551 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9915 |
1 |
|
T1 |
1 |
|
T3 |
219 |
|
T25 |
118 |
| others[1] |
787 |
1 |
|
T19 |
1 |
|
T31 |
21 |
|
T49 |
3 |
| others[2] |
808 |
1 |
|
T31 |
16 |
|
T49 |
12 |
|
T43 |
2 |
| others[3] |
1315 |
1 |
|
T31 |
40 |
|
T49 |
25 |
|
T27 |
1 |
| false |
393 |
1 |
|
T31 |
11 |
|
T49 |
7 |
|
T44 |
2 |
| true |
562 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2346 |
1 |
|
T3 |
41 |
|
T25 |
20 |
|
T19 |
1 |
| others[1] |
2369 |
1 |
|
T3 |
44 |
|
T25 |
22 |
|
T13 |
1 |
| others[2] |
2381 |
1 |
|
T1 |
1 |
|
T3 |
38 |
|
T16 |
1 |
| others[3] |
3885 |
1 |
|
T3 |
81 |
|
T25 |
44 |
|
T23 |
1 |
| false |
1198 |
1 |
|
T3 |
15 |
|
T25 |
10 |
|
T31 |
5 |
| true |
1601 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9436 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
278 |
1 |
|
T38 |
1 |
|
T31 |
6 |
|
T43 |
1 |
| others[2] |
284 |
1 |
|
T20 |
1 |
|
T31 |
15 |
|
T111 |
1 |
| others[3] |
441 |
1 |
|
T5 |
1 |
|
T26 |
1 |
|
T31 |
18 |
| false |
139 |
1 |
|
T31 |
5 |
|
T37 |
1 |
|
T27 |
1 |
| true |
3202 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9603 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
501 |
1 |
|
T5 |
1 |
|
T26 |
1 |
|
T12 |
1 |
| others[2] |
448 |
1 |
|
T4 |
1 |
|
T31 |
11 |
|
T49 |
4 |
| others[3] |
822 |
1 |
|
T16 |
1 |
|
T19 |
1 |
|
T23 |
1 |
| false |
223 |
1 |
|
T31 |
4 |
|
T49 |
1 |
|
T43 |
1 |
| true |
2183 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9420 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
238 |
1 |
|
T31 |
12 |
|
T43 |
3 |
|
T44 |
2 |
| others[2] |
258 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T31 |
11 |
| others[3] |
455 |
1 |
|
T31 |
19 |
|
T43 |
3 |
|
T44 |
1 |
| false |
125 |
1 |
|
T6 |
1 |
|
T38 |
1 |
|
T31 |
2 |
| true |
3284 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9393 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
262 |
1 |
|
T1 |
1 |
|
T31 |
10 |
|
T130 |
16 |
| others[2] |
234 |
1 |
|
T20 |
1 |
|
T31 |
9 |
|
T44 |
1 |
| others[3] |
412 |
1 |
|
T19 |
1 |
|
T23 |
1 |
|
T38 |
1 |
| false |
123 |
1 |
|
T31 |
5 |
|
T43 |
2 |
|
T44 |
1 |
| true |
3356 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9926 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
728 |
1 |
|
T1 |
1 |
|
T12 |
1 |
|
T31 |
17 |
| others[2] |
839 |
1 |
|
T19 |
1 |
|
T31 |
24 |
|
T49 |
12 |
| others[3] |
1342 |
1 |
|
T31 |
28 |
|
T49 |
15 |
|
T124 |
1 |
| false |
401 |
1 |
|
T31 |
12 |
|
T49 |
7 |
|
T43 |
1 |
| true |
544 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9917 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
793 |
1 |
|
T31 |
18 |
|
T49 |
11 |
|
T43 |
1 |
| others[2] |
789 |
1 |
|
T1 |
1 |
|
T31 |
14 |
|
T49 |
14 |
| others[3] |
1325 |
1 |
|
T19 |
1 |
|
T31 |
37 |
|
T49 |
15 |
| false |
388 |
1 |
|
T31 |
9 |
|
T49 |
9 |
|
T43 |
1 |
| true |
568 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2342 |
1 |
|
T3 |
38 |
|
T25 |
21 |
|
T31 |
8 |
| others[1] |
2316 |
1 |
|
T3 |
40 |
|
T25 |
20 |
|
T13 |
1 |
| others[2] |
2318 |
1 |
|
T1 |
1 |
|
T3 |
54 |
|
T25 |
24 |
| others[3] |
3985 |
1 |
|
T3 |
66 |
|
T25 |
45 |
|
T23 |
1 |
| false |
1204 |
1 |
|
T3 |
21 |
|
T25 |
8 |
|
T13 |
1 |
| true |
1615 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9418 |
1 |
|
T3 |
219 |
|
T5 |
1 |
|
T25 |
118 |
| others[1] |
276 |
1 |
|
T6 |
1 |
|
T23 |
1 |
|
T31 |
10 |
| others[2] |
256 |
1 |
|
T31 |
8 |
|
T21 |
1 |
|
T46 |
1 |
| others[3] |
455 |
1 |
|
T38 |
1 |
|
T31 |
12 |
|
T124 |
1 |
| false |
155 |
1 |
|
T16 |
1 |
|
T31 |
6 |
|
T43 |
1 |
| true |
3220 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9601 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
476 |
1 |
|
T19 |
1 |
|
T31 |
7 |
|
T49 |
3 |
| others[2] |
486 |
1 |
|
T20 |
1 |
|
T31 |
10 |
|
T49 |
6 |
| others[3] |
741 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T5 |
1 |
| false |
267 |
1 |
|
T31 |
1 |
|
T21 |
1 |
|
T43 |
3 |
| true |
2209 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9384 |
1 |
|
T3 |
219 |
|
T6 |
1 |
|
T25 |
118 |
| others[1] |
283 |
1 |
|
T23 |
1 |
|
T31 |
7 |
|
T224 |
1 |
| others[2] |
293 |
1 |
|
T19 |
1 |
|
T38 |
1 |
|
T31 |
9 |
| others[3] |
425 |
1 |
|
T26 |
1 |
|
T31 |
15 |
|
T21 |
1 |
| false |
144 |
1 |
|
T31 |
7 |
|
T130 |
10 |
|
T376 |
1 |
| true |
3251 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9389 |
1 |
|
T1 |
1 |
|
T3 |
219 |
|
T16 |
1 |
| others[1] |
267 |
1 |
|
T31 |
7 |
|
T43 |
1 |
|
T130 |
13 |
| others[2] |
251 |
1 |
|
T19 |
1 |
|
T31 |
9 |
|
T21 |
1 |
| others[3] |
442 |
1 |
|
T6 |
1 |
|
T20 |
1 |
|
T31 |
11 |
| false |
128 |
1 |
|
T31 |
6 |
|
T46 |
1 |
|
T130 |
4 |
| true |
3303 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9922 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
778 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T31 |
20 |
| others[2] |
769 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T31 |
22 |
| others[3] |
1352 |
1 |
|
T31 |
27 |
|
T49 |
24 |
|
T43 |
1 |
| false |
415 |
1 |
|
T31 |
9 |
|
T49 |
5 |
|
T24 |
1 |
| true |
544 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9886 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
833 |
1 |
|
T31 |
23 |
|
T49 |
16 |
|
T43 |
1 |
| others[2] |
781 |
1 |
|
T1 |
1 |
|
T31 |
22 |
|
T49 |
12 |
| others[3] |
1335 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T12 |
1 |
| false |
395 |
1 |
|
T31 |
11 |
|
T49 |
2 |
|
T43 |
1 |
| true |
550 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2322 |
1 |
|
T3 |
54 |
|
T25 |
18 |
|
T23 |
1 |
| others[1] |
2386 |
1 |
|
T3 |
41 |
|
T25 |
30 |
|
T31 |
10 |
| others[2] |
2299 |
1 |
|
T3 |
37 |
|
T6 |
1 |
|
T25 |
17 |
| others[3] |
3911 |
1 |
|
T1 |
1 |
|
T3 |
67 |
|
T25 |
41 |
| false |
1263 |
1 |
|
T3 |
20 |
|
T25 |
12 |
|
T13 |
1 |
| true |
1599 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9443 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T23 |
1 |
| others[1] |
285 |
1 |
|
T31 |
6 |
|
T21 |
1 |
|
T43 |
2 |
| others[2] |
282 |
1 |
|
T31 |
16 |
|
T43 |
3 |
|
T24 |
1 |
| others[3] |
453 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T31 |
15 |
| false |
140 |
1 |
|
T26 |
1 |
|
T31 |
4 |
|
T43 |
1 |
| true |
3177 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9620 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
478 |
1 |
|
T4 |
1 |
|
T31 |
9 |
|
T49 |
4 |
| others[2] |
484 |
1 |
|
T26 |
1 |
|
T31 |
15 |
|
T49 |
4 |
| others[3] |
823 |
1 |
|
T1 |
1 |
|
T16 |
1 |
|
T19 |
1 |
| false |
243 |
1 |
|
T31 |
5 |
|
T49 |
5 |
|
T43 |
1 |
| true |
2132 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9402 |
1 |
|
T1 |
1 |
|
T3 |
219 |
|
T16 |
1 |
| others[1] |
275 |
1 |
|
T20 |
1 |
|
T31 |
9 |
|
T43 |
1 |
| others[2] |
232 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T31 |
6 |
| others[3] |
454 |
1 |
|
T26 |
1 |
|
T31 |
16 |
|
T43 |
2 |
| false |
114 |
1 |
|
T31 |
6 |
|
T44 |
1 |
|
T130 |
7 |
| true |
3303 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9375 |
1 |
|
T3 |
219 |
|
T6 |
1 |
|
T25 |
118 |
| others[1] |
258 |
1 |
|
T23 |
1 |
|
T31 |
10 |
|
T43 |
1 |
| others[2] |
252 |
1 |
|
T31 |
14 |
|
T43 |
1 |
|
T44 |
1 |
| others[3] |
407 |
1 |
|
T16 |
1 |
|
T19 |
1 |
|
T31 |
13 |
| false |
138 |
1 |
|
T31 |
2 |
|
T44 |
1 |
|
T111 |
1 |
| true |
3350 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9934 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T19 |
1 |
| others[1] |
797 |
1 |
|
T31 |
27 |
|
T49 |
12 |
|
T43 |
2 |
| others[2] |
796 |
1 |
|
T31 |
18 |
|
T49 |
13 |
|
T46 |
1 |
| others[3] |
1316 |
1 |
|
T1 |
1 |
|
T31 |
29 |
|
T49 |
18 |
| false |
379 |
1 |
|
T31 |
10 |
|
T34 |
1 |
|
T130 |
11 |
| true |
558 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |