Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	256792	1		T1	952		T3	1272		T16	1
auto[FlashEraseBank]	288709	1		T1	687		T4	1		T5	6

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	272675	1		T1	1639		T3	632		T5	7
auto[FlashOpProgram]	253887	1		T3	320		T4	1		T16	1
auto[FlashOpErase]	14939	1		T3	320		T25	169		T31	48
auto[FlashOpInvalid]	4000	1		T71	200		T129	200		T133	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	272675	1		T1	1639		T3	632		T5	7
op[FlashOpProgram]	253887	1		T3	320		T4	1		T16	1
op[FlashOpErase]	14939	1		T3	320		T25	169		T31	48
read_erase_read	543	1		T31	6		T32	1		T44	2
read_prog_read	890	1		T5	1		T6	10		T20	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	403507	1		T1	1639		T16	1		T5	5
auto[FlashPartInfo]	138621	1		T3	1272		T4	1		T5	3
auto[FlashPartInfo1]	732	1		T6	5		T21	1		T44	14
auto[FlashPartInfo2]	2641	1		T6	11		T23	13		T20	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	200778	1		T1	1639		T5	4		T6	763
auto[FlashPartData]	auto[FlashOpProgram]	195152	1		T16	1		T5	1		T6	2001
auto[FlashPartData]	auto[FlashOpErase]	3655	1		T31	32		T43	1		T44	1
auto[FlashPartData]	auto[FlashOpInvalid]	3922	1		T71	192		T129	196		T133	190
auto[FlashPartInfo]	auto[FlashOpRead]	69737	1		T3	632		T5	3		T6	360
auto[FlashPartInfo]	auto[FlashOpProgram]	57565	1		T3	320		T4	1		T6	168
auto[FlashPartInfo]	auto[FlashOpErase]	11251	1		T3	320		T25	169		T31	16
auto[FlashPartInfo]	auto[FlashOpInvalid]	68	1		T71	8		T129	2		T133	8
auto[FlashPartInfo1]	auto[FlashOpRead]	563	1		T6	5		T21	1		T44	14
auto[FlashPartInfo1]	auto[FlashOpProgram]	164	1		T115	32		T117	1		T118	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T63	1		T117	1		T386	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T117	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1597	1		T6	8		T38	3		T21	2
auto[FlashPartInfo2]	auto[FlashOpProgram]	1006	1		T6	3		T23	13		T20	1
auto[FlashPartInfo2]	auto[FlashOpErase]	30	1		T129	1		T133	1		T376	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T129	2		T133	2		T387	2