Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29197	1		T3	648		T25	336		T69	624
auto[1]	54	1		T27	1		T201	1		T388	1
auto[2]	51	1		T24	1		T41	2		T389	9
auto[3]	222	1		T5	1		T24	1		T28	7

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7381	1		T3	162		T25	84		T69	156
evic_idx[1]	7391	1		T3	162		T25	84		T69	156
evic_idx[2]	7369	1		T3	162		T25	84		T69	156
evic_idx[3]	7383	1		T3	162		T5	1		T25	84

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28569	1		T3	648		T25	336		T69	624
evic_op[2]	349	1		T5	1		T24	2		T27	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7081	1		T3	162		T25	84		T69	156
evic_idx[0]	evic_op[1]	auto[1]	12	1		T389	1		T274	3		T390	3
evic_idx[0]	evic_op[1]	auto[2]	8	1		T389	3		T274	1		T391	1
evic_idx[0]	evic_op[1]	auto[3]	46	1		T28	2		T376	1		T391	5
evic_idx[0]	evic_op[2]	auto[0]	68	1		T58	4		T130	1		T42	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T201	1		T392	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	2	1		T393	1		T394	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	10	1		T40	1		T395	1		T396	1
evic_idx[1]	evic_op[1]	auto[0]	7082	1		T3	162		T25	84		T69	156
evic_idx[1]	evic_op[1]	auto[1]	11	1		T389	1		T274	2		T390	4
evic_idx[1]	evic_op[1]	auto[2]	11	1		T389	3		T274	1		T391	1
evic_idx[1]	evic_op[1]	auto[3]	46	1		T28	3		T376	2		T274	3
evic_idx[1]	evic_op[2]	auto[0]	71	1		T58	4		T130	1		T112	1
evic_idx[1]	evic_op[2]	auto[1]	4	1		T388	1		T72	1		T397	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T24	1		T41	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	12	1		T204	1		T41	1		T128	1
evic_idx[2]	evic_op[1]	auto[0]	7082	1		T3	162		T25	84		T69	156
evic_idx[2]	evic_op[1]	auto[1]	7	1		T389	1		T390	2		T398	4
evic_idx[2]	evic_op[1]	auto[2]	8	1		T389	2		T390	1		T399	1
evic_idx[2]	evic_op[1]	auto[3]	37	1		T28	1		T376	1		T274	1
evic_idx[2]	evic_op[2]	auto[0]	69	1		T58	4		T130	1		T143	1
evic_idx[2]	evic_op[2]	auto[1]	5	1		T27	1		T72	1		T400	1
evic_idx[2]	evic_op[2]	auto[2]	1	1		T401	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	9	1		T42	1		T402	1		T403	1
evic_idx[3]	evic_op[1]	auto[0]	7078	1		T3	162		T25	84		T69	156
evic_idx[3]	evic_op[1]	auto[1]	8	1		T389	1		T274	2		T390	3
evic_idx[3]	evic_op[1]	auto[2]	5	1		T389	1		T391	1		T390	1
evic_idx[3]	evic_op[1]	auto[3]	47	1		T28	1		T376	3		T391	4
evic_idx[3]	evic_op[2]	auto[0]	72	1		T58	4		T130	1		T226	1
evic_idx[3]	evic_op[2]	auto[1]	5	1		T72	1		T404	1		T405	1
evic_idx[3]	evic_op[2]	auto[2]	2	1		T41	1		T393	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	15	1		T5	1		T24	1		T210	1