Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

---

Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	3152	1		T326	1159		T327	1993		-	-
rd_lvl[2]	56726	1		T1	11978		T213	1203		T328	12146
rd_lvl[3]	21466	1		T1	567		T26	903		T329	782
rd_lvl[4]	39956	1		T26	3265		T144	1404		T329	2046
rd_lvl[5]	13430	1		T26	374		T37	889		T144	392
rd_lvl[6]	11184	1		T26	961		T37	260		T329	1234
rd_lvl[7]	11723	1		T26	1178		T37	1		T144	85
rd_lvl[8]	21790	1		T26	730		T37	100		T144	1
rd_lvl[9]	5771	1		T219	168		T330	479		T331	479
rd_lvl[10]	8383	1		T219	1480		T330	1188		T328	1
rd_lvl[11]	5072	1		T37	101		T144	1		T332	636
rd_lvl[12]	4327	1		T144	85		T213	75		T332	1103
rd_lvl[13]	2271	1		T213	75		T275	496		T36	295
rd_lvl[14]	7458	1		T34	1262		T333	1345		T275	1147
rd_lvl[15]	5323	1		T34	350		T333	336		T35	150