Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	314420	1		T1	13680		T2	1		T3	1
all_pins[1]	314420	1		T1	13680		T2	1		T3	1
all_pins[2]	314420	1		T1	13680		T2	1		T3	1
all_pins[3]	314420	1		T1	13680		T2	1		T3	1
all_pins[4]	314420	1		T1	13680		T2	1		T3	1
all_pins[5]	314420	1		T1	13680		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1534908	1		T1	67896		T2	6		T3	6
values[0x1]	351612	1		T1	14184		T26	9142		T23	1556
transitions[0x0=>0x1]	307070	1		T1	13112		T26	7654		T23	1556
transitions[0x1=>0x0]	307053	1		T1	13112		T26	7654		T23	1556

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	314274	1		T1	13680		T2	1		T3	1
all_pins[0]	values[0x1]	146	1		T248	6		T249	5		T250	6
all_pins[0]	transitions[0x0=>0x1]	73	1		T248	6		T249	1		T250	4
all_pins[0]	transitions[0x1=>0x0]	76	1		T248	1		T250	2		T321	5
all_pins[1]	values[0x0]	314271	1		T1	13680		T2	1		T3	1
all_pins[1]	values[0x1]	149	1		T248	1		T249	4		T250	4
all_pins[1]	transitions[0x0=>0x1]	115	1		T248	1		T249	4		T250	3
all_pins[1]	transitions[0x1=>0x0]	6110	1		T34	1		T35	105		T336	932
all_pins[2]	values[0x0]	308276	1		T1	13680		T2	1		T3	1
all_pins[2]	values[0x1]	6144	1		T34	1		T35	105		T336	932
all_pins[2]	transitions[0x0=>0x1]	54	1		T248	1		T249	3		T250	2
all_pins[2]	transitions[0x1=>0x0]	218349	1		T1	12545		T26	7411		T37	1351
all_pins[3]	values[0x0]	89981	1		T1	1135		T2	1		T3	1
all_pins[3]	values[0x1]	224439	1		T1	12545		T26	7411		T37	1351
all_pins[3]	transitions[0x0=>0x1]	186132	1		T1	11473		T26	5923		T37	1181
all_pins[3]	transitions[0x1=>0x0]	82372	1		T1	567		T26	243		T23	1556
all_pins[4]	values[0x0]	193741	1		T1	12041		T2	1		T3	1
all_pins[4]	values[0x1]	120679	1		T1	1639		T26	1731		T23	1556
all_pins[4]	transitions[0x0=>0x1]	120666	1		T1	1639		T26	1731		T23	1556
all_pins[4]	transitions[0x1=>0x0]	42	1		T248	1		T249	2		T250	2
all_pins[5]	values[0x0]	314365	1		T1	13680		T2	1		T3	1
all_pins[5]	values[0x1]	55	1		T248	3		T249	2		T250	2
all_pins[5]	transitions[0x0=>0x1]	30	1		T248	1		T249	1		T250	1
all_pins[5]	transitions[0x1=>0x0]	104	1		T248	4		T249	3		T250	4