Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	296	1		T248	7		T249	7		T250	7
all_values[1]	296	1		T248	7		T249	7		T250	7
all_values[2]	296	1		T248	7		T249	7		T250	7
all_values[3]	296	1		T248	7		T249	7		T250	7
all_values[4]	296	1		T248	7		T249	7		T250	7
all_values[5]	296	1		T248	7		T249	7		T250	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1014	1		T248	30		T249	26		T250	16
auto[1]	762	1		T248	12		T249	16		T250	26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	596	1		T248	12		T249	13		T250	14
auto[1]	1180	1		T248	30		T249	29		T250	28

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1046	1		T248	25		T249	26		T250	28
auto[1]	730	1		T248	17		T249	16		T250	14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	103	1		T248	3		T249	4		T321	2
all_values[0]	auto[0]	auto[1]	auto[1]	69	1		T248	3		T249	2		T250	5
all_values[0]	auto[1]	auto[0]	auto[1]	75	1		T249	1		T250	1		T322	2
all_values[0]	auto[1]	auto[1]	auto[1]	49	1		T248	1		T250	1		T322	1
all_values[1]	auto[0]	auto[0]	auto[1]	95	1		T248	3		T249	3		T250	3
all_values[1]	auto[0]	auto[1]	auto[1]	81	1		T249	1		T250	3		T321	2
all_values[1]	auto[1]	auto[0]	auto[1]	71	1		T248	4		T249	2		T250	1
all_values[1]	auto[1]	auto[1]	auto[1]	49	1		T249	1		T321	4		T323	2
all_values[2]	auto[0]	auto[0]	auto[0]	109	1		T248	4		T249	1		T250	3
all_values[2]	auto[0]	auto[1]	auto[0]	59	1		T248	1		T249	1		T250	1
all_values[2]	auto[1]	auto[0]	auto[1]	66	1		T248	1		T249	1		T250	1
all_values[2]	auto[1]	auto[1]	auto[1]	62	1		T248	1		T249	4		T250	2
all_values[3]	auto[0]	auto[0]	auto[0]	92	1		T248	2		T249	3		T322	1
all_values[3]	auto[0]	auto[1]	auto[0]	89	1		T248	3		T249	2		T250	4
all_values[3]	auto[1]	auto[0]	auto[1]	66	1		T248	1		T249	2		T250	2
all_values[3]	auto[1]	auto[1]	auto[1]	49	1		T248	1		T250	1		T322	1
all_values[4]	auto[0]	auto[0]	auto[0]	55	1		T249	2		T250	1		T322	1
all_values[4]	auto[0]	auto[0]	auto[1]	33	1		T248	3		T249	2		T250	1
all_values[4]	auto[0]	auto[1]	auto[0]	53	1		T248	1		T250	2		T321	1
all_values[4]	auto[0]	auto[1]	auto[1]	26	1		T250	1		T322	1		T321	1
all_values[4]	auto[1]	auto[0]	auto[1]	87	1		T248	3		T249	2		T250	2
all_values[4]	auto[1]	auto[1]	auto[1]	42	1		T249	1		T322	1		T321	2
all_values[5]	auto[0]	auto[0]	auto[0]	75	1		T248	1		T249	3		T322	1
all_values[5]	auto[0]	auto[0]	auto[1]	22	1		T248	1		T322	1		T324	1
all_values[5]	auto[0]	auto[1]	auto[0]	64	1		T249	1		T250	3		T321	4
all_values[5]	auto[0]	auto[1]	auto[1]	21	1		T249	1		T250	1		T325	1
all_values[5]	auto[1]	auto[0]	auto[1]	65	1		T248	4		T250	1		T322	1
all_values[5]	auto[1]	auto[1]	auto[1]	49	1		T248	1		T249	2		T250	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal