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LINE 140
EXPRESSION (read_buf[0].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 140
EXPRESSION (read_buf[1].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 140
EXPRESSION (read_buf[2].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 140
EXPRESSION (read_buf[3].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 141
EXPRESSION (read_buf[0].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 141
EXPRESSION (read_buf[1].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 141
EXPRESSION (read_buf[2].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 141
EXPRESSION (read_buf[3].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 146
EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T6,T202,T148 |
1 | 0 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (read_buf[0].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T5 |
1 | 1 | 0 | Covered | T203 |
1 | 1 | 1 | Covered | T6,T202,T148 |
LINE 146
SUB-EXPRESSION (read_buf[0].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 146
EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T6,T131,T202 |
1 | 0 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (read_buf[1].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T6,T131,T202 |
LINE 146
SUB-EXPRESSION (read_buf[1].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 146
EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T6,T202,T148 |
1 | 0 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (read_buf[2].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T6,T202,T148 |
LINE 146
SUB-EXPRESSION (read_buf[2].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 146
EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T6,T24,T202 |
1 | 0 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (read_buf[3].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T5 |
1 | 1 | 0 | Covered | T205,T203 |
1 | 1 | 1 | Covered | T6,T24,T202 |
LINE 146
SUB-EXPRESSION (read_buf[3].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 154
EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
-------1------ ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 154
EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 154
EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 167
EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 167
SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
-----------1---------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (req_o & ack_i & no_match)
--1-- --2-- ----3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T6,T21,T46 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 186
EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[0].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[1].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[2].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[3].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 194
EXPRESSION (read_buf[0].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 194
EXPRESSION (read_buf[1].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 194
EXPRESSION (read_buf[2].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 194
EXPRESSION (read_buf[3].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[0] | buf_wip[0]) &
4 (read_buf[0].addr == flash_word_addr) &
5 ((~read_buf[0].err)) &
6 gen_buf_match[0].part_match &
7 gen_buf_match[0].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T40,T136,T211 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T4,T5 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T6,T202,T148 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T212,T213,T214 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 196
SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
LINE 196
SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[1] | buf_wip[1]) &
4 (read_buf[1].addr == flash_word_addr) &
5 ((~read_buf[1].err)) &
6 gen_buf_match[1].part_match &
7 gen_buf_match[1].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T71,T129,T41 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T4,T5 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T6,T202,T148 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T127,T215,T214 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 196
SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
LINE 196
SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[2] | buf_wip[2]) &
4 (read_buf[2].addr == flash_word_addr) &
5 ((~read_buf[2].err)) &
6 gen_buf_match[2].part_match &
7 gen_buf_match[2].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T71,T129,T133 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T4,T5 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T6,T202,T148 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T122,T213,T216 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 196
SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
LINE 196
SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[3] | buf_wip[3]) &
4 (read_buf[3].addr == flash_word_addr) &
5 ((~read_buf[3].err)) &
6 gen_buf_match[3].part_match &
7 gen_buf_match[3].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T24,T71,T129 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T4,T5 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T6,T202,T148 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T6,T123,T142 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 196
SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
LINE 196
SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 212
EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T212,T213,T217 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 212
SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 212
EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T127,T215,T217 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 212
SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 212
EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T122,T213,T216 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 212
SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 212
EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T6,T123,T142 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 212
SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 218
EXPRESSION
Number Term
1 (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[0].part_match &
3 gen_buf_match[0].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T44,T218,T84 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 218
SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 218
EXPRESSION
Number Term
1 (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[1].part_match &
3 gen_buf_match[1].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T44,T39,T218 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 218
SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 218
EXPRESSION
Number Term
1 (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[2].part_match &
3 gen_buf_match[2].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T6,T44,T122 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 218
SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 218
EXPRESSION
Number Term
1 (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[3].part_match &
3 gen_buf_match[3].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T6,T44,T123 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 218
SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 222
EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T62,T33 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T62,T33,T71 |
LINE 222
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T33,T71 |
0 | 1 | 0 | Covered | T13,T33,T7 |
1 | 0 | 0 | Covered | T62,T33,T63 |
LINE 222
SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T16,T6,T23 |
1 | 1 | Covered | T13,T33,T7 |
LINE 222
SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T31,T44 |
1 | 1 | Covered | T13,T33,T71 |
LINE 222
EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T44,T62 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T44,T62,T33 |
LINE 222
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T44,T33 |
0 | 1 | 0 | Covered | T13,T33,T7 |
1 | 0 | 0 | Covered | T62,T33,T63 |
LINE 222
SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T16,T6,T23 |
1 | 1 | Covered | T13,T33,T7 |
LINE 222
SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T31,T44 |
1 | 1 | Covered | T13,T44,T33 |
LINE 222
EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T44,T62 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T44,T62,T33 |
LINE 222
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T44,T33 |
0 | 1 | 0 | Covered | T13,T33,T7 |
1 | 0 | 0 | Covered | T62,T33,T63 |
LINE 222
SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T16,T6,T23 |
1 | 1 | Covered | T13,T33,T7 |
LINE 222
SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T31,T44 |
1 | 1 | Covered | T13,T44,T33 |
LINE 222
EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T24,T62 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T24,T62,T33 |
LINE 222
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T33,T71 |
0 | 1 | 0 | Covered | T13,T24,T33 |
1 | 0 | 0 | Covered | T62,T33,T63 |
LINE 222
SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T16,T6,T23 |
1 | 1 | Covered | T13,T24,T33 |
LINE 222
SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T31,T44 |
1 | 1 | Covered | T13,T33,T71 |
LINE 232
EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 239
EXPRESSION (rdy_o & alloc[0])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T148,T208 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 239
EXPRESSION (rdy_o & alloc[1])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T207 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 239
EXPRESSION (rdy_o & alloc[2])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T26 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 239
EXPRESSION (rdy_o & alloc[3])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 291
EXPRESSION (req_o & ack_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T21,T46 |
1 | 1 | Covered | T1,T4,T5 |
LINE 292
EXPRESSION (rd_busy & done_i)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T23,T20 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 302
EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 305
EXPRESSION (req_i && rdy_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 308
EXPRESSION (rsp_fifo_vld & data_valid_o)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 377
EXPRESSION (((~rd_busy)) | rd_done)
------1----- ---2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 382
EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T15,T54 |
1 | 0 | Covered | T15,T54 |
1 | 1 | Covered | T1,T2,T3 |
LINE 393
EXPRESSION (buf_en_q == buf_en_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 399
EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
--------------------------------1------------------------------- -----------2----------- --------3------- -----------------4-----------------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T4,T5,T6 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
----1---
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
--1-- ----2---- ------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T4,T5 |
1 | 1 | 0 | Covered | T6,T26,T20 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T6 |
LINE 407
EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
--1-- --------2------- ----3---- ------4------ ----5--- -----------------6-----------------
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T6,T19 |
1 | 1 | 1 | 0 | 1 | 1 | Covered | T209 |
1 | 1 | 1 | 1 | 0 | 1 | Covered | T1,T5,T6 |
1 | 1 | 1 | 1 | 1 | 0 | Covered | T4,T6,T26 |
1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 407
SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T6 |
LINE 428
EXPRESSION (rd_done && rd_attrs.ecc)
---1--- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T19,T26 |
1 | 1 | Covered | T4,T5,T6 |
LINE 432
EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
---1--- ------------------------2------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T23 |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T4,T31,T28 |
LINE 432
SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T23 |
LINE 442
EXPRESSION (valid_ecc & ecc_multi_err)
----1---- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T19 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T6,T24,T131 |
LINE 451
EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T20,T38 |
LINE 451
SUB-EXPRESSION (data_err | ecc_single_err_o)
----1--- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T20,T38,T39 |
1 | 0 | Covered | T6,T24,T131 |
LINE 456
EXPRESSION (valid_ecc & ecc_single_err)
----1---- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T19,T26 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T20,T38,T39 |
LINE 491
EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
------1------ ------2------ --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T15,T54 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T6,T26,T20 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 494
EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
---1--- ---------2--------- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T1,T6,T19 |
1 | 1 | 0 | Covered | T4,T28,T120 |
1 | 1 | 1 | Covered | T5,T6,T26 |
LINE 497
EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
---1--- ---------2--------- -----3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T31,T120,T123 |
1 | 1 | 0 | Covered | T5,T6,T26 |
1 | 1 | 1 | Covered | T4,T28,T120 |
LINE 501
EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
---1--- ------2----- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T5,T6,T26 |
1 | 1 | 0 | Covered | T6,T26,T219 |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 503
EXPRESSION (fifo_data_valid & descram_q)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T5,T6,T26 |
LINE 504
EXPRESSION (fifo_data_valid & dropmsk_q)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T4,T28,T120 |
LINE 505
EXPRESSION (fifo_data_valid & forward_q)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T26 |
1 | 1 | Covered | T1,T4,T6 |
LINE 513
EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T26 |
LINE 513
SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T26 |
1 | 1 | Covered | T5,T6,T26 |
LINE 513
SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T28,T120 |
LINE 521
EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
------1----- -----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T122,T123 |
1 | 1 | Covered | T1,T4,T6 |
LINE 521
SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T28,T120 |
LINE 523
EXPRESSION (fifo_data_ready | fifo_forward_pop)
-------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T26 |
LINE 597
EXPRESSION (req_o & ack_i & descramble_i)
--1-- --2-- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T6,T21,T46 |
1 | 1 | 0 | Covered | T1,T6,T19 |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 598
EXPRESSION (calc_req_o & calc_ack_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T23,T20,T13 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 614
EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
-------1------- -----2---- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T6,T26,T20 |
1 | 1 | 0 | Covered | T4,T28,T120 |
1 | 1 | 1 | Covered | T5,T6,T26 |
LINE 624
EXPRESSION
Number Term
1 forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 624
SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T26 |
LINE 628
EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 628
SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 636
EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
---1--- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T26 |
1 | 0 | Covered | T1,T4,T6 |
LINE 636
SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T26 |
LINE 654
EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 654
SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T26 |
LINE 654
SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T26 |
LINE 659
EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
------1----- -----2---- --------------------------3-------------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T15,T54 |
1 | 0 | 1 | Covered | T13,T33,T68 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 659
SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
------1------ -----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 659
SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
-----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 664
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T4,T5 |
1 | 1 | 1 | 0 | Covered | T1,T4,T5 |
1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 664
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T4,T5 |
1 | 1 | 1 | 0 | Covered | T1,T4,T5 |
1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 664
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T4,T5 |
1 | 1 | 1 | 0 | Covered | T1,T4,T5 |
1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 664
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T4,T5 |
1 | 1 | 1 | 0 | Covered | T1,T4,T5 |
1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 677
EXPRESSION (buf_rsp_err | read_buf[i].err)
-----1----- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T6 |
0 | 1 | Covered | T205,T203 |
1 | 0 | Not Covered | |
LINE 683
EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T5,T6 |
LINE 736
EXPRESSION (data_err_o ? inv_data_integ : data_out_intg)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T24,T131 |
LINE 747
EXPRESSION (((|buf_rsp_match)) ? buf_addr_xor_muxed : fifo_addr_xor_muxed)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T5,T6 |
LINE 775
EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T6 |
LINE 775
SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
---------------------------------------------1---------------------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T6,T26 |
LINE 787
EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
-------1------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T4,T5 |