| T1079 |
/workspace/coverage/default/1.flash_ctrl_ro_serr.2189435642 |
|
|
Jul 21 06:01:44 PM PDT 24 |
Jul 21 06:03:43 PM PDT 24 |
1125274000 ps |
| T1080 |
/workspace/coverage/default/3.flash_ctrl_hw_sec_otp.559158310 |
|
|
Jul 21 06:01:54 PM PDT 24 |
Jul 21 06:03:20 PM PDT 24 |
4454396000 ps |
| T1081 |
/workspace/coverage/default/47.flash_ctrl_otp_reset.1742359870 |
|
|
Jul 21 06:06:44 PM PDT 24 |
Jul 21 06:08:37 PM PDT 24 |
144202900 ps |
| T1082 |
/workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3840661150 |
|
|
Jul 21 06:01:39 PM PDT 24 |
Jul 21 06:03:11 PM PDT 24 |
10019244200 ps |
| T1083 |
/workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1630949675 |
|
|
Jul 21 06:04:55 PM PDT 24 |
Jul 21 06:08:53 PM PDT 24 |
10016144700 ps |
| T1084 |
/workspace/coverage/default/76.flash_ctrl_connect.3512177049 |
|
|
Jul 21 06:07:18 PM PDT 24 |
Jul 21 06:07:32 PM PDT 24 |
40054300 ps |
| T1085 |
/workspace/coverage/default/1.flash_ctrl_rd_buff_evict.2906854077 |
|
|
Jul 21 06:01:38 PM PDT 24 |
Jul 21 06:03:49 PM PDT 24 |
1448270800 ps |
| T1086 |
/workspace/coverage/default/2.flash_ctrl_smoke.2826729021 |
|
|
Jul 21 06:01:46 PM PDT 24 |
Jul 21 06:04:39 PM PDT 24 |
101475200 ps |
| T1087 |
/workspace/coverage/default/15.flash_ctrl_disable.2305227550 |
|
|
Jul 21 06:04:16 PM PDT 24 |
Jul 21 06:04:38 PM PDT 24 |
14710300 ps |
| T1088 |
/workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.3199250161 |
|
|
Jul 21 06:06:26 PM PDT 24 |
Jul 21 06:06:58 PM PDT 24 |
27311000 ps |
| T1089 |
/workspace/coverage/default/1.flash_ctrl_intr_rd.1588672382 |
|
|
Jul 21 06:01:39 PM PDT 24 |
Jul 21 06:04:05 PM PDT 24 |
1082174800 ps |
| T1090 |
/workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1795555738 |
|
|
Jul 21 06:03:27 PM PDT 24 |
Jul 21 06:05:18 PM PDT 24 |
10017472000 ps |
| T1091 |
/workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.3454599505 |
|
|
Jul 21 06:04:36 PM PDT 24 |
Jul 21 06:04:51 PM PDT 24 |
15914600 ps |
| T54 |
/workspace/coverage/default/4.flash_ctrl_sec_cm.2707477979 |
|
|
Jul 21 06:02:10 PM PDT 24 |
Jul 21 07:21:29 PM PDT 24 |
1021580500 ps |
| T1092 |
/workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.630976669 |
|
|
Jul 21 06:01:46 PM PDT 24 |
Jul 21 06:06:15 PM PDT 24 |
12125967500 ps |
| T1093 |
/workspace/coverage/default/25.flash_ctrl_rw_evict.2575753531 |
|
|
Jul 21 06:05:21 PM PDT 24 |
Jul 21 06:05:53 PM PDT 24 |
36371400 ps |
| T1094 |
/workspace/coverage/default/17.flash_ctrl_prog_reset.3048079710 |
|
|
Jul 21 06:04:36 PM PDT 24 |
Jul 21 06:04:51 PM PDT 24 |
22366700 ps |
| T1095 |
/workspace/coverage/default/2.flash_ctrl_host_addr_infection.2766063546 |
|
|
Jul 21 06:01:52 PM PDT 24 |
Jul 21 06:02:20 PM PDT 24 |
40585700 ps |
| T1096 |
/workspace/coverage/default/15.flash_ctrl_intr_rd.85219065 |
|
|
Jul 21 06:04:15 PM PDT 24 |
Jul 21 06:07:03 PM PDT 24 |
10321748300 ps |
| T1097 |
/workspace/coverage/default/53.flash_ctrl_otp_reset.3557496135 |
|
|
Jul 21 06:06:54 PM PDT 24 |
Jul 21 06:08:47 PM PDT 24 |
40814200 ps |
| T1098 |
/workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2544429260 |
|
|
Jul 21 06:01:35 PM PDT 24 |
Jul 21 06:15:32 PM PDT 24 |
160174183900 ps |
| T1099 |
/workspace/coverage/default/34.flash_ctrl_intr_rd.4138509938 |
|
|
Jul 21 06:06:07 PM PDT 24 |
Jul 21 06:09:38 PM PDT 24 |
3207333400 ps |
| T1100 |
/workspace/coverage/default/2.flash_ctrl_wo.4153288922 |
|
|
Jul 21 06:01:52 PM PDT 24 |
Jul 21 06:04:23 PM PDT 24 |
1946014700 ps |
| T1101 |
/workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.1618645858 |
|
|
Jul 21 06:02:29 PM PDT 24 |
Jul 21 06:05:26 PM PDT 24 |
23882842600 ps |
| T1102 |
/workspace/coverage/default/25.flash_ctrl_alert_test.4205045954 |
|
|
Jul 21 06:05:27 PM PDT 24 |
Jul 21 06:05:41 PM PDT 24 |
63913000 ps |
| T1103 |
/workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.4028854538 |
|
|
Jul 21 06:05:42 PM PDT 24 |
Jul 21 06:10:20 PM PDT 24 |
27800258400 ps |
| T386 |
/workspace/coverage/default/15.flash_ctrl_mp_regions.1035183242 |
|
|
Jul 21 06:04:09 PM PDT 24 |
Jul 21 06:10:18 PM PDT 24 |
41386402600 ps |
| T1104 |
/workspace/coverage/default/1.flash_ctrl_hw_sec_otp.3192682132 |
|
|
Jul 21 06:01:44 PM PDT 24 |
Jul 21 06:04:10 PM PDT 24 |
3399453200 ps |
| T1105 |
/workspace/coverage/default/5.flash_ctrl_sec_info_access.3941484214 |
|
|
Jul 21 06:02:34 PM PDT 24 |
Jul 21 06:03:47 PM PDT 24 |
5543062500 ps |
| T1106 |
/workspace/coverage/default/0.flash_ctrl_re_evict.1759651940 |
|
|
Jul 21 06:01:34 PM PDT 24 |
Jul 21 06:02:11 PM PDT 24 |
225270200 ps |
| T1107 |
/workspace/coverage/default/5.flash_ctrl_intr_wr.3600732488 |
|
|
Jul 21 06:02:27 PM PDT 24 |
Jul 21 06:03:33 PM PDT 24 |
4774947900 ps |
| T1108 |
/workspace/coverage/default/9.flash_ctrl_ro_serr.3954426251 |
|
|
Jul 21 06:03:11 PM PDT 24 |
Jul 21 06:05:01 PM PDT 24 |
497954200 ps |
| T1109 |
/workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.264266226 |
|
|
Jul 21 06:03:37 PM PDT 24 |
Jul 21 06:03:51 PM PDT 24 |
47855000 ps |
| T1110 |
/workspace/coverage/default/3.flash_ctrl_host_dir_rd.1105355250 |
|
|
Jul 21 06:01:55 PM PDT 24 |
Jul 21 06:03:06 PM PDT 24 |
39273700 ps |
| T1111 |
/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.2305760667 |
|
|
Jul 21 06:03:45 PM PDT 24 |
Jul 21 06:03:58 PM PDT 24 |
15592500 ps |
| T1112 |
/workspace/coverage/default/33.flash_ctrl_rw_evict.2073774455 |
|
|
Jul 21 06:06:01 PM PDT 24 |
Jul 21 06:06:33 PM PDT 24 |
107951900 ps |
| T1113 |
/workspace/coverage/default/52.flash_ctrl_otp_reset.1324951434 |
|
|
Jul 21 06:06:52 PM PDT 24 |
Jul 21 06:09:04 PM PDT 24 |
103670700 ps |
| T1114 |
/workspace/coverage/default/11.flash_ctrl_mp_regions.2935846451 |
|
|
Jul 21 06:03:32 PM PDT 24 |
Jul 21 06:09:23 PM PDT 24 |
29208253400 ps |
| T1115 |
/workspace/coverage/default/15.flash_ctrl_prog_reset.3832253215 |
|
|
Jul 21 06:04:19 PM PDT 24 |
Jul 21 06:04:33 PM PDT 24 |
69403000 ps |
| T1116 |
/workspace/coverage/default/42.flash_ctrl_alert_test.4153426915 |
|
|
Jul 21 06:06:31 PM PDT 24 |
Jul 21 06:06:45 PM PDT 24 |
93261000 ps |
| T1117 |
/workspace/coverage/default/11.flash_ctrl_prog_reset.3968167882 |
|
|
Jul 21 06:03:37 PM PDT 24 |
Jul 21 06:03:51 PM PDT 24 |
21925000 ps |
| T1118 |
/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.373589402 |
|
|
Jul 21 06:06:27 PM PDT 24 |
Jul 21 06:07:39 PM PDT 24 |
6052074800 ps |
| T392 |
/workspace/coverage/default/2.flash_ctrl_fs_sup.983481750 |
|
|
Jul 21 06:01:58 PM PDT 24 |
Jul 21 06:02:43 PM PDT 24 |
737360300 ps |
| T1119 |
/workspace/coverage/default/46.flash_ctrl_otp_reset.4279272806 |
|
|
Jul 21 06:06:40 PM PDT 24 |
Jul 21 06:08:30 PM PDT 24 |
40157600 ps |
| T1120 |
/workspace/coverage/default/13.flash_ctrl_sec_info_access.3321226805 |
|
|
Jul 21 06:03:57 PM PDT 24 |
Jul 21 06:05:10 PM PDT 24 |
2622821800 ps |
| T1121 |
/workspace/coverage/default/69.flash_ctrl_otp_reset.3260335757 |
|
|
Jul 21 06:07:09 PM PDT 24 |
Jul 21 06:09:01 PM PDT 24 |
37250000 ps |
| T1122 |
/workspace/coverage/default/2.flash_ctrl_hw_sec_otp.1299303091 |
|
|
Jul 21 06:01:44 PM PDT 24 |
Jul 21 06:03:42 PM PDT 24 |
3051888900 ps |
| T1123 |
/workspace/coverage/default/2.flash_ctrl_alert_test.2317216175 |
|
|
Jul 21 06:02:00 PM PDT 24 |
Jul 21 06:02:15 PM PDT 24 |
53009000 ps |
| T1124 |
/workspace/coverage/default/9.flash_ctrl_mp_regions.163106921 |
|
|
Jul 21 06:03:04 PM PDT 24 |
Jul 21 06:08:38 PM PDT 24 |
44515811200 ps |
| T1125 |
/workspace/coverage/default/8.flash_ctrl_hw_rma_reset.2269697374 |
|
|
Jul 21 06:02:54 PM PDT 24 |
Jul 21 06:17:21 PM PDT 24 |
40122275900 ps |
| T1126 |
/workspace/coverage/default/1.flash_ctrl_prog_reset.3801047715 |
|
|
Jul 21 06:01:44 PM PDT 24 |
Jul 21 06:05:58 PM PDT 24 |
35491741600 ps |
| T1127 |
/workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1514062977 |
|
|
Jul 21 06:05:53 PM PDT 24 |
Jul 21 06:11:04 PM PDT 24 |
13049387100 ps |
| T248 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2569560208 |
|
|
Jul 21 06:43:25 PM PDT 24 |
Jul 21 06:43:39 PM PDT 24 |
254034400 ps |
| T249 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1980283388 |
|
|
Jul 21 06:43:36 PM PDT 24 |
Jul 21 06:43:50 PM PDT 24 |
16368200 ps |
| T1128 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1396392744 |
|
|
Jul 21 06:43:18 PM PDT 24 |
Jul 21 06:43:35 PM PDT 24 |
12552200 ps |
| T96 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.310432794 |
|
|
Jul 21 06:43:34 PM PDT 24 |
Jul 21 06:43:52 PM PDT 24 |
67854500 ps |
| T1129 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.83736927 |
|
|
Jul 21 06:43:43 PM PDT 24 |
Jul 21 06:44:00 PM PDT 24 |
18970100 ps |
| T250 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1915388103 |
|
|
Jul 21 06:43:36 PM PDT 24 |
Jul 21 06:43:50 PM PDT 24 |
16373100 ps |
| T322 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1301536440 |
|
|
Jul 21 06:43:21 PM PDT 24 |
Jul 21 06:43:36 PM PDT 24 |
27013600 ps |
| T321 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3497516581 |
|
|
Jul 21 06:43:27 PM PDT 24 |
Jul 21 06:43:41 PM PDT 24 |
45065900 ps |
| T323 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2833035916 |
|
|
Jul 21 06:43:38 PM PDT 24 |
Jul 21 06:43:52 PM PDT 24 |
29055100 ps |
| T59 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2717121037 |
|
|
Jul 21 06:43:12 PM PDT 24 |
Jul 21 06:43:31 PM PDT 24 |
157427400 ps |
| T1130 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3499236428 |
|
|
Jul 21 06:43:36 PM PDT 24 |
Jul 21 06:43:50 PM PDT 24 |
51205400 ps |
| T60 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.4071718622 |
|
|
Jul 21 06:43:45 PM PDT 24 |
Jul 21 06:44:02 PM PDT 24 |
59058000 ps |
| T61 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2525592697 |
|
|
Jul 21 06:43:17 PM PDT 24 |
Jul 21 06:43:49 PM PDT 24 |
21897600 ps |
| T1131 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1115161535 |
|
|
Jul 21 06:43:30 PM PDT 24 |
Jul 21 06:43:44 PM PDT 24 |
21116400 ps |
| T97 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1015871475 |
|
|
Jul 21 06:43:42 PM PDT 24 |
Jul 21 06:44:00 PM PDT 24 |
104040700 ps |
| T101 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.4210246391 |
|
|
Jul 21 06:43:28 PM PDT 24 |
Jul 21 06:44:13 PM PDT 24 |
1468349600 ps |
| T98 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.668830085 |
|
|
Jul 21 06:43:26 PM PDT 24 |
Jul 21 06:56:07 PM PDT 24 |
3367273900 ps |
| T324 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3053812118 |
|
|
Jul 21 06:43:38 PM PDT 24 |
Jul 21 06:43:53 PM PDT 24 |
17096700 ps |
| T99 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2658868281 |
|
|
Jul 21 06:43:37 PM PDT 24 |
Jul 21 06:43:55 PM PDT 24 |
68188400 ps |
| T1132 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.399896975 |
|
|
Jul 21 06:43:12 PM PDT 24 |
Jul 21 06:43:27 PM PDT 24 |
20449700 ps |
| T320 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.539521474 |
|
|
Jul 21 06:43:18 PM PDT 24 |
Jul 21 06:43:59 PM PDT 24 |
2076179000 ps |
| T1133 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3387039785 |
|
|
Jul 21 06:43:30 PM PDT 24 |
Jul 21 06:43:45 PM PDT 24 |
25753400 ps |
| T100 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2258828972 |
|
|
Jul 21 06:43:13 PM PDT 24 |
Jul 21 06:58:15 PM PDT 24 |
801678900 ps |
| T286 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1660228824 |
|
|
Jul 21 06:43:29 PM PDT 24 |
Jul 21 06:43:44 PM PDT 24 |
46332000 ps |
| T230 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2431293429 |
|
|
Jul 21 06:43:15 PM PDT 24 |
Jul 21 06:43:34 PM PDT 24 |
83695200 ps |
| T1134 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.871930945 |
|
|
Jul 21 06:43:22 PM PDT 24 |
Jul 21 06:43:38 PM PDT 24 |
11261200 ps |
| T236 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.881533672 |
|
|
Jul 21 06:43:21 PM PDT 24 |
Jul 21 06:51:05 PM PDT 24 |
1738135500 ps |
| T349 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3997699098 |
|
|
Jul 21 06:43:20 PM PDT 24 |
Jul 21 06:44:16 PM PDT 24 |
1783402800 ps |
| T1135 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.790735137 |
|
|
Jul 21 06:43:50 PM PDT 24 |
Jul 21 06:44:10 PM PDT 24 |
175652000 ps |
| T1136 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.809509977 |
|
|
Jul 21 06:43:42 PM PDT 24 |
Jul 21 06:43:56 PM PDT 24 |
59435700 ps |
| T1137 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1495511730 |
|
|
Jul 21 06:43:24 PM PDT 24 |
Jul 21 06:43:38 PM PDT 24 |
34067400 ps |
| T1138 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1168096561 |
|
|
Jul 21 06:43:21 PM PDT 24 |
Jul 21 06:43:38 PM PDT 24 |
17529900 ps |
| T231 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3332642042 |
|
|
Jul 21 06:43:32 PM PDT 24 |
Jul 21 06:43:50 PM PDT 24 |
134861100 ps |
| T1139 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1640960838 |
|
|
Jul 21 06:43:38 PM PDT 24 |
Jul 21 06:43:53 PM PDT 24 |
51507500 ps |
| T325 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2537127777 |
|
|
Jul 21 06:43:47 PM PDT 24 |
Jul 21 06:44:02 PM PDT 24 |
32275100 ps |
| T1140 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1152790941 |
|
|
Jul 21 06:43:30 PM PDT 24 |
Jul 21 06:43:44 PM PDT 24 |
27004800 ps |
| T1141 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.215663514 |
|
|
Jul 21 06:43:32 PM PDT 24 |
Jul 21 06:43:45 PM PDT 24 |
27646500 ps |
| T1142 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.4193614440 |
|
|
Jul 21 06:43:37 PM PDT 24 |
Jul 21 06:44:11 PM PDT 24 |
1676502200 ps |
| T1143 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1732412020 |
|
|
Jul 21 06:43:17 PM PDT 24 |
Jul 21 06:43:32 PM PDT 24 |
13938500 ps |
| T348 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1028460705 |
|
|
Jul 21 06:43:20 PM PDT 24 |
Jul 21 06:43:57 PM PDT 24 |
390374600 ps |
| T1144 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3697094808 |
|
|
Jul 21 06:43:46 PM PDT 24 |
Jul 21 06:44:00 PM PDT 24 |
16206700 ps |
| T287 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3808261899 |
|
|
Jul 21 06:43:25 PM PDT 24 |
Jul 21 06:43:42 PM PDT 24 |
914272000 ps |
| T1145 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3109797982 |
|
|
Jul 21 06:43:17 PM PDT 24 |
Jul 21 06:43:38 PM PDT 24 |
609098400 ps |
| T291 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.784263528 |
|
|
Jul 21 06:43:33 PM PDT 24 |
Jul 21 06:43:50 PM PDT 24 |
40217200 ps |
| T1146 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3051102518 |
|
|
Jul 21 06:43:34 PM PDT 24 |
Jul 21 06:44:14 PM PDT 24 |
1299517900 ps |
| T1147 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3625457149 |
|
|
Jul 21 06:43:23 PM PDT 24 |
Jul 21 06:43:40 PM PDT 24 |
21913900 ps |
| T288 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3563174870 |
|
|
Jul 21 06:43:29 PM PDT 24 |
Jul 21 06:43:46 PM PDT 24 |
127396000 ps |
| T1148 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.670303506 |
|
|
Jul 21 06:43:20 PM PDT 24 |
Jul 21 06:43:37 PM PDT 24 |
113021400 ps |
| T1149 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3797769633 |
|
|
Jul 21 06:43:26 PM PDT 24 |
Jul 21 06:43:40 PM PDT 24 |
48822700 ps |
| T1150 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.784975093 |
|
|
Jul 21 06:43:15 PM PDT 24 |
Jul 21 06:43:33 PM PDT 24 |
14962200 ps |
| T1151 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.263831694 |
|
|
Jul 21 06:43:11 PM PDT 24 |
Jul 21 06:43:25 PM PDT 24 |
26424100 ps |
| T1152 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.453076582 |
|
|
Jul 21 06:43:26 PM PDT 24 |
Jul 21 06:43:44 PM PDT 24 |
15007900 ps |
| T1153 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3708910889 |
|
|
Jul 21 06:43:34 PM PDT 24 |
Jul 21 06:43:50 PM PDT 24 |
15468000 ps |
| T232 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2104826487 |
|
|
Jul 21 06:43:23 PM PDT 24 |
Jul 21 06:43:44 PM PDT 24 |
335890200 ps |
| T1154 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3267799754 |
|
|
Jul 21 06:43:19 PM PDT 24 |
Jul 21 06:43:33 PM PDT 24 |
55964300 ps |
| T1155 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.1656309985 |
|
|
Jul 21 06:43:44 PM PDT 24 |
Jul 21 06:43:58 PM PDT 24 |
29459300 ps |
| T233 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3238264467 |
|
|
Jul 21 06:43:15 PM PDT 24 |
Jul 21 06:43:32 PM PDT 24 |
31705000 ps |
| T234 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2772060522 |
|
|
Jul 21 06:43:32 PM PDT 24 |
Jul 21 06:43:49 PM PDT 24 |
45496900 ps |
| T238 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3214073494 |
|
|
Jul 21 06:43:12 PM PDT 24 |
Jul 21 06:43:27 PM PDT 24 |
217403400 ps |
| T1156 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.4109138298 |
|
|
Jul 21 06:43:22 PM PDT 24 |
Jul 21 06:43:40 PM PDT 24 |
14388200 ps |
| T1157 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1047817642 |
|
|
Jul 21 06:43:14 PM PDT 24 |
Jul 21 06:43:30 PM PDT 24 |
11884200 ps |
| T235 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1425916647 |
|
|
Jul 21 06:43:18 PM PDT 24 |
Jul 21 06:43:36 PM PDT 24 |
109132000 ps |
| T289 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.4092100006 |
|
|
Jul 21 06:43:18 PM PDT 24 |
Jul 21 06:43:37 PM PDT 24 |
98195500 ps |
| T255 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2344567960 |
|
|
Jul 21 06:43:02 PM PDT 24 |
Jul 21 06:58:07 PM PDT 24 |
3404494000 ps |
| T341 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1326932920 |
|
|
Jul 21 06:43:31 PM PDT 24 |
Jul 21 06:51:09 PM PDT 24 |
175774400 ps |
| T1158 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.44665131 |
|
|
Jul 21 06:43:28 PM PDT 24 |
Jul 21 06:43:42 PM PDT 24 |
29532900 ps |
| T252 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2604878909 |
|
|
Jul 21 06:43:23 PM PDT 24 |
Jul 21 06:43:43 PM PDT 24 |
90694500 ps |
| T239 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3017396049 |
|
|
Jul 21 06:43:33 PM PDT 24 |
Jul 21 06:43:47 PM PDT 24 |
17520500 ps |
| T1159 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.4094230512 |
|
|
Jul 21 06:43:34 PM PDT 24 |
Jul 21 06:43:55 PM PDT 24 |
67079100 ps |
| T240 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.481373077 |
|
|
Jul 21 06:43:22 PM PDT 24 |
Jul 21 06:43:36 PM PDT 24 |
52773500 ps |
| T258 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2457031506 |
|
|
Jul 21 06:43:14 PM PDT 24 |
Jul 21 06:43:33 PM PDT 24 |
93167400 ps |
| T251 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3215559362 |
|
|
Jul 21 06:43:16 PM PDT 24 |
Jul 21 06:43:32 PM PDT 24 |
102639200 ps |
| T1160 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.600015149 |
|
|
Jul 21 06:43:22 PM PDT 24 |
Jul 21 06:43:38 PM PDT 24 |
54089000 ps |
| T267 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.600690773 |
|
|
Jul 21 06:43:38 PM PDT 24 |
Jul 21 06:58:29 PM PDT 24 |
1338503800 ps |
| T290 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1913805462 |
|
|
Jul 21 06:43:15 PM PDT 24 |
Jul 21 06:43:34 PM PDT 24 |
823739900 ps |
| T1161 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2604571615 |
|
|
Jul 21 06:43:16 PM PDT 24 |
Jul 21 06:43:35 PM PDT 24 |
36992700 ps |
| T1162 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.566770671 |
|
|
Jul 21 06:43:20 PM PDT 24 |
Jul 21 06:43:39 PM PDT 24 |
363205400 ps |
| T1163 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.4189987843 |
|
|
Jul 21 06:43:37 PM PDT 24 |
Jul 21 06:43:52 PM PDT 24 |
28234500 ps |
| T1164 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.4023700173 |
|
|
Jul 21 06:43:12 PM PDT 24 |
Jul 21 06:43:25 PM PDT 24 |
61664300 ps |
| T1165 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.50134061 |
|
|
Jul 21 06:43:12 PM PDT 24 |
Jul 21 06:43:27 PM PDT 24 |
19057100 ps |
| T241 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.661190772 |
|
|
Jul 21 06:43:24 PM PDT 24 |
Jul 21 06:43:38 PM PDT 24 |
58236200 ps |
| T1166 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3655574380 |
|
|
Jul 21 06:43:47 PM PDT 24 |
Jul 21 06:44:02 PM PDT 24 |
20397300 ps |
| T1167 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2815127411 |
|
|
Jul 21 06:43:16 PM PDT 24 |
Jul 21 06:43:35 PM PDT 24 |
100120600 ps |
| T1168 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3880060797 |
|
|
Jul 21 06:43:33 PM PDT 24 |
Jul 21 06:43:47 PM PDT 24 |
29830300 ps |
| T1169 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.911724502 |
|
|
Jul 21 06:43:17 PM PDT 24 |
Jul 21 06:43:38 PM PDT 24 |
57852000 ps |
| T254 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.939671233 |
|
|
Jul 21 06:43:20 PM PDT 24 |
Jul 21 06:43:41 PM PDT 24 |
57789700 ps |
| T292 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.442443383 |
|
|
Jul 21 06:43:27 PM PDT 24 |
Jul 21 06:51:03 PM PDT 24 |
2421062200 ps |
| T259 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1941674460 |
|
|
Jul 21 06:43:21 PM PDT 24 |
Jul 21 06:55:55 PM PDT 24 |
1948293400 ps |
| T1170 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4170473212 |
|
|
Jul 21 06:43:21 PM PDT 24 |
Jul 21 06:43:39 PM PDT 24 |
19372000 ps |
| T293 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.496528137 |
|
|
Jul 21 06:43:19 PM PDT 24 |
Jul 21 06:44:31 PM PDT 24 |
6769296800 ps |
| T1171 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2475048474 |
|
|
Jul 21 06:43:31 PM PDT 24 |
Jul 21 06:43:45 PM PDT 24 |
53641600 ps |
| T1172 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1926240412 |
|
|
Jul 21 06:43:44 PM PDT 24 |
Jul 21 06:43:59 PM PDT 24 |
15797800 ps |
| T294 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3179406396 |
|
|
Jul 21 06:43:21 PM PDT 24 |
Jul 21 06:43:41 PM PDT 24 |
1534830200 ps |
| T1173 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1520581381 |
|
|
Jul 21 06:43:46 PM PDT 24 |
Jul 21 06:44:01 PM PDT 24 |
92056300 ps |
| T1174 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2134611995 |
|
|
Jul 21 06:43:39 PM PDT 24 |
Jul 21 06:44:01 PM PDT 24 |
637412900 ps |
| T1175 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1358082331 |
|
|
Jul 21 06:43:20 PM PDT 24 |
Jul 21 06:43:35 PM PDT 24 |
26522200 ps |
| T1176 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1640071850 |
|
|
Jul 21 06:43:15 PM PDT 24 |
Jul 21 06:43:32 PM PDT 24 |
14050600 ps |
| T1177 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3509655123 |
|
|
Jul 21 06:43:40 PM PDT 24 |
Jul 21 06:43:54 PM PDT 24 |
62425900 ps |
| T1178 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3648273454 |
|
|
Jul 21 06:43:33 PM PDT 24 |
Jul 21 06:43:50 PM PDT 24 |
22293500 ps |
| T339 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3741419893 |
|
|
Jul 21 06:43:22 PM PDT 24 |
Jul 21 06:56:01 PM PDT 24 |
1376972700 ps |
| T1179 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1906622959 |
|
|
Jul 21 06:43:23 PM PDT 24 |
Jul 21 06:43:37 PM PDT 24 |
13588000 ps |
| T1180 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.998590479 |
|
|
Jul 21 06:43:16 PM PDT 24 |
Jul 21 06:43:30 PM PDT 24 |
16760400 ps |
| T295 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1591915018 |
|
|
Jul 21 06:43:16 PM PDT 24 |
Jul 21 06:43:36 PM PDT 24 |
396686400 ps |
| T1181 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3746290494 |
|
|
Jul 21 06:43:45 PM PDT 24 |
Jul 21 06:43:59 PM PDT 24 |
15172400 ps |
| T1182 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3745535360 |
|
|
Jul 21 06:43:20 PM PDT 24 |
Jul 21 06:43:36 PM PDT 24 |
19894400 ps |
| T256 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2919921646 |
|
|
Jul 21 06:43:18 PM PDT 24 |
Jul 21 06:43:38 PM PDT 24 |
194510700 ps |
| T337 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1726327902 |
|
|
Jul 21 06:43:40 PM PDT 24 |
Jul 21 06:43:58 PM PDT 24 |
38273000 ps |
| T1183 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2688026393 |
|
|
Jul 21 06:43:43 PM PDT 24 |
Jul 21 06:43:57 PM PDT 24 |
18128800 ps |
| T1184 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2024181096 |
|
|
Jul 21 06:43:41 PM PDT 24 |
Jul 21 06:43:55 PM PDT 24 |
54626400 ps |
| T1185 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1942563641 |
|
|
Jul 21 06:43:20 PM PDT 24 |
Jul 21 06:43:39 PM PDT 24 |
95825800 ps |
| T1186 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3509639677 |
|
|
Jul 21 06:43:28 PM PDT 24 |
Jul 21 06:43:41 PM PDT 24 |
21302400 ps |
| T340 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2387189470 |
|
|
Jul 21 06:43:20 PM PDT 24 |
Jul 21 06:51:06 PM PDT 24 |
339250000 ps |
| T1187 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3783949876 |
|
|
Jul 21 06:43:26 PM PDT 24 |
Jul 21 06:43:40 PM PDT 24 |
24077800 ps |
| T264 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3493563099 |
|
|
Jul 21 06:43:14 PM PDT 24 |
Jul 21 06:58:02 PM PDT 24 |
3229622800 ps |
| T253 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.320691279 |
|
|
Jul 21 06:43:25 PM PDT 24 |
Jul 21 06:43:46 PM PDT 24 |
723526300 ps |
| T1188 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3908440450 |
|
|
Jul 21 06:43:16 PM PDT 24 |
Jul 21 06:43:52 PM PDT 24 |
235934100 ps |
| T1189 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2744919308 |
|
|
Jul 21 06:43:38 PM PDT 24 |
Jul 21 06:43:53 PM PDT 24 |
16551500 ps |
| T1190 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2168720809 |
|
|
Jul 21 06:43:24 PM PDT 24 |
Jul 21 06:43:37 PM PDT 24 |
32852400 ps |
| T1191 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2517092930 |
|
|
Jul 21 06:43:39 PM PDT 24 |
Jul 21 06:43:58 PM PDT 24 |
124490500 ps |
| T1192 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1132509106 |
|
|
Jul 21 06:43:25 PM PDT 24 |
Jul 21 06:43:38 PM PDT 24 |
17853400 ps |
| T1193 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3102890556 |
|
|
Jul 21 06:43:32 PM PDT 24 |
Jul 21 06:43:46 PM PDT 24 |
42584600 ps |
| T1194 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3220488431 |
|
|
Jul 21 06:43:31 PM PDT 24 |
Jul 21 06:43:45 PM PDT 24 |
17953200 ps |
| T296 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3271335803 |
|
|
Jul 21 06:43:47 PM PDT 24 |
Jul 21 06:44:04 PM PDT 24 |
115394900 ps |
| T1195 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1121400720 |
|
|
Jul 21 06:43:48 PM PDT 24 |
Jul 21 06:44:03 PM PDT 24 |
80898500 ps |
| T260 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1317315534 |
|
|
Jul 21 06:43:20 PM PDT 24 |
Jul 21 06:43:38 PM PDT 24 |
70827000 ps |
| T268 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.346540195 |
|
|
Jul 21 06:43:34 PM PDT 24 |
Jul 21 06:43:52 PM PDT 24 |
181408000 ps |
| T1196 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2030412554 |
|
|
Jul 21 06:43:31 PM PDT 24 |
Jul 21 06:43:44 PM PDT 24 |
23940300 ps |
| T1197 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2959275687 |
|
|
Jul 21 06:43:43 PM PDT 24 |
Jul 21 06:43:57 PM PDT 24 |
39885000 ps |
| T1198 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3749403067 |
|
|
Jul 21 06:43:31 PM PDT 24 |
Jul 21 06:43:47 PM PDT 24 |
11682700 ps |
| T1199 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1990493052 |
|
|
Jul 21 06:43:28 PM PDT 24 |
Jul 21 06:43:46 PM PDT 24 |
48836800 ps |
| T1200 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3347281305 |
|
|
Jul 21 06:43:36 PM PDT 24 |
Jul 21 06:43:55 PM PDT 24 |
88883500 ps |
| T1201 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3908366842 |
|
|
Jul 21 06:43:31 PM PDT 24 |
Jul 21 06:43:45 PM PDT 24 |
14340700 ps |
| T1202 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.658929430 |
|
|
Jul 21 06:43:50 PM PDT 24 |
Jul 21 06:44:04 PM PDT 24 |
14353200 ps |
| T1203 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.714544326 |
|
|
Jul 21 06:43:36 PM PDT 24 |
Jul 21 06:43:54 PM PDT 24 |
222474800 ps |
| T1204 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.496266666 |
|
|
Jul 21 06:43:19 PM PDT 24 |
Jul 21 06:43:35 PM PDT 24 |
32885200 ps |
| T1205 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1830058634 |
|
|
Jul 21 06:43:22 PM PDT 24 |
Jul 21 06:43:38 PM PDT 24 |
36282400 ps |
| T297 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3898611813 |
|
|
Jul 21 06:43:10 PM PDT 24 |
Jul 21 06:43:57 PM PDT 24 |
92345700 ps |
| T262 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1382694331 |
|
|
Jul 21 06:43:24 PM PDT 24 |
Jul 21 06:43:41 PM PDT 24 |
111268900 ps |
| T1206 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3151870806 |
|
|
Jul 21 06:43:21 PM PDT 24 |
Jul 21 06:43:40 PM PDT 24 |
311744000 ps |
| T1207 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.4280659131 |
|
|
Jul 21 06:43:42 PM PDT 24 |
Jul 21 06:43:56 PM PDT 24 |
22926100 ps |
| T1208 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1600265739 |
|
|
Jul 21 06:43:37 PM PDT 24 |
Jul 21 06:43:51 PM PDT 24 |
18534200 ps |
| T1209 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2818451613 |
|
|
Jul 21 06:43:12 PM PDT 24 |
Jul 21 06:43:27 PM PDT 24 |
48833400 ps |
| T1210 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2791194228 |
|
|
Jul 21 06:43:21 PM PDT 24 |
Jul 21 06:43:39 PM PDT 24 |
326817700 ps |
| T1211 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3292574292 |
|
|
Jul 21 06:43:13 PM PDT 24 |
Jul 21 06:43:29 PM PDT 24 |
767583200 ps |
| T1212 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2783264280 |
|
|
Jul 21 06:43:10 PM PDT 24 |
Jul 21 06:43:49 PM PDT 24 |
415932900 ps |
| T1213 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.824852705 |
|
|
Jul 21 06:43:34 PM PDT 24 |
Jul 21 06:43:48 PM PDT 24 |
27406600 ps |
| T1214 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3086962308 |
|
|
Jul 21 06:43:46 PM PDT 24 |
Jul 21 06:44:04 PM PDT 24 |
232845200 ps |
| T257 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3681759361 |
|
|
Jul 21 06:43:38 PM PDT 24 |
Jul 21 06:43:56 PM PDT 24 |
40699900 ps |
| T263 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2289682707 |
|
|
Jul 21 06:43:36 PM PDT 24 |
Jul 21 06:58:36 PM PDT 24 |
326871700 ps |
| T338 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.956047443 |
|
|
Jul 21 06:43:22 PM PDT 24 |
Jul 21 06:58:35 PM PDT 24 |
2978931700 ps |
| T1215 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.700880697 |
|
|
Jul 21 06:43:53 PM PDT 24 |
Jul 21 06:44:07 PM PDT 24 |
25209000 ps |
| T1216 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.823632263 |
|
|
Jul 21 06:43:20 PM PDT 24 |
Jul 21 06:43:56 PM PDT 24 |
346549100 ps |
| T1217 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2935879924 |
|
|
Jul 21 06:43:30 PM PDT 24 |
Jul 21 06:43:49 PM PDT 24 |
318703600 ps |
| T342 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1027711232 |
|
|
Jul 21 06:43:28 PM PDT 24 |
Jul 21 06:51:06 PM PDT 24 |
967641800 ps |
| T1218 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1390457186 |
|
|
Jul 21 06:43:12 PM PDT 24 |
Jul 21 06:43:28 PM PDT 24 |
123478500 ps |
| T1219 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.4233414371 |
|
|
Jul 21 06:43:31 PM PDT 24 |
Jul 21 06:43:51 PM PDT 24 |
730006000 ps |
| T1220 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3312534955 |
|
|
Jul 21 06:43:22 PM PDT 24 |
Jul 21 06:43:54 PM PDT 24 |
27667300 ps |
| T246 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1956280370 |
|
|
Jul 21 06:43:22 PM PDT 24 |
Jul 21 06:43:43 PM PDT 24 |
123984800 ps |
| T1221 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1808672040 |
|
|
Jul 21 06:43:46 PM PDT 24 |
Jul 21 06:44:05 PM PDT 24 |
126362300 ps |
| T1222 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.951405490 |
|
|
Jul 21 06:43:35 PM PDT 24 |
Jul 21 06:43:49 PM PDT 24 |
27443500 ps |
| T1223 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1449050488 |
|
|
Jul 21 06:43:16 PM PDT 24 |
Jul 21 06:43:33 PM PDT 24 |
13479700 ps |
| T1224 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.351030024 |
|
|
Jul 21 06:43:20 PM PDT 24 |
Jul 21 06:43:37 PM PDT 24 |
139395000 ps |
| T1225 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2655647389 |
|
|
Jul 21 06:43:23 PM PDT 24 |
Jul 21 06:43:40 PM PDT 24 |
41412700 ps |
| T1226 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3220723819 |
|
|
Jul 21 06:43:34 PM PDT 24 |
Jul 21 06:43:48 PM PDT 24 |
79638400 ps |
| T1227 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1582101441 |
|
|
Jul 21 06:43:17 PM PDT 24 |
Jul 21 06:43:36 PM PDT 24 |
27011400 ps |
| T1228 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4092811708 |
|
|
Jul 21 06:43:11 PM PDT 24 |
Jul 21 06:43:26 PM PDT 24 |
15877100 ps |
| T1229 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.4227113916 |
|
|
Jul 21 06:43:25 PM PDT 24 |
Jul 21 06:43:39 PM PDT 24 |
30208300 ps |
| T1230 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.4293936483 |
|
|
Jul 21 06:43:37 PM PDT 24 |
Jul 21 06:58:22 PM PDT 24 |
1796612100 ps |
| T1231 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2682474125 |
|
|
Jul 21 06:43:14 PM PDT 24 |
Jul 21 06:43:30 PM PDT 24 |
83962200 ps |
| T1232 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1953803459 |
|
|
Jul 21 06:43:17 PM PDT 24 |
Jul 21 06:43:33 PM PDT 24 |
33714100 ps |
| T1233 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2808949530 |
|
|
Jul 21 06:43:44 PM PDT 24 |
Jul 21 06:44:01 PM PDT 24 |
12507600 ps |
| T265 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.811078429 |
|
|
Jul 21 06:43:14 PM PDT 24 |
Jul 21 06:43:33 PM PDT 24 |
188355900 ps |
| T298 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.926808580 |
|
|
Jul 21 06:43:22 PM PDT 24 |
Jul 21 06:44:34 PM PDT 24 |
19847550000 ps |
| T1234 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.585777372 |
|
|
Jul 21 06:43:25 PM PDT 24 |
Jul 21 06:43:55 PM PDT 24 |
111902800 ps |
| T1235 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2219677200 |
|
|
Jul 21 06:43:00 PM PDT 24 |
Jul 21 06:43:17 PM PDT 24 |
24652300 ps |
| T1236 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.719625248 |
|
|
Jul 21 06:43:38 PM PDT 24 |
Jul 21 06:44:15 PM PDT 24 |
160688900 ps |
| T299 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1069956566 |
|
|
Jul 21 06:43:15 PM PDT 24 |
Jul 21 06:43:34 PM PDT 24 |
366813000 ps |
| T1237 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.874993433 |
|
|
Jul 21 06:43:29 PM PDT 24 |
Jul 21 06:43:42 PM PDT 24 |
23997600 ps |
| T1238 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1144599668 |
|
|
Jul 21 06:43:13 PM PDT 24 |
Jul 21 06:43:28 PM PDT 24 |
15156500 ps |
| T1239 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.800594830 |
|
|
Jul 21 06:43:24 PM PDT 24 |
Jul 21 06:43:37 PM PDT 24 |
32132300 ps |
| T1240 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.741928082 |
|
|
Jul 21 06:43:33 PM PDT 24 |
Jul 21 06:43:48 PM PDT 24 |
157507200 ps |
| T1241 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1838042664 |
|
|
Jul 21 06:43:35 PM PDT 24 |
Jul 21 06:43:49 PM PDT 24 |
48170500 ps |
| T261 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1519048723 |
|
|
Jul 21 06:43:20 PM PDT 24 |
Jul 21 06:43:43 PM PDT 24 |
246730500 ps |
| T1242 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.289652031 |
|
|
Jul 21 06:43:15 PM PDT 24 |
Jul 21 06:43:34 PM PDT 24 |
24451600 ps |
| T1243 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.4184962794 |
|
|
Jul 21 06:42:59 PM PDT 24 |
Jul 21 06:43:14 PM PDT 24 |
17685800 ps |
| T1244 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.446909530 |
|
|
Jul 21 06:43:31 PM PDT 24 |
Jul 21 06:43:47 PM PDT 24 |
45788300 ps |
| T1245 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3768988706 |
|
|
Jul 21 06:43:32 PM PDT 24 |
Jul 21 06:43:46 PM PDT 24 |
47697200 ps |
| T1246 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1891704197 |
|
|
Jul 21 06:43:30 PM PDT 24 |
Jul 21 06:43:45 PM PDT 24 |
26007000 ps |
| T1247 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3980947002 |
|
|
Jul 21 06:43:28 PM PDT 24 |
Jul 21 06:43:42 PM PDT 24 |
28202200 ps |
| T1248 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1224171140 |
|
|
Jul 21 06:43:37 PM PDT 24 |
Jul 21 06:51:12 PM PDT 24 |
612787200 ps |
| T1249 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2885614184 |
|
|
Jul 21 06:43:20 PM PDT 24 |
Jul 21 06:51:01 PM PDT 24 |
734441500 ps |
| T1250 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2603489370 |
|
|
Jul 21 06:43:17 PM PDT 24 |
Jul 21 06:43:32 PM PDT 24 |
15427700 ps |
| T300 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1789708345 |
|
|
Jul 21 06:43:22 PM PDT 24 |
Jul 21 06:43:59 PM PDT 24 |
420578400 ps |
| T1251 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.971902362 |
|
|
Jul 21 06:43:18 PM PDT 24 |
Jul 21 06:43:38 PM PDT 24 |
414742700 ps |
| T1252 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1730264482 |
|
|
Jul 21 06:43:35 PM PDT 24 |
Jul 21 06:43:50 PM PDT 24 |
35812800 ps |
| T1253 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3447900862 |
|
|
Jul 21 06:43:40 PM PDT 24 |
Jul 21 06:43:54 PM PDT 24 |
15308600 ps |
| T1254 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2581696881 |
|
|
Jul 21 06:43:20 PM PDT 24 |
Jul 21 06:43:35 PM PDT 24 |
43268700 ps |
| T1255 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2988721980 |
|
|
Jul 21 06:43:21 PM PDT 24 |
Jul 21 06:43:37 PM PDT 24 |
105542100 ps |