SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 97.22 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block] | 91.67 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
91.67 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 2 | 12 | 91.67 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 1 | 3 | 75.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 83137 | 0 | T66 | 2688 | T67 | 123 | T68 | 943 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 1 | 3 | 75.00 |
NAME | COUNT | AT LEAST | NUMBER |
values[2] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 82935 | 1 | T66 | 2688 | T67 | 123 | T68 | 943 | |||
values[1] | 26 | 1 | T225 | 3 | T226 | 1 | T269 | 6 | |||
values[3] | 96 | 1 | T225 | 3 | T244 | 5 | T226 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 82944 | 1 | T66 | 2688 | T67 | 123 | T68 | 943 | |||
values[1] | 24 | 1 | T244 | 1 | T226 | 1 | T269 | 1 | |||
values[2] | 9 | 1 | T225 | 1 | T244 | 1 | T269 | 3 | |||
values[3] | 93 | 1 | T225 | 9 | T244 | 5 | T226 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 82837 | 1 | T66 | 2688 | T67 | 123 | T68 | 943 | |||
auto[TlIntgErrCmd] | 107 | 1 | T225 | 5 | T244 | 2 | T226 | 3 | |||
auto[TlIntgErrData] | 98 | 1 | T225 | 9 | T244 | 4 | T226 | 4 | |||
auto[TlIntgErrBoth] | 95 | 1 | T225 | 6 | T244 | 4 | T226 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 30471257 | 1 | T1 | 105957 | T2 | 2089 | T3 | 989 | |||
auto[1] | 5335592 | 1 | T1 | 7878 | T2 | 152 | T18 | 7076 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 35806643 | 1 | T1 | 113835 | T2 | 2241 | T3 | 989 | |||
values[1] | 24 | 1 | T244 | 1 | T243 | 1 | T269 | 2 | |||
values[2] | 4 | 1 | T244 | 1 | T269 | 1 | T365 | 1 | |||
values[3] | 105 | 1 | T225 | 7 | T244 | 2 | T226 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 35806649 | 1 | T1 | 113835 | T2 | 2241 | T3 | 989 | |||
values[1] | 19 | 1 | T225 | 3 | T244 | 1 | T269 | 1 | |||
values[2] | 4 | 1 | T243 | 1 | T269 | 1 | T365 | 1 | |||
values[3] | 102 | 1 | T225 | 8 | T244 | 3 | T226 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 35806549 | 1 | T1 | 113835 | T2 | 2241 | T3 | 989 | |||
auto[TlIntgErrCmd] | 100 | 1 | T225 | 6 | T244 | 5 | T226 | 6 | |||
auto[TlIntgErrData] | 94 | 1 | T225 | 5 | T244 | 3 | T226 | 2 | |||
auto[TlIntgErrBoth] | 106 | 1 | T225 | 9 | T244 | 2 | T226 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | |||
auto[1] | 4050263 | 0 | T2 | 23 | T3 | 15932 | T20 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4050088 | 1 | T2 | 23 | T3 | 15932 | T20 | 11 | |||
values[1] | 14 | 1 | T225 | 1 | T226 | 1 | T274 | 1 | |||
values[2] | 3 | 1 | T366 | 2 | T367 | 1 | - | - | |||
values[3] | 96 | 1 | T225 | 6 | T244 | 5 | T226 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4050068 | 1 | T2 | 23 | T3 | 15932 | T20 | 11 | |||
values[1] | 14 | 1 | T269 | 2 | T274 | 2 | T368 | 3 | |||
values[2] | 6 | 1 | T269 | 1 | T369 | 1 | T266 | 1 | |||
values[3] | 108 | 1 | T225 | 8 | T244 | 3 | T226 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 4049988 | 1 | T2 | 23 | T3 | 15932 | T20 | 11 | |||
auto[TlIntgErrCmd] | 80 | 1 | T225 | 5 | T244 | 4 | T226 | 4 | |||
auto[TlIntgErrData] | 100 | 1 | T225 | 8 | T244 | 1 | T226 | 4 | |||
auto[TlIntgErrBoth] | 95 | 1 | T225 | 6 | T244 | 4 | T226 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |