Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 97.92 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 95.83 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 1 15 93.75


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 1 15 93.75 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 27760212 1 T1 101581 T2 1938 T3 946
full_word 8046637 1 T1 12254 T2 303 T3 43


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 35806549 1 T1 113835 T2 2241 T3 989
auto[TlIntgErrCmd] 100 1 T225 6 T244 5 T226 6
auto[TlIntgErrData] 94 1 T225 5 T244 3 T226 2
auto[TlIntgErrBoth] 106 1 T225 9 T244 2 T226 2


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31251531 1 T1 101177 T2 2065 T3 942
auto[1] 4555318 1 T1 12658 T2 176 T3 47


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 1 15 93.75 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrData]] [full_word] [auto[1]] 0 1 1


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 27048069 1 T1 100380 T2 1893 T3 941
auto[TlIntgErrNone] partial auto[1] 711866 1 T1 1201 T2 45 T3 5
auto[TlIntgErrNone] full_word auto[0] 4203307 1 T1 797 T2 172 T3 1
auto[TlIntgErrNone] full_word auto[1] 3843307 1 T1 11457 T2 131 T3 42
auto[TlIntgErrCmd] partial auto[0] 48 1 T225 5 T244 5 T226 4
auto[TlIntgErrCmd] partial auto[1] 41 1 T226 2 T243 1 T269 5
auto[TlIntgErrCmd] full_word auto[0] 4 1 T225 1 T370 1 T365 1
auto[TlIntgErrCmd] full_word auto[1] 7 1 T264 1 T274 1 T371 1
auto[TlIntgErrData] partial auto[0] 49 1 T225 2 T244 2 T226 1
auto[TlIntgErrData] partial auto[1] 42 1 T225 2 T244 1 T226 1
auto[TlIntgErrData] full_word auto[0] 3 1 T225 1 T372 1 T373 1
auto[TlIntgErrBoth] partial auto[0] 47 1 T225 3 T244 1 T226 1
auto[TlIntgErrBoth] partial auto[1] 50 1 T225 5 T244 1 T226 1
auto[TlIntgErrBoth] full_word auto[0] 4 1 T269 1 T368 1 T371 1
auto[TlIntgErrBoth] full_word auto[1] 5 1 T225 1 T243 1 T366 1


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 23076 1 T68 583 T103 175 T104 44
full_word 4027187 1 T2 23 T3 15932 T20 11


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 4049988 1 T2 23 T3 15932 T20 11
auto[TlIntgErrCmd] 80 1 T225 5 T244 4 T226 4
auto[TlIntgErrData] 100 1 T225 8 T244 1 T226 4
auto[TlIntgErrBoth] 95 1 T225 6 T244 4 T226 2


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4020462 1 T2 23 T3 15932 T20 11
auto[1] 29801 1 T68 686 T103 214 T104 52


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1589 1 T68 47 T103 12 T104 4
auto[TlIntgErrNone] partial auto[1] 21239 1 T68 536 T103 163 T104 40
auto[TlIntgErrNone] full_word auto[0] 4018765 1 T2 23 T3 15932 T20 11
auto[TlIntgErrNone] full_word auto[1] 8395 1 T68 150 T103 51 T104 12
auto[TlIntgErrCmd] partial auto[0] 23 1 T225 2 T244 1 T264 1
auto[TlIntgErrCmd] partial auto[1] 53 1 T225 3 T244 2 T226 3
auto[TlIntgErrCmd] full_word auto[0] 2 1 T226 1 T374 1 - -
auto[TlIntgErrCmd] full_word auto[1] 2 1 T244 1 T372 1 - -
auto[TlIntgErrData] partial auto[0] 40 1 T225 4 T226 2 T243 3
auto[TlIntgErrData] partial auto[1] 47 1 T225 3 T244 1 T226 2
auto[TlIntgErrData] full_word auto[0] 8 1 T269 2 T368 1 T371 1
auto[TlIntgErrData] full_word auto[1] 5 1 T225 1 T243 1 T269 1
auto[TlIntgErrBoth] partial auto[0] 31 1 T225 2 T244 2 T269 3
auto[TlIntgErrBoth] partial auto[1] 54 1 T225 3 T244 2 T226 2
auto[TlIntgErrBoth] full_word auto[0] 4 1 T264 1 T368 1 T365 1
auto[TlIntgErrBoth] full_word auto[1] 6 1 T225 1 T269 1 T371 1

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