SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 97.62 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if | 83.33 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_iso_part_sw_rd_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_iso_part_sw_wr_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_nvm_debug_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_owner_seed_sw_rw_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER |
others[1] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 4 | 1 | T377 | 1 | T378 | 1 | T379 | 1 | |||
others[2] | 4 | 1 | T203 | 1 | T380 | 1 | T343 | 1 | |||
others[3] | 6 | 1 | T76 | 1 | T381 | 1 | T382 | 1 | |||
false | 12760 | 1 | T1 | 1 | T2 | 2 | T3 | 2 | |||
true | 7 | 1 | T11 | 1 | T97 | 1 | T98 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 84 | 1 | T5 | 1 | T31 | 2 | T32 | 2 | |||
others[1] | 78 | 1 | T5 | 2 | T31 | 2 | T32 | 2 | |||
others[2] | 78 | 1 | T5 | 2 | T32 | 3 | T46 | 1 | |||
others[3] | 135 | 1 | T5 | 3 | T31 | 3 | T32 | 3 | |||
false | 29412 | 1 | T3 | 2 | T17 | 11 | T18 | 1 | |||
true | 24427 | 1 | T1 | 2 | T2 | 3 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 2565 | 1 | T5 | 1 | T31 | 1 | T46 | 1 | |||
others[1] | 2611 | 1 | T5 | 1 | T31 | 1 | T32 | 1 | |||
others[2] | 2585 | 1 | T46 | 1 | T96 | 21 | T99 | 26 | |||
others[3] | 4359 | 1 | T5 | 1 | T31 | 2 | T46 | 3 | |||
false | 7285 | 1 | T17 | 11 | T18 | 1 | T4 | 1 | |||
true | 1570 | 1 | T1 | 2 | T2 | 3 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 2690 | 1 | T5 | 1 | T31 | 1 | T32 | 2 | |||
others[1] | 2528 | 1 | T31 | 1 | T32 | 1 | T69 | 2 | |||
others[2] | 2590 | 1 | T5 | 1 | T31 | 1 | T32 | 2 | |||
others[3] | 4212 | 1 | T31 | 2 | T32 | 1 | T46 | 1 | |||
false | 7394 | 1 | T17 | 11 | T18 | 1 | T4 | 1 | |||
true | 1570 | 1 | T1 | 2 | T2 | 3 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 2521 | 1 | T96 | 18 | T99 | 26 | T100 | 22 | |||
others[1] | 2550 | 1 | T69 | 2 | T96 | 33 | T99 | 47 | |||
others[2] | 2477 | 1 | T96 | 28 | T99 | 26 | T383 | 1 | |||
others[3] | 4405 | 1 | T101 | 1 | T96 | 32 | T99 | 51 | |||
false | 7839 | 1 | T1 | 1 | T2 | 2 | T3 | 2 | |||
true | 42 | 1 | T102 | 1 | T114 | 1 | T141 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 84 | 1 | T5 | 1 | T31 | 1 | T32 | 2 | |||
others[1] | 84 | 1 | T5 | 4 | T31 | 1 | T32 | 3 | |||
others[2] | 77 | 1 | T5 | 1 | T31 | 3 | T32 | 1 | |||
others[3] | 124 | 1 | T5 | 3 | T31 | 2 | T32 | 1 | |||
false | 29441 | 1 | T1 | 1 | T3 | 2 | T17 | 11 | |||
true | 24568 | 1 | T1 | 1 | T2 | 3 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 8407 | 1 | T69 | 1 | T96 | 69 | T99 | 121 | |||
others[1] | 8448 | 1 | T69 | 2 | T96 | 76 | T99 | 92 | |||
others[2] | 8387 | 1 | T69 | 3 | T96 | 74 | T99 | 101 | |||
others[3] | 13866 | 1 | T17 | 3 | T69 | 5 | T96 | 121 | |||
false | 4414 | 1 | T69 | 6 | T96 | 45 | T99 | 44 | |||
true | 20397 | 1 | T1 | 1 | T2 | 2 | T3 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |