Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T19

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1610178096	1606709756	0	0
CheckNGreaterZero_A	4176	4176	0	0
GntImpliesReady_A	1610178096	409927734	0	0
GntImpliesValid_A	1610178096	409927734	0	0
GrantKnown_A	1610178096	1606709756	0	0
IdxKnown_A	1610178096	1606709756	0	0
IndexIsCorrect_A	1610178096	409927734	0	0
NoReadyValidNoGrant_A	1610178096	176414507	0	0
Priority_A	1610178096	434172715	0	0
ReadyAndValidImplyGrant_A	1610178096	409927734	0	0
ReqAndReadyImplyGrant_A	1610178096	409927734	0	0
ReqImpliesValid_A	1610178096	434172715	0	0
ValidKnown_A	1610178096	1606709756	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610178096	1606709756	0	0
T1	914992	914616	0	0
T2	22916	22256	0	0
T3	2237112	2236500	0	0
T4	288524	288312	0	0
T11	4408	4176	0	0
T12	14492	11860	0	0
T16	11176	10896	0	0
T17	13508	10696	0	0
T18	865120	864784	0	0
T19	24952	23032	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4176	4176	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T11	4	4	0	0
T12	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610178096	409927734	0	0
T1	914992	405960	0	0
T2	22916	6198	0	0
T3	2237112	31938	0	0
T4	288524	135698	0	0
T6	0	20420	0	0
T11	4408	76	0	0
T12	14492	384	0	0
T16	11176	64	0	0
T17	13508	232	0	0
T18	865120	386284	0	0
T19	24952	1384	0	0
T20	0	130	0	0
T38	0	12270	0	0
T42	0	152	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610178096	409927734	0	0
T1	914992	405960	0	0
T2	22916	6198	0	0
T3	2237112	31938	0	0
T4	288524	135698	0	0
T6	0	20420	0	0
T11	4408	76	0	0
T12	14492	384	0	0
T16	11176	64	0	0
T17	13508	232	0	0
T18	865120	386284	0	0
T19	24952	1384	0	0
T20	0	130	0	0
T38	0	12270	0	0
T42	0	152	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610178096	1606709756	0	0
T1	914992	914616	0	0
T2	22916	22256	0	0
T3	2237112	2236500	0	0
T4	288524	288312	0	0
T11	4408	4176	0	0
T12	14492	11860	0	0
T16	11176	10896	0	0
T17	13508	10696	0	0
T18	865120	864784	0	0
T19	24952	23032	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610178096	1606709756	0	0
T1	914992	914616	0	0
T2	22916	22256	0	0
T3	2237112	2236500	0	0
T4	288524	288312	0	0
T11	4408	4176	0	0
T12	14492	11860	0	0
T16	11176	10896	0	0
T17	13508	10696	0	0
T18	865120	864784	0	0
T19	24952	23032	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610178096	409927734	0	0
T1	914992	405960	0	0
T2	22916	6198	0	0
T3	2237112	31938	0	0
T4	288524	135698	0	0
T6	0	20420	0	0
T11	4408	76	0	0
T12	14492	384	0	0
T16	11176	64	0	0
T17	13508	232	0	0
T18	865120	386284	0	0
T19	24952	1384	0	0
T20	0	130	0	0
T38	0	12270	0	0
T42	0	152	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610178096	176414507	0	0
T1	457496	256	0	0
T2	22916	1302	0	0
T3	2237112	1136218	0	0
T4	288524	508	0	0
T5	495478	0	0	0
T6	0	59768	0	0
T7	0	529876	0	0
T11	4408	286	0	0
T12	14492	1536	0	0
T16	11176	256	0	0
T17	13508	924	0	0
T18	865120	256	0	0
T19	24952	3304	0	0
T20	0	16	0	0
T26	0	1250164	0	0
T38	0	1212	0	0
T42	0	52	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610178096	434172715	0	0
T1	914992	405960	0	0
T2	22916	6198	0	0
T3	2237112	510616	0	0
T4	288524	135698	0	0
T6	0	22050	0	0
T11	4408	76	0	0
T12	14492	384	0	0
T16	11176	64	0	0
T17	13508	232	0	0
T18	865120	386284	0	0
T19	24952	1384	0	0
T20	0	130	0	0
T38	0	12270	0	0
T42	0	152	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610178096	409927734	0	0
T1	914992	405960	0	0
T2	22916	6198	0	0
T3	2237112	31938	0	0
T4	288524	135698	0	0
T6	0	20420	0	0
T11	4408	76	0	0
T12	14492	384	0	0
T16	11176	64	0	0
T17	13508	232	0	0
T18	865120	386284	0	0
T19	24952	1384	0	0
T20	0	130	0	0
T38	0	12270	0	0
T42	0	152	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610178096	409927734	0	0
T1	914992	405960	0	0
T2	22916	6198	0	0
T3	2237112	31938	0	0
T4	288524	135698	0	0
T6	0	20420	0	0
T11	4408	76	0	0
T12	14492	384	0	0
T16	11176	64	0	0
T17	13508	232	0	0
T18	865120	386284	0	0
T19	24952	1384	0	0
T20	0	130	0	0
T38	0	12270	0	0
T42	0	152	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610178096	434172715	0	0
T1	914992	405960	0	0
T2	22916	6198	0	0
T3	2237112	510616	0	0
T4	288524	135698	0	0
T6	0	22050	0	0
T11	4408	76	0	0
T12	14492	384	0	0
T16	11176	64	0	0
T17	13508	232	0	0
T18	865120	386284	0	0
T19	24952	1384	0	0
T20	0	130	0	0
T38	0	12270	0	0
T42	0	152	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610178096	1606709756	0	0
T1	914992	914616	0	0
T2	22916	22256	0	0
T3	2237112	2236500	0	0
T4	288524	288312	0	0
T11	4408	4176	0	0
T12	14492	11860	0	0
T16	11176	10896	0	0
T17	13508	10696	0	0
T18	865120	864784	0	0
T19	24952	23032	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402544524	401677439	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	402544524	103712053	0	0
GntImpliesValid_A	402544524	103712053	0	0
GrantKnown_A	402544524	401677439	0	0
IdxKnown_A	402544524	401677439	0	0
IndexIsCorrect_A	402544524	103712053	0	0
NoReadyValidNoGrant_A	402544524	45114126	0	0
Priority_A	402544524	109761608	0	0
ReadyAndValidImplyGrant_A	402544524	103712053	0	0
ReqAndReadyImplyGrant_A	402544524	103712053	0	0
ReqImpliesValid_A	402544524	109761608	0	0
ValidKnown_A	402544524	401677439	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	103712053	0	0
T1	228748	113203	0	0
T2	5729	2025	0	0
T3	559278	8051	0	0
T4	72131	66448	0	0
T11	1102	38	0	0
T12	3623	192	0	0
T16	2794	32	0	0
T17	3377	116	0	0
T18	216280	105518	0	0
T19	6238	492	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	103712053	0	0
T1	228748	113203	0	0
T2	5729	2025	0	0
T3	559278	8051	0	0
T4	72131	66448	0	0
T11	1102	38	0	0
T12	3623	192	0	0
T16	2794	32	0	0
T17	3377	116	0	0
T18	216280	105518	0	0
T19	6238	492	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	103712053	0	0
T1	228748	113203	0	0
T2	5729	2025	0	0
T3	559278	8051	0	0
T4	72131	66448	0	0
T11	1102	38	0	0
T12	3623	192	0	0
T16	2794	32	0	0
T17	3377	116	0	0
T18	216280	105518	0	0
T19	6238	492	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	45114126	0	0
T1	228748	128	0	0
T2	5729	575	0	0
T3	559278	285328	0	0
T4	72131	215	0	0
T11	1102	143	0	0
T12	3623	768	0	0
T16	2794	128	0	0
T17	3377	462	0	0
T18	216280	128	0	0
T19	6238	1296	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	109761608	0	0
T1	228748	113203	0	0
T2	5729	2025	0	0
T3	559278	129832	0	0
T4	72131	66448	0	0
T11	1102	38	0	0
T12	3623	192	0	0
T16	2794	32	0	0
T17	3377	116	0	0
T18	216280	105518	0	0
T19	6238	492	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	103712053	0	0
T1	228748	113203	0	0
T2	5729	2025	0	0
T3	559278	8051	0	0
T4	72131	66448	0	0
T11	1102	38	0	0
T12	3623	192	0	0
T16	2794	32	0	0
T17	3377	116	0	0
T18	216280	105518	0	0
T19	6238	492	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	103712053	0	0
T1	228748	113203	0	0
T2	5729	2025	0	0
T3	559278	8051	0	0
T4	72131	66448	0	0
T11	1102	38	0	0
T12	3623	192	0	0
T16	2794	32	0	0
T17	3377	116	0	0
T18	216280	105518	0	0
T19	6238	492	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	109761608	0	0
T1	228748	113203	0	0
T2	5729	2025	0	0
T3	559278	129832	0	0
T4	72131	66448	0	0
T11	1102	38	0	0
T12	3623	192	0	0
T16	2794	32	0	0
T17	3377	116	0	0
T18	216280	105518	0	0
T19	6238	492	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402544524	401677439	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	402544524	103711972	0	0
GntImpliesValid_A	402544524	103711972	0	0
GrantKnown_A	402544524	401677439	0	0
IdxKnown_A	402544524	401677439	0	0
IndexIsCorrect_A	402544524	103711972	0	0
NoReadyValidNoGrant_A	402544524	45114126	0	0
Priority_A	402544524	109761527	0	0
ReadyAndValidImplyGrant_A	402544524	103711972	0	0
ReqAndReadyImplyGrant_A	402544524	103711972	0	0
ReqImpliesValid_A	402544524	109761527	0	0
ValidKnown_A	402544524	401677439	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	103711972	0	0
T1	228748	113203	0	0
T2	5729	2025	0	0
T3	559278	8051	0	0
T4	72131	66448	0	0
T11	1102	38	0	0
T12	3623	192	0	0
T16	2794	32	0	0
T17	3377	116	0	0
T18	216280	105518	0	0
T19	6238	492	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	103711972	0	0
T1	228748	113203	0	0
T2	5729	2025	0	0
T3	559278	8051	0	0
T4	72131	66448	0	0
T11	1102	38	0	0
T12	3623	192	0	0
T16	2794	32	0	0
T17	3377	116	0	0
T18	216280	105518	0	0
T19	6238	492	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	103711972	0	0
T1	228748	113203	0	0
T2	5729	2025	0	0
T3	559278	8051	0	0
T4	72131	66448	0	0
T11	1102	38	0	0
T12	3623	192	0	0
T16	2794	32	0	0
T17	3377	116	0	0
T18	216280	105518	0	0
T19	6238	492	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	45114126	0	0
T1	228748	128	0	0
T2	5729	575	0	0
T3	559278	285328	0	0
T4	72131	215	0	0
T11	1102	143	0	0
T12	3623	768	0	0
T16	2794	128	0	0
T17	3377	462	0	0
T18	216280	128	0	0
T19	6238	1296	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	109761527	0	0
T1	228748	113203	0	0
T2	5729	2025	0	0
T3	559278	129832	0	0
T4	72131	66448	0	0
T11	1102	38	0	0
T12	3623	192	0	0
T16	2794	32	0	0
T17	3377	116	0	0
T18	216280	105518	0	0
T19	6238	492	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	103711972	0	0
T1	228748	113203	0	0
T2	5729	2025	0	0
T3	559278	8051	0	0
T4	72131	66448	0	0
T11	1102	38	0	0
T12	3623	192	0	0
T16	2794	32	0	0
T17	3377	116	0	0
T18	216280	105518	0	0
T19	6238	492	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	103711972	0	0
T1	228748	113203	0	0
T2	5729	2025	0	0
T3	559278	8051	0	0
T4	72131	66448	0	0
T11	1102	38	0	0
T12	3623	192	0	0
T16	2794	32	0	0
T17	3377	116	0	0
T18	216280	105518	0	0
T19	6238	492	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	109761527	0	0
T1	228748	113203	0	0
T2	5729	2025	0	0
T3	559278	129832	0	0
T4	72131	66448	0	0
T11	1102	38	0	0
T12	3623	192	0	0
T16	2794	32	0	0
T17	3377	116	0	0
T18	216280	105518	0	0
T19	6238	492	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T18
1	0	Covered	T2,T3,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T19
1	0	Covered	T1,T2,T18
1	1	Covered	T2,T3,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T18

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402544524	401677439	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	402544524	101251812	0	0
GntImpliesValid_A	402544524	101251812	0	0
GrantKnown_A	402544524	401677439	0	0
IdxKnown_A	402544524	401677439	0	0
IndexIsCorrect_A	402544524	101251812	0	0
NoReadyValidNoGrant_A	402544524	43093161	0	0
Priority_A	402544524	107324714	0	0
ReadyAndValidImplyGrant_A	402544524	101251812	0	0
ReqAndReadyImplyGrant_A	402544524	101251812	0	0
ReqImpliesValid_A	402544524	107324714	0	0
ValidKnown_A	402544524	401677439	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	101251812	0	0
T1	228748	89777	0	0
T2	5729	1074	0	0
T3	559278	7918	0	0
T4	72131	1401	0	0
T6	0	10210	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	87624	0	0
T19	6238	200	0	0
T20	0	65	0	0
T38	0	6135	0	0
T42	0	76	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	101251812	0	0
T1	228748	89777	0	0
T2	5729	1074	0	0
T3	559278	7918	0	0
T4	72131	1401	0	0
T6	0	10210	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	87624	0	0
T19	6238	200	0	0
T20	0	65	0	0
T38	0	6135	0	0
T42	0	76	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	101251812	0	0
T1	228748	89777	0	0
T2	5729	1074	0	0
T3	559278	7918	0	0
T4	72131	1401	0	0
T6	0	10210	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	87624	0	0
T19	6238	200	0	0
T20	0	65	0	0
T38	0	6135	0	0
T42	0	76	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	43093161	0	0
T2	5729	76	0	0
T3	559278	282781	0	0
T4	72131	39	0	0
T5	247739	0	0	0
T6	0	29884	0	0
T7	0	264938	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	0	0	0
T19	6238	356	0	0
T20	0	8	0	0
T26	0	625082	0	0
T38	0	606	0	0
T42	0	26	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	107324714	0	0
T1	228748	89777	0	0
T2	5729	1074	0	0
T3	559278	125476	0	0
T4	72131	1401	0	0
T6	0	11025	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	87624	0	0
T19	6238	200	0	0
T20	0	65	0	0
T38	0	6135	0	0
T42	0	76	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	101251812	0	0
T1	228748	89777	0	0
T2	5729	1074	0	0
T3	559278	7918	0	0
T4	72131	1401	0	0
T6	0	10210	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	87624	0	0
T19	6238	200	0	0
T20	0	65	0	0
T38	0	6135	0	0
T42	0	76	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	101251812	0	0
T1	228748	89777	0	0
T2	5729	1074	0	0
T3	559278	7918	0	0
T4	72131	1401	0	0
T6	0	10210	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	87624	0	0
T19	6238	200	0	0
T20	0	65	0	0
T38	0	6135	0	0
T42	0	76	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	107324714	0	0
T1	228748	89777	0	0
T2	5729	1074	0	0
T3	559278	125476	0	0
T4	72131	1401	0	0
T6	0	11025	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	87624	0	0
T19	6238	200	0	0
T20	0	65	0	0
T38	0	6135	0	0
T42	0	76	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T18
1	0	Covered	T2,T3,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T19
1	0	Covered	T1,T2,T18
1	1	Covered	T2,T3,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T18

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402544524	401677439	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	402544524	101251897	0	0
GntImpliesValid_A	402544524	101251897	0	0
GrantKnown_A	402544524	401677439	0	0
IdxKnown_A	402544524	401677439	0	0
IndexIsCorrect_A	402544524	101251897	0	0
NoReadyValidNoGrant_A	402544524	43093094	0	0
Priority_A	402544524	107324866	0	0
ReadyAndValidImplyGrant_A	402544524	101251897	0	0
ReqAndReadyImplyGrant_A	402544524	101251897	0	0
ReqImpliesValid_A	402544524	107324866	0	0
ValidKnown_A	402544524	401677439	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	101251897	0	0
T1	228748	89777	0	0
T2	5729	1074	0	0
T3	559278	7918	0	0
T4	72131	1401	0	0
T6	0	10210	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	87624	0	0
T19	6238	200	0	0
T20	0	65	0	0
T38	0	6135	0	0
T42	0	76	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	101251897	0	0
T1	228748	89777	0	0
T2	5729	1074	0	0
T3	559278	7918	0	0
T4	72131	1401	0	0
T6	0	10210	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	87624	0	0
T19	6238	200	0	0
T20	0	65	0	0
T38	0	6135	0	0
T42	0	76	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	101251897	0	0
T1	228748	89777	0	0
T2	5729	1074	0	0
T3	559278	7918	0	0
T4	72131	1401	0	0
T6	0	10210	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	87624	0	0
T19	6238	200	0	0
T20	0	65	0	0
T38	0	6135	0	0
T42	0	76	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	43093094	0	0
T2	5729	76	0	0
T3	559278	282781	0	0
T4	72131	39	0	0
T5	247739	0	0	0
T6	0	29884	0	0
T7	0	264938	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	0	0	0
T19	6238	356	0	0
T20	0	8	0	0
T26	0	625082	0	0
T38	0	606	0	0
T42	0	26	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	107324866	0	0
T1	228748	89777	0	0
T2	5729	1074	0	0
T3	559278	125476	0	0
T4	72131	1401	0	0
T6	0	11025	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	87624	0	0
T19	6238	200	0	0
T20	0	65	0	0
T38	0	6135	0	0
T42	0	76	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	101251897	0	0
T1	228748	89777	0	0
T2	5729	1074	0	0
T3	559278	7918	0	0
T4	72131	1401	0	0
T6	0	10210	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	87624	0	0
T19	6238	200	0	0
T20	0	65	0	0
T38	0	6135	0	0
T42	0	76	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	101251897	0	0
T1	228748	89777	0	0
T2	5729	1074	0	0
T3	559278	7918	0	0
T4	72131	1401	0	0
T6	0	10210	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	87624	0	0
T19	6238	200	0	0
T20	0	65	0	0
T38	0	6135	0	0
T42	0	76	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	107324866	0	0
T1	228748	89777	0	0
T2	5729	1074	0	0
T3	559278	125476	0	0
T4	72131	1401	0	0
T6	0	11025	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	87624	0	0
T19	6238	200	0	0
T20	0	65	0	0
T38	0	6135	0	0
T42	0	76	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0