SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T18 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 8352 | 8352 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 2147483647 | 167740319 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 8352 | 8352 | 0 | 0 |
T1 | 8 | 8 | 0 | 0 |
T2 | 8 | 8 | 0 | 0 |
T3 | 8 | 8 | 0 | 0 |
T4 | 8 | 8 | 0 | 0 |
T11 | 8 | 8 | 0 | 0 |
T12 | 8 | 8 | 0 | 0 |
T16 | 8 | 8 | 0 | 0 |
T17 | 8 | 8 | 0 | 0 |
T18 | 8 | 8 | 0 | 0 |
T19 | 8 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 167740319 | 0 | 0 |
T1 | 228748 | 11550 | 0 | 0 |
T2 | 5729 | 256 | 0 | 0 |
T3 | 559278 | 0 | 0 | 0 |
T4 | 72131 | 150 | 0 | 0 |
T5 | 0 | 12800 | 0 | 0 |
T11 | 1102 | 0 | 0 | 0 |
T12 | 3623 | 0 | 0 | 0 |
T16 | 2794 | 0 | 0 | 0 |
T17 | 3377 | 0 | 0 | 0 |
T18 | 216280 | 10000 | 0 | 0 |
T19 | 6238 | 0 | 0 | 0 |
T20 | 0 | 50 | 0 | 0 |
T27 | 0 | 50 | 0 | 0 |
T31 | 0 | 12800 | 0 | 0 |
T32 | 0 | 256 | 0 | 0 |
T38 | 31670 | 8250 | 0 | 0 |
T71 | 0 | 12 | 0 | 0 |
T72 | 229799 | 0 | 0 | 0 |
T81 | 160522 | 0 | 0 | 0 |
T97 | 764 | 0 | 0 | 0 |
T128 | 489139 | 38400 | 0 | 0 |
T129 | 0 | 1572864 | 0 | 0 |
T130 | 0 | 458752 | 0 | 0 |
T131 | 0 | 720896 | 0 | 0 |
T132 | 0 | 655360 | 0 | 0 |
T133 | 0 | 262144 | 0 | 0 |
T134 | 0 | 458752 | 0 | 0 |
T135 | 0 | 655360 | 0 | 0 |
T136 | 0 | 720896 | 0 | 0 |
T137 | 0 | 589824 | 0 | 0 |
T138 | 67349 | 0 | 0 | 0 |
T139 | 2912 | 0 | 0 | 0 |
T140 | 1183 | 0 | 0 | 0 |
T141 | 1518 | 0 | 0 | 0 |
T142 | 3862 | 0 | 0 | 0 |
T143 | 979 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T18 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 402544524 | 57613819 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 402544524 | 57613819 | 0 | 0 |
T1 | 228748 | 87800 | 0 | 0 |
T2 | 5729 | 1536 | 0 | 0 |
T3 | 559278 | 0 | 0 | 0 |
T4 | 72131 | 66186 | 0 | 0 |
T11 | 1102 | 0 | 0 | 0 |
T12 | 3623 | 0 | 0 | 0 |
T16 | 2794 | 0 | 0 | 0 |
T17 | 3377 | 0 | 0 | 0 |
T18 | 216280 | 80150 | 0 | 0 |
T19 | 6238 | 0 | 0 | 0 |
T24 | 0 | 300 | 0 | 0 |
T25 | 0 | 200 | 0 | 0 |
T38 | 0 | 4450 | 0 | 0 |
T42 | 0 | 650 | 0 | 0 |
T61 | 0 | 10700 | 0 | 0 |
T109 | 0 | 200 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T18 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 402544524 | 15467691 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 402544524 | 15467691 | 0 | 0 |
T1 | 228748 | 11550 | 0 | 0 |
T2 | 5729 | 256 | 0 | 0 |
T3 | 559278 | 0 | 0 | 0 |
T4 | 72131 | 150 | 0 | 0 |
T5 | 0 | 12800 | 0 | 0 |
T11 | 1102 | 0 | 0 | 0 |
T12 | 3623 | 0 | 0 | 0 |
T16 | 2794 | 0 | 0 | 0 |
T17 | 3377 | 0 | 0 | 0 |
T18 | 216280 | 10000 | 0 | 0 |
T19 | 6238 | 0 | 0 | 0 |
T20 | 0 | 50 | 0 | 0 |
T31 | 0 | 12800 | 0 | 0 |
T32 | 0 | 256 | 0 | 0 |
T38 | 0 | 7800 | 0 | 0 |
T71 | 0 | 12 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T8,T128,T129 |
1 | 0 | Covered | T4,T44,T56 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 402544524 | 5321216 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 402544524 | 5321216 | 0 | 0 |
T72 | 229799 | 0 | 0 | 0 |
T81 | 160522 | 0 | 0 | 0 |
T97 | 764 | 0 | 0 | 0 |
T128 | 489139 | 12800 | 0 | 0 |
T129 | 0 | 786432 | 0 | 0 |
T130 | 0 | 458752 | 0 | 0 |
T131 | 0 | 720896 | 0 | 0 |
T132 | 0 | 655360 | 0 | 0 |
T133 | 0 | 262144 | 0 | 0 |
T134 | 0 | 458752 | 0 | 0 |
T135 | 0 | 655360 | 0 | 0 |
T136 | 0 | 720896 | 0 | 0 |
T137 | 0 | 589824 | 0 | 0 |
T138 | 67349 | 0 | 0 | 0 |
T139 | 2912 | 0 | 0 | 0 |
T140 | 1183 | 0 | 0 | 0 |
T141 | 1518 | 0 | 0 | 0 |
T142 | 3862 | 0 | 0 | 0 |
T143 | 979 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T38,T27,T127 |
1 | 0 | Covered | T2,T4,T20 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 402544524 | 5436800 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 402544524 | 5436800 | 0 | 0 |
T6 | 55853 | 0 | 0 | 0 |
T7 | 562531 | 0 | 0 | 0 |
T23 | 1400 | 0 | 0 | 0 |
T26 | 120315 | 0 | 0 | 0 |
T27 | 0 | 50 | 0 | 0 |
T28 | 0 | 250 | 0 | 0 |
T29 | 0 | 1000 | 0 | 0 |
T38 | 31670 | 450 | 0 | 0 |
T57 | 1463 | 0 | 0 | 0 |
T61 | 39053 | 0 | 0 | 0 |
T80 | 0 | 1100 | 0 | 0 |
T93 | 4620 | 0 | 0 | 0 |
T101 | 1110 | 0 | 0 | 0 |
T113 | 1259 | 0 | 0 | 0 |
T127 | 0 | 100 | 0 | 0 |
T128 | 0 | 25600 | 0 | 0 |
T129 | 0 | 786432 | 0 | 0 |
T144 | 0 | 256 | 0 | 0 |
T145 | 0 | 400 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T18 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 402544524 | 66664065 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 402544524 | 66664065 | 0 | 0 |
T1 | 228748 | 79600 | 0 | 0 |
T2 | 5729 | 1024 | 0 | 0 |
T3 | 559278 | 0 | 0 | 0 |
T4 | 72131 | 400 | 0 | 0 |
T11 | 1102 | 0 | 0 | 0 |
T12 | 3623 | 0 | 0 | 0 |
T16 | 2794 | 0 | 0 | 0 |
T17 | 3377 | 0 | 0 | 0 |
T18 | 216280 | 73900 | 0 | 0 |
T19 | 6238 | 0 | 0 | 0 |
T20 | 0 | 50 | 0 | 0 |
T24 | 0 | 65792 | 0 | 0 |
T38 | 0 | 5050 | 0 | 0 |
T42 | 0 | 50 | 0 | 0 |
T61 | 0 | 12900 | 0 | 0 |
T109 | 0 | 450 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T4,T109,T40 |
1 | 0 | Covered | T2,T4,T109 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 402544524 | 6589976 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 402544524 | 6589976 | 0 | 0 |
T4 | 72131 | 306 | 0 | 0 |
T5 | 247739 | 0 | 0 | 0 |
T6 | 55853 | 0 | 0 | 0 |
T11 | 1102 | 0 | 0 | 0 |
T12 | 3623 | 0 | 0 | 0 |
T13 | 962 | 0 | 0 | 0 |
T19 | 6238 | 0 | 0 | 0 |
T20 | 3167 | 0 | 0 | 0 |
T38 | 31670 | 0 | 0 | 0 |
T40 | 0 | 50 | 0 | 0 |
T41 | 0 | 50 | 0 | 0 |
T42 | 2363 | 0 | 0 | 0 |
T77 | 0 | 1062 | 0 | 0 |
T109 | 0 | 600 | 0 | 0 |
T146 | 0 | 400 | 0 | 0 |
T147 | 0 | 50 | 0 | 0 |
T148 | 0 | 400 | 0 | 0 |
T149 | 0 | 50 | 0 | 0 |
T150 | 0 | 25600 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T8,T129,T130 |
1 | 0 | Covered | T4,T109,T8 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 402544524 | 5294080 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 402544524 | 5294080 | 0 | 0 |
T129 | 178348 | 851968 | 0 | 0 |
T130 | 0 | 655360 | 0 | 0 |
T132 | 0 | 655360 | 0 | 0 |
T151 | 0 | 12800 | 0 | 0 |
T152 | 0 | 12800 | 0 | 0 |
T153 | 0 | 720896 | 0 | 0 |
T154 | 0 | 851968 | 0 | 0 |
T155 | 0 | 458752 | 0 | 0 |
T156 | 0 | 589824 | 0 | 0 |
T157 | 0 | 458752 | 0 | 0 |
T158 | 41619 | 0 | 0 | 0 |
T159 | 209799 | 0 | 0 | 0 |
T160 | 3871 | 0 | 0 | 0 |
T161 | 289582 | 0 | 0 | 0 |
T162 | 1379 | 0 | 0 | 0 |
T163 | 1049 | 0 | 0 | 0 |
T164 | 1932 | 0 | 0 | 0 |
T165 | 554614 | 0 | 0 | 0 |
T166 | 3318 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T4,T8,T129 |
1 | 0 | Covered | T4,T8,T167 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 402544524 | 5352672 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 402544524 | 5352672 | 0 | 0 |
T4 | 72131 | 650 | 0 | 0 |
T5 | 247739 | 0 | 0 | 0 |
T6 | 55853 | 0 | 0 | 0 |
T11 | 1102 | 0 | 0 | 0 |
T12 | 3623 | 0 | 0 | 0 |
T13 | 962 | 0 | 0 | 0 |
T19 | 6238 | 0 | 0 | 0 |
T20 | 3167 | 0 | 0 | 0 |
T38 | 31670 | 0 | 0 | 0 |
T42 | 2363 | 0 | 0 | 0 |
T129 | 0 | 851968 | 0 | 0 |
T130 | 0 | 655360 | 0 | 0 |
T132 | 0 | 655360 | 0 | 0 |
T151 | 0 | 25600 | 0 | 0 |
T152 | 0 | 25600 | 0 | 0 |
T153 | 0 | 720896 | 0 | 0 |
T167 | 0 | 100 | 0 | 0 |
T168 | 0 | 50 | 0 | 0 |
T169 | 0 | 1162 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |