SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_seed_hw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_flash_hw_if.u_sync_rma_req | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prog_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_escalation_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.u_lc_nvm_debug_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.69 | 97.12 | 93.60 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.75 | 100.00 | 92.71 | 92.11 | 98.94 | 100.00 | u_flash_hw_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.37 | 100.00 | 88.89 | 57.14 | 95.83 | 50.00 | u_prog_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.69 | 97.12 | 93.60 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
80.60 | 100.00 | 100.00 | 57.14 | 95.83 | 50.00 | u_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.22 | 97.67 | 88.00 | 100.00 | u_eflash |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 10440 | 10440 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 21666 |
gen_no_flops.OutputDelay_A | 790736834 | 789002664 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10440 | 10440 | 0 | 0 |
T1 | 10 | 10 | 0 | 0 |
T2 | 10 | 10 | 0 | 0 |
T3 | 10 | 10 | 0 | 0 |
T4 | 10 | 10 | 0 | 0 |
T11 | 10 | 10 | 0 | 0 |
T12 | 10 | 10 | 0 | 0 |
T16 | 10 | 10 | 0 | 0 |
T17 | 10 | 10 | 0 | 0 |
T18 | 10 | 10 | 0 | 0 |
T19 | 10 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 2287480 | 2286540 | 0 | 0 |
T2 | 57290 | 55640 | 0 | 0 |
T3 | 5592780 | 5591250 | 0 | 0 |
T4 | 721310 | 720780 | 0 | 0 |
T11 | 10362 | 9782 | 0 | 0 |
T12 | 36230 | 29650 | 0 | 0 |
T16 | 27940 | 27240 | 0 | 0 |
T17 | 33770 | 26740 | 0 | 0 |
T18 | 2162800 | 2161960 | 0 | 0 |
T19 | 62380 | 57580 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 21666 |
T1 | 1829984 | 1829208 | 0 | 24 |
T2 | 45832 | 44464 | 0 | 24 |
T3 | 4474224 | 4472952 | 0 | 24 |
T4 | 577048 | 576600 | 0 | 24 |
T11 | 8158 | 7673 | 0 | 21 |
T12 | 28984 | 23504 | 0 | 24 |
T16 | 22352 | 21768 | 0 | 24 |
T17 | 27016 | 21176 | 0 | 24 |
T18 | 1730240 | 1729544 | 0 | 24 |
T19 | 49904 | 45896 | 0 | 24 |
T20 | 0 | 0 | 0 | 3 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 790736834 | 789002664 | 0 | 0 |
T1 | 457496 | 457308 | 0 | 0 |
T2 | 11458 | 11128 | 0 | 0 |
T3 | 1118556 | 1118250 | 0 | 0 |
T4 | 144262 | 144156 | 0 | 0 |
T11 | 2204 | 2088 | 0 | 0 |
T12 | 7246 | 5930 | 0 | 0 |
T16 | 5588 | 5448 | 0 | 0 |
T17 | 6754 | 5348 | 0 | 0 |
T18 | 432560 | 432392 | 0 | 0 |
T19 | 12476 | 11516 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 395368438 | 394501353 | 0 | 0 |
gen_flops.OutputDelay_A | 395368438 | 394467075 | 0 | 2727 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368438 | 394501353 | 0 | 0 |
T1 | 228748 | 228654 | 0 | 0 |
T2 | 5729 | 5564 | 0 | 0 |
T3 | 559278 | 559125 | 0 | 0 |
T4 | 72131 | 72078 | 0 | 0 |
T11 | 1102 | 1044 | 0 | 0 |
T12 | 3623 | 2965 | 0 | 0 |
T16 | 2794 | 2724 | 0 | 0 |
T17 | 3377 | 2674 | 0 | 0 |
T18 | 216280 | 216196 | 0 | 0 |
T19 | 6238 | 5758 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368438 | 394467075 | 0 | 2727 |
T1 | 228748 | 228651 | 0 | 3 |
T2 | 5729 | 5558 | 0 | 3 |
T3 | 559278 | 559119 | 0 | 3 |
T4 | 72131 | 72075 | 0 | 3 |
T11 | 1102 | 1041 | 0 | 3 |
T12 | 3623 | 2938 | 0 | 3 |
T16 | 2794 | 2721 | 0 | 3 |
T17 | 3377 | 2647 | 0 | 3 |
T18 | 216280 | 216193 | 0 | 3 |
T19 | 6238 | 5737 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 395368438 | 394501353 | 0 | 0 |
gen_flops.OutputDelay_A | 395368438 | 394467075 | 0 | 2727 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368438 | 394501353 | 0 | 0 |
T1 | 228748 | 228654 | 0 | 0 |
T2 | 5729 | 5564 | 0 | 0 |
T3 | 559278 | 559125 | 0 | 0 |
T4 | 72131 | 72078 | 0 | 0 |
T11 | 1102 | 1044 | 0 | 0 |
T12 | 3623 | 2965 | 0 | 0 |
T16 | 2794 | 2724 | 0 | 0 |
T17 | 3377 | 2674 | 0 | 0 |
T18 | 216280 | 216196 | 0 | 0 |
T19 | 6238 | 5758 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368438 | 394467075 | 0 | 2727 |
T1 | 228748 | 228651 | 0 | 3 |
T2 | 5729 | 5558 | 0 | 3 |
T3 | 559278 | 559119 | 0 | 3 |
T4 | 72131 | 72075 | 0 | 3 |
T11 | 1102 | 1041 | 0 | 3 |
T12 | 3623 | 2938 | 0 | 3 |
T16 | 2794 | 2721 | 0 | 3 |
T17 | 3377 | 2647 | 0 | 3 |
T18 | 216280 | 216193 | 0 | 3 |
T19 | 6238 | 5737 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 395368438 | 394501353 | 0 | 0 |
gen_flops.OutputDelay_A | 395368438 | 394467075 | 0 | 2727 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368438 | 394501353 | 0 | 0 |
T1 | 228748 | 228654 | 0 | 0 |
T2 | 5729 | 5564 | 0 | 0 |
T3 | 559278 | 559125 | 0 | 0 |
T4 | 72131 | 72078 | 0 | 0 |
T11 | 1102 | 1044 | 0 | 0 |
T12 | 3623 | 2965 | 0 | 0 |
T16 | 2794 | 2724 | 0 | 0 |
T17 | 3377 | 2674 | 0 | 0 |
T18 | 216280 | 216196 | 0 | 0 |
T19 | 6238 | 5758 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368438 | 394467075 | 0 | 2727 |
T1 | 228748 | 228651 | 0 | 3 |
T2 | 5729 | 5558 | 0 | 3 |
T3 | 559278 | 559119 | 0 | 3 |
T4 | 72131 | 72075 | 0 | 3 |
T11 | 1102 | 1041 | 0 | 3 |
T12 | 3623 | 2938 | 0 | 3 |
T16 | 2794 | 2721 | 0 | 3 |
T17 | 3377 | 2647 | 0 | 3 |
T18 | 216280 | 216193 | 0 | 3 |
T19 | 6238 | 5737 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 395368438 | 394501353 | 0 | 0 |
gen_flops.OutputDelay_A | 395368438 | 394467075 | 0 | 2727 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368438 | 394501353 | 0 | 0 |
T1 | 228748 | 228654 | 0 | 0 |
T2 | 5729 | 5564 | 0 | 0 |
T3 | 559278 | 559125 | 0 | 0 |
T4 | 72131 | 72078 | 0 | 0 |
T11 | 1102 | 1044 | 0 | 0 |
T12 | 3623 | 2965 | 0 | 0 |
T16 | 2794 | 2724 | 0 | 0 |
T17 | 3377 | 2674 | 0 | 0 |
T18 | 216280 | 216196 | 0 | 0 |
T19 | 6238 | 5758 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368438 | 394467075 | 0 | 2727 |
T1 | 228748 | 228651 | 0 | 3 |
T2 | 5729 | 5558 | 0 | 3 |
T3 | 559278 | 559119 | 0 | 3 |
T4 | 72131 | 72075 | 0 | 3 |
T11 | 1102 | 1041 | 0 | 3 |
T12 | 3623 | 2938 | 0 | 3 |
T16 | 2794 | 2721 | 0 | 3 |
T17 | 3377 | 2647 | 0 | 3 |
T18 | 216280 | 216193 | 0 | 3 |
T19 | 6238 | 5737 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 395368438 | 394501353 | 0 | 0 |
gen_flops.OutputDelay_A | 395368438 | 394467075 | 0 | 2727 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368438 | 394501353 | 0 | 0 |
T1 | 228748 | 228654 | 0 | 0 |
T2 | 5729 | 5564 | 0 | 0 |
T3 | 559278 | 559125 | 0 | 0 |
T4 | 72131 | 72078 | 0 | 0 |
T11 | 1102 | 1044 | 0 | 0 |
T12 | 3623 | 2965 | 0 | 0 |
T16 | 2794 | 2724 | 0 | 0 |
T17 | 3377 | 2674 | 0 | 0 |
T18 | 216280 | 216196 | 0 | 0 |
T19 | 6238 | 5758 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368438 | 394467075 | 0 | 2727 |
T1 | 228748 | 228651 | 0 | 3 |
T2 | 5729 | 5558 | 0 | 3 |
T3 | 559278 | 559119 | 0 | 3 |
T4 | 72131 | 72075 | 0 | 3 |
T11 | 1102 | 1041 | 0 | 3 |
T12 | 3623 | 2938 | 0 | 3 |
T16 | 2794 | 2721 | 0 | 3 |
T17 | 3377 | 2647 | 0 | 3 |
T18 | 216280 | 216193 | 0 | 3 |
T19 | 6238 | 5737 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 395368438 | 394501353 | 0 | 0 |
gen_flops.OutputDelay_A | 395368438 | 394467075 | 0 | 2727 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368438 | 394501353 | 0 | 0 |
T1 | 228748 | 228654 | 0 | 0 |
T2 | 5729 | 5564 | 0 | 0 |
T3 | 559278 | 559125 | 0 | 0 |
T4 | 72131 | 72078 | 0 | 0 |
T11 | 1102 | 1044 | 0 | 0 |
T12 | 3623 | 2965 | 0 | 0 |
T16 | 2794 | 2724 | 0 | 0 |
T17 | 3377 | 2674 | 0 | 0 |
T18 | 216280 | 216196 | 0 | 0 |
T19 | 6238 | 5758 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368438 | 394467075 | 0 | 2727 |
T1 | 228748 | 228651 | 0 | 3 |
T2 | 5729 | 5558 | 0 | 3 |
T3 | 559278 | 559119 | 0 | 3 |
T4 | 72131 | 72075 | 0 | 3 |
T11 | 1102 | 1041 | 0 | 3 |
T12 | 3623 | 2938 | 0 | 3 |
T16 | 2794 | 2721 | 0 | 3 |
T17 | 3377 | 2647 | 0 | 3 |
T18 | 216280 | 216193 | 0 | 3 |
T19 | 6238 | 5737 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 395368417 | 394501332 | 0 | 0 |
gen_no_flops.OutputDelay_A | 395368417 | 394501332 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368417 | 394501332 | 0 | 0 |
T1 | 228748 | 228654 | 0 | 0 |
T2 | 5729 | 5564 | 0 | 0 |
T3 | 559278 | 559125 | 0 | 0 |
T4 | 72131 | 72078 | 0 | 0 |
T11 | 1102 | 1044 | 0 | 0 |
T12 | 3623 | 2965 | 0 | 0 |
T16 | 2794 | 2724 | 0 | 0 |
T17 | 3377 | 2674 | 0 | 0 |
T18 | 216280 | 216196 | 0 | 0 |
T19 | 6238 | 5758 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368417 | 394501332 | 0 | 0 |
T1 | 228748 | 228654 | 0 | 0 |
T2 | 5729 | 5564 | 0 | 0 |
T3 | 559278 | 559125 | 0 | 0 |
T4 | 72131 | 72078 | 0 | 0 |
T11 | 1102 | 1044 | 0 | 0 |
T12 | 3623 | 2965 | 0 | 0 |
T16 | 2794 | 2724 | 0 | 0 |
T17 | 3377 | 2674 | 0 | 0 |
T18 | 216280 | 216196 | 0 | 0 |
T19 | 6238 | 5758 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 395347140 | 394480055 | 0 | 0 |
gen_flops.OutputDelay_A | 395347140 | 394445927 | 0 | 2577 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395347140 | 394480055 | 0 | 0 |
T1 | 228748 | 228654 | 0 | 0 |
T2 | 5729 | 5564 | 0 | 0 |
T3 | 559278 | 559125 | 0 | 0 |
T4 | 72131 | 72078 | 0 | 0 |
T11 | 444 | 386 | 0 | 0 |
T12 | 3623 | 2965 | 0 | 0 |
T16 | 2794 | 2724 | 0 | 0 |
T17 | 3377 | 2674 | 0 | 0 |
T18 | 216280 | 216196 | 0 | 0 |
T19 | 6238 | 5758 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395347140 | 394445927 | 0 | 2577 |
T1 | 228748 | 228651 | 0 | 3 |
T2 | 5729 | 5558 | 0 | 3 |
T3 | 559278 | 559119 | 0 | 3 |
T4 | 72131 | 72075 | 0 | 3 |
T11 | 444 | 386 | 0 | 0 |
T12 | 3623 | 2938 | 0 | 3 |
T16 | 2794 | 2721 | 0 | 3 |
T17 | 3377 | 2647 | 0 | 3 |
T18 | 216280 | 216193 | 0 | 3 |
T19 | 6238 | 5737 | 0 | 3 |
T20 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 395368417 | 394501332 | 0 | 0 |
gen_no_flops.OutputDelay_A | 395368417 | 394501332 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368417 | 394501332 | 0 | 0 |
T1 | 228748 | 228654 | 0 | 0 |
T2 | 5729 | 5564 | 0 | 0 |
T3 | 559278 | 559125 | 0 | 0 |
T4 | 72131 | 72078 | 0 | 0 |
T11 | 1102 | 1044 | 0 | 0 |
T12 | 3623 | 2965 | 0 | 0 |
T16 | 2794 | 2724 | 0 | 0 |
T17 | 3377 | 2674 | 0 | 0 |
T18 | 216280 | 216196 | 0 | 0 |
T19 | 6238 | 5758 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368417 | 394501332 | 0 | 0 |
T1 | 228748 | 228654 | 0 | 0 |
T2 | 5729 | 5564 | 0 | 0 |
T3 | 559278 | 559125 | 0 | 0 |
T4 | 72131 | 72078 | 0 | 0 |
T11 | 1102 | 1044 | 0 | 0 |
T12 | 3623 | 2965 | 0 | 0 |
T16 | 2794 | 2724 | 0 | 0 |
T17 | 3377 | 2674 | 0 | 0 |
T18 | 216280 | 216196 | 0 | 0 |
T19 | 6238 | 5758 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 395368417 | 394501332 | 0 | 0 |
gen_flops.OutputDelay_A | 395368417 | 394467069 | 0 | 2727 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368417 | 394501332 | 0 | 0 |
T1 | 228748 | 228654 | 0 | 0 |
T2 | 5729 | 5564 | 0 | 0 |
T3 | 559278 | 559125 | 0 | 0 |
T4 | 72131 | 72078 | 0 | 0 |
T11 | 1102 | 1044 | 0 | 0 |
T12 | 3623 | 2965 | 0 | 0 |
T16 | 2794 | 2724 | 0 | 0 |
T17 | 3377 | 2674 | 0 | 0 |
T18 | 216280 | 216196 | 0 | 0 |
T19 | 6238 | 5758 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 395368417 | 394467069 | 0 | 2727 |
T1 | 228748 | 228651 | 0 | 3 |
T2 | 5729 | 5558 | 0 | 3 |
T3 | 559278 | 559119 | 0 | 3 |
T4 | 72131 | 72075 | 0 | 3 |
T11 | 1102 | 1041 | 0 | 3 |
T12 | 3623 | 2938 | 0 | 3 |
T16 | 2794 | 2721 | 0 | 3 |
T17 | 3377 | 2647 | 0 | 3 |
T18 | 216280 | 216193 | 0 | 3 |
T19 | 6238 | 5737 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |