Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.24 95.70 93.99 98.31 92.52 98.21 96.89 98.09


Total test records in report: 1259
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T1251 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.188321281 Jul 22 06:19:09 PM PDT 24 Jul 22 06:19:26 PM PDT 24 83991700 ps
T1252 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2184286714 Jul 22 06:20:05 PM PDT 24 Jul 22 06:20:24 PM PDT 24 253576700 ps
T1253 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1757302516 Jul 22 06:19:05 PM PDT 24 Jul 22 06:19:22 PM PDT 24 13507400 ps
T1254 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1754978345 Jul 22 06:18:38 PM PDT 24 Jul 22 06:18:52 PM PDT 24 195963200 ps
T1255 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.11213530 Jul 22 06:19:06 PM PDT 24 Jul 22 06:19:24 PM PDT 24 37407600 ps
T1256 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.226841236 Jul 22 06:19:06 PM PDT 24 Jul 22 06:19:22 PM PDT 24 107172000 ps
T1257 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1478324749 Jul 22 06:18:50 PM PDT 24 Jul 22 06:19:05 PM PDT 24 12514200 ps
T1258 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.4286660868 Jul 22 06:19:13 PM PDT 24 Jul 22 06:19:29 PM PDT 24 23527500 ps
T1259 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.631506530 Jul 22 06:19:07 PM PDT 24 Jul 22 06:19:26 PM PDT 24 51927200 ps

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.2181268130
Short name T4
Test name
Test status
Simulation time 966576400 ps
CPU time 298.76 seconds
Started Jul 22 05:26:29 PM PDT 24
Finished Jul 22 05:31:28 PM PDT 24
Peak memory 281496 kb
Host smart-106084fe-5bfd-425d-a472-6fe82fe905b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181268130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.2181268130
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1717776871
Short name T225
Test name
Test status
Simulation time 1790866100 ps
CPU time 911.94 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:34:02 PM PDT 24
Peak memory 264076 kb
Host smart-b33814c9-384e-4590-b012-f39b8ced7ca8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717776871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.1717776871
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.2880835194
Short name T19
Test name
Test status
Simulation time 64905600 ps
CPU time 32.01 seconds
Started Jul 22 05:26:30 PM PDT 24
Finished Jul 22 05:27:02 PM PDT 24
Peak memory 275628 kb
Host smart-c64581b3-2251-4f58-b567-b751f34c1f62
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880835194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.2880835194
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.239506339
Short name T69
Test name
Test status
Simulation time 157490588000 ps
CPU time 1072.13 seconds
Started Jul 22 05:26:33 PM PDT 24
Finished Jul 22 05:44:26 PM PDT 24
Peak memory 261420 kb
Host smart-4f541a26-d4f3-4d87-a218-4309063c3bc0
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239506339 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.239506339
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_derr.3107639737
Short name T48
Test name
Test status
Simulation time 14228400300 ps
CPU time 680.76 seconds
Started Jul 22 05:27:46 PM PDT 24
Finished Jul 22 05:39:07 PM PDT 24
Peak memory 333684 kb
Host smart-5968e378-eeac-4d76-98a7-2fb34f4875d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107639737 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_rw_derr.3107639737
Directory /workspace/4.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.900337629
Short name T150
Test name
Test status
Simulation time 3696891400 ps
CPU time 115.98 seconds
Started Jul 22 05:29:00 PM PDT 24
Finished Jul 22 05:30:56 PM PDT 24
Peak memory 263812 kb
Host smart-ac69cf8e-8ba6-4c3f-b045-29815e4305cd
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900337629 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.900337629
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3806939016
Short name T26
Test name
Test status
Simulation time 12512803400 ps
CPU time 284.9 seconds
Started Jul 22 05:30:12 PM PDT 24
Finished Jul 22 05:34:58 PM PDT 24
Peak memory 284868 kb
Host smart-f81fdccd-3130-4cd8-a7ed-ef97b2c61df3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806939016 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.3806939016
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.2694192886
Short name T14
Test name
Test status
Simulation time 5093190300 ps
CPU time 4748.26 seconds
Started Jul 22 05:26:07 PM PDT 24
Finished Jul 22 06:45:16 PM PDT 24
Peak memory 294948 kb
Host smart-6e8d93d3-21d0-4bf7-ad01-8f013edcfa22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694192886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.2694192886
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.276761838
Short name T173
Test name
Test status
Simulation time 1958920200 ps
CPU time 300.13 seconds
Started Jul 22 05:26:45 PM PDT 24
Finished Jul 22 05:31:45 PM PDT 24
Peak memory 263448 kb
Host smart-72712c75-20aa-4010-b0d3-7d7da1a42210
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=276761838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.276761838
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.728488360
Short name T71
Test name
Test status
Simulation time 140292100 ps
CPU time 110.91 seconds
Started Jul 22 05:30:08 PM PDT 24
Finished Jul 22 05:31:59 PM PDT 24
Peak memory 260012 kb
Host smart-0cbd5e29-5090-41f1-9fe0-729b80c2e8f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728488360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ot
p_reset.728488360
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2901375833
Short name T242
Test name
Test status
Simulation time 65636300 ps
CPU time 20.33 seconds
Started Jul 22 06:18:51 PM PDT 24
Finished Jul 22 06:19:12 PM PDT 24
Peak memory 263056 kb
Host smart-58fe1823-9487-476d-a425-3bbd4fd7b4c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901375833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.2
901375833
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.1545171343
Short name T24
Test name
Test status
Simulation time 688067200 ps
CPU time 213.49 seconds
Started Jul 22 05:28:53 PM PDT 24
Finished Jul 22 05:32:27 PM PDT 24
Peak memory 263300 kb
Host smart-df3bd7d6-8635-4aea-9f17-cb2e8fe67e34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1545171343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.1545171343
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.4101002314
Short name T20
Test name
Test status
Simulation time 32959800 ps
CPU time 29.49 seconds
Started Jul 22 05:31:28 PM PDT 24
Finished Jul 22 05:31:58 PM PDT 24
Peak memory 275580 kb
Host smart-a6b2f22d-4052-455a-b5b0-97761af9a457
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101002314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_rw_evict.4101002314
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.2277586583
Short name T171
Test name
Test status
Simulation time 1405145500 ps
CPU time 72.81 seconds
Started Jul 22 05:27:38 PM PDT 24
Finished Jul 22 05:28:51 PM PDT 24
Peak memory 260592 kb
Host smart-fa64bd70-4b29-44a8-92a3-6c2d8ef61852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277586583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.2277586583
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.1734025724
Short name T201
Test name
Test status
Simulation time 68389700 ps
CPU time 129.71 seconds
Started Jul 22 05:29:00 PM PDT 24
Finished Jul 22 05:31:10 PM PDT 24
Peak memory 265208 kb
Host smart-a6c44032-c8e3-4162-bf9d-2647510fb171
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734025724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot
p_reset.1734025724
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.28122024
Short name T75
Test name
Test status
Simulation time 66066900 ps
CPU time 130.63 seconds
Started Jul 22 05:34:02 PM PDT 24
Finished Jul 22 05:36:14 PM PDT 24
Peak memory 264420 kb
Host smart-1398e486-c346-4887-b990-29b2be936d04
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28122024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_otp
_reset.28122024
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.1699011615
Short name T8
Test name
Test status
Simulation time 21581500 ps
CPU time 13.76 seconds
Started Jul 22 05:27:56 PM PDT 24
Finished Jul 22 05:28:10 PM PDT 24
Peak memory 262772 kb
Host smart-f63b87eb-9d41-4c9f-a7cf-2d0f30c24497
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699011615 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.1699011615
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.572706761
Short name T106
Test name
Test status
Simulation time 272684344200 ps
CPU time 2754.77 seconds
Started Jul 22 05:28:00 PM PDT 24
Finished Jul 22 06:13:55 PM PDT 24
Peak memory 265304 kb
Host smart-eec0f0cd-c889-4cb5-9f77-1c7e72609c92
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572706761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.flash_ctrl_host_ctrl_arb.572706761
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.999491813
Short name T262
Test name
Test status
Simulation time 17865600 ps
CPU time 13.29 seconds
Started Jul 22 06:20:04 PM PDT 24
Finished Jul 22 06:20:24 PM PDT 24
Peak memory 261424 kb
Host smart-c629f51a-a2ee-4a8c-a995-1d3bc8aa79a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999491813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.999491813
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.3006510276
Short name T159
Test name
Test status
Simulation time 2811325500 ps
CPU time 187.95 seconds
Started Jul 22 05:32:11 PM PDT 24
Finished Jul 22 05:35:20 PM PDT 24
Peak memory 261036 kb
Host smart-16787f06-423c-41d5-a770-393e895d9e07
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006510276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.3006510276
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.2149710078
Short name T2
Test name
Test status
Simulation time 114610600 ps
CPU time 34.48 seconds
Started Jul 22 05:32:05 PM PDT 24
Finished Jul 22 05:32:39 PM PDT 24
Peak memory 275620 kb
Host smart-0aed8224-e03b-4f0d-ae06-6add5d344d57
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149710078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.2149710078
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.4151396396
Short name T170
Test name
Test status
Simulation time 10037710000 ps
CPU time 58.13 seconds
Started Jul 22 05:30:51 PM PDT 24
Finished Jul 22 05:31:49 PM PDT 24
Peak memory 287904 kb
Host smart-79a5302e-94a3-4113-88fd-dc786f4de835
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151396396 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.4151396396
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.4096773290
Short name T11
Test name
Test status
Simulation time 11257900 ps
CPU time 20.43 seconds
Started Jul 22 05:28:58 PM PDT 24
Finished Jul 22 05:29:19 PM PDT 24
Peak memory 273548 kb
Host smart-cf6ef596-a54a-4f11-9054-329c1fdb7606
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096773290 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.4096773290
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1901760621
Short name T1003
Test name
Test status
Simulation time 10020358800 ps
CPU time 169.56 seconds
Started Jul 22 05:28:00 PM PDT 24
Finished Jul 22 05:30:50 PM PDT 24
Peak memory 288980 kb
Host smart-7469c62f-7e6a-42df-8443-1aebb2571e0f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901760621 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.1901760621
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.1791470009
Short name T93
Test name
Test status
Simulation time 135869700 ps
CPU time 13.74 seconds
Started Jul 22 05:33:43 PM PDT 24
Finished Jul 22 05:33:58 PM PDT 24
Peak memory 258232 kb
Host smart-86b155e4-9d15-4b94-8ebb-b9d5ec3a27a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791470009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
1791470009
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.489765206
Short name T269
Test name
Test status
Simulation time 3447716300 ps
CPU time 913.68 seconds
Started Jul 22 06:18:36 PM PDT 24
Finished Jul 22 06:33:51 PM PDT 24
Peak memory 264172 kb
Host smart-88fbdb1f-e342-4017-b18f-635d03abeebc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489765206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_
tl_intg_err.489765206
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.688140749
Short name T32
Test name
Test status
Simulation time 1346019100 ps
CPU time 57.17 seconds
Started Jul 22 05:32:37 PM PDT 24
Finished Jul 22 05:33:34 PM PDT 24
Peak memory 263324 kb
Host smart-a577d173-f13d-49f2-90c5-b41859ccb6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688140749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.688140749
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.1961300717
Short name T49
Test name
Test status
Simulation time 6513990700 ps
CPU time 35.14 seconds
Started Jul 22 05:25:51 PM PDT 24
Finished Jul 22 05:26:27 PM PDT 24
Peak memory 262536 kb
Host smart-89a0b766-5b50-4b19-9d81-5ef2f86d55d5
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961300717 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_fetch_code.1961300717
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.3096931613
Short name T90
Test name
Test status
Simulation time 1336120900 ps
CPU time 69.4 seconds
Started Jul 22 05:28:25 PM PDT 24
Finished Jul 22 05:29:35 PM PDT 24
Peak memory 260620 kb
Host smart-68de1677-dfab-4222-86b4-9fe15b9be106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096931613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.3096931613
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.1380801140
Short name T80
Test name
Test status
Simulation time 1360496400 ps
CPU time 39.99 seconds
Started Jul 22 05:27:54 PM PDT 24
Finished Jul 22 05:28:35 PM PDT 24
Peak memory 265336 kb
Host smart-6634c513-e339-4b84-9a7a-6f851d18bbf4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380801140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.1380801140
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.1576770163
Short name T77
Test name
Test status
Simulation time 2000198700 ps
CPU time 95.64 seconds
Started Jul 22 05:31:48 PM PDT 24
Finished Jul 22 05:33:24 PM PDT 24
Peak memory 263492 kb
Host smart-f0706b1d-594a-4616-b820-c913ea2d422e
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576770163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.1
576770163
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.3149552876
Short name T129
Test name
Test status
Simulation time 35669635200 ps
CPU time 1347.59 seconds
Started Jul 22 05:29:26 PM PDT 24
Finished Jul 22 05:51:54 PM PDT 24
Peak memory 273852 kb
Host smart-5ee525c0-f541-4706-935e-91b12480709e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149552876 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.3149552876
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.3696547207
Short name T334
Test name
Test status
Simulation time 1653627900 ps
CPU time 276.48 seconds
Started Jul 22 05:32:05 PM PDT 24
Finished Jul 22 05:36:42 PM PDT 24
Peak memory 291428 kb
Host smart-2bda4f5f-a5fa-4932-b3ae-14cfaa7bdf32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696547207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.3696547207
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1088903991
Short name T260
Test name
Test status
Simulation time 204741100 ps
CPU time 18.55 seconds
Started Jul 22 06:18:58 PM PDT 24
Finished Jul 22 06:19:17 PM PDT 24
Peak memory 264104 kb
Host smart-5c61f5bc-4fa7-49a6-8899-c49186662dac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088903991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
1088903991
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.3800605731
Short name T522
Test name
Test status
Simulation time 15485100 ps
CPU time 13.56 seconds
Started Jul 22 05:31:10 PM PDT 24
Finished Jul 22 05:31:24 PM PDT 24
Peak memory 264984 kb
Host smart-ca591f9c-394f-4ab5-b318-75bd9b420f7a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800605731 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.3800605731
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.10299311
Short name T248
Test name
Test status
Simulation time 19207400 ps
CPU time 13.3 seconds
Started Jul 22 06:18:50 PM PDT 24
Finished Jul 22 06:19:04 PM PDT 24
Peak memory 262212 kb
Host smart-65f5ad43-1a93-4a46-badf-ebc257134e10
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10299311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_mem_partial_access.10299311
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.1267851606
Short name T209
Test name
Test status
Simulation time 3466259400 ps
CPU time 420.13 seconds
Started Jul 22 05:31:04 PM PDT 24
Finished Jul 22 05:38:05 PM PDT 24
Peak memory 309804 kb
Host smart-31ae3f2e-db29-4502-b087-e66499a56b34
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267851606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_rw.1267851606
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1982990193
Short name T68
Test name
Test status
Simulation time 177187500 ps
CPU time 21.11 seconds
Started Jul 22 06:18:50 PM PDT 24
Finished Jul 22 06:19:12 PM PDT 24
Peak memory 271644 kb
Host smart-5a09c381-5bc7-476c-8c2e-7307372bbb00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982990193 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.1982990193
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.2373561755
Short name T25
Test name
Test status
Simulation time 103518400 ps
CPU time 30.54 seconds
Started Jul 22 05:30:13 PM PDT 24
Finished Jul 22 05:30:44 PM PDT 24
Peak memory 275528 kb
Host smart-ceeda55f-29b4-4b9d-9597-5afc49d1bde8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373561755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_rw_evict.2373561755
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.2452194347
Short name T21
Test name
Test status
Simulation time 47041300 ps
CPU time 15.01 seconds
Started Jul 22 05:26:32 PM PDT 24
Finished Jul 22 05:26:47 PM PDT 24
Peak memory 260496 kb
Host smart-7359702d-c720-41be-8f40-1cdf1e1a4654
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452194347 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.2452194347
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.2661601719
Short name T39
Test name
Test status
Simulation time 4437823400 ps
CPU time 129.75 seconds
Started Jul 22 05:27:08 PM PDT 24
Finished Jul 22 05:29:18 PM PDT 24
Peak memory 281804 kb
Host smart-ca5ab91c-7071-4a2e-a16b-9dcac4f733db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661601719 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.2661601719
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.3122215817
Short name T189
Test name
Test status
Simulation time 290281253900 ps
CPU time 912.04 seconds
Started Jul 22 05:28:13 PM PDT 24
Finished Jul 22 05:43:25 PM PDT 24
Peak memory 265124 kb
Host smart-adda7c13-938e-4227-870a-8e48064aedfa
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122215817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.flash_ctrl_hw_rma_reset.3122215817
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.2745919088
Short name T59
Test name
Test status
Simulation time 1151568600 ps
CPU time 4793.21 seconds
Started Jul 22 05:26:45 PM PDT 24
Finished Jul 22 06:46:39 PM PDT 24
Peak memory 283860 kb
Host smart-7ce4edf1-67c3-4e6c-b1c2-a56b306b0d8b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745919088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.2745919088
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3015346377
Short name T332
Test name
Test status
Simulation time 27697800 ps
CPU time 14.33 seconds
Started Jul 22 06:19:15 PM PDT 24
Finished Jul 22 06:19:31 PM PDT 24
Peak memory 261300 kb
Host smart-08ad57c8-082d-4064-b5d3-f74c0ebff020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015346377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
3015346377
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.3552517917
Short name T61
Test name
Test status
Simulation time 796702200 ps
CPU time 969.51 seconds
Started Jul 22 05:27:03 PM PDT 24
Finished Jul 22 05:43:13 PM PDT 24
Peak memory 273636 kb
Host smart-084fd4aa-49a7-4e25-af88-34e6fca37874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552517917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.3552517917
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.2957978972
Short name T252
Test name
Test status
Simulation time 13315502100 ps
CPU time 706.79 seconds
Started Jul 22 05:25:58 PM PDT 24
Finished Jul 22 05:37:45 PM PDT 24
Peak memory 341416 kb
Host smart-7ccca78d-7b5d-4d7a-928d-951cdc100c1c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957978972 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_rw_derr.2957978972
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.1616572850
Short name T63
Test name
Test status
Simulation time 61556100 ps
CPU time 14.07 seconds
Started Jul 22 05:26:52 PM PDT 24
Finished Jul 22 05:27:06 PM PDT 24
Peak memory 276928 kb
Host smart-7da8bf2d-664a-4f4c-8d17-19fe3994d904
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1616572850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.1616572850
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.1590587015
Short name T313
Test name
Test status
Simulation time 19907129200 ps
CPU time 281.26 seconds
Started Jul 22 05:26:58 PM PDT 24
Finished Jul 22 05:31:40 PM PDT 24
Peak memory 262492 kb
Host smart-20cbf403-425a-45b2-8576-2b0dda9632d4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590587015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.1590587015
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.2952710643
Short name T275
Test name
Test status
Simulation time 4716632300 ps
CPU time 80.78 seconds
Started Jul 22 05:30:45 PM PDT 24
Finished Jul 22 05:32:06 PM PDT 24
Peak memory 263664 kb
Host smart-e40c2503-f9ab-4853-ad7e-a2074cacad51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952710643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2952710643
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.1499319160
Short name T348
Test name
Test status
Simulation time 71612700 ps
CPU time 34.16 seconds
Started Jul 22 05:30:21 PM PDT 24
Finished Jul 22 05:30:55 PM PDT 24
Peak memory 268508 kb
Host smart-aa8897a2-3822-43a1-93a5-3ec092b4b436
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499319160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.1499319160
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.1984847448
Short name T122
Test name
Test status
Simulation time 806958900 ps
CPU time 18.94 seconds
Started Jul 22 05:27:54 PM PDT 24
Finished Jul 22 05:28:13 PM PDT 24
Peak memory 264248 kb
Host smart-becbb20f-4589-45c8-b8b0-ff8f22571c8f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984847448 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.1984847448
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.1193173343
Short name T33
Test name
Test status
Simulation time 3041867100 ps
CPU time 148.2 seconds
Started Jul 22 05:34:17 PM PDT 24
Finished Jul 22 05:36:45 PM PDT 24
Peak memory 294096 kb
Host smart-b2dc8153-2c00-41fc-b139-428f0e9cd8fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193173343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.1193173343
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.1273221945
Short name T140
Test name
Test status
Simulation time 47414200 ps
CPU time 13.58 seconds
Started Jul 22 05:31:26 PM PDT 24
Finished Jul 22 05:31:40 PM PDT 24
Peak memory 258600 kb
Host smart-6a8ee9c0-0429-4c50-9822-7f02a66f1c91
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273221945 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.1273221945
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2088748049
Short name T309
Test name
Test status
Simulation time 48829500 ps
CPU time 47.41 seconds
Started Jul 22 06:18:39 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 262656 kb
Host smart-a78d47f4-204e-49f3-9cde-29f7e6d07435
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088748049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.2088748049
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.1841302682
Short name T634
Test name
Test status
Simulation time 16075100 ps
CPU time 14.11 seconds
Started Jul 22 05:26:33 PM PDT 24
Finished Jul 22 05:26:48 PM PDT 24
Peak memory 264944 kb
Host smart-95387131-58a4-4ee0-902a-07617d18254d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841302682 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.1841302682
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.3125211289
Short name T9
Test name
Test status
Simulation time 21719500 ps
CPU time 13.91 seconds
Started Jul 22 05:26:30 PM PDT 24
Finished Jul 22 05:26:44 PM PDT 24
Peak memory 265288 kb
Host smart-91c2f7bf-3f1a-43dc-8527-74a78028ec92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125211289 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.3125211289
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.2316596989
Short name T422
Test name
Test status
Simulation time 1046591800 ps
CPU time 61.19 seconds
Started Jul 22 05:31:50 PM PDT 24
Finished Jul 22 05:32:52 PM PDT 24
Peak memory 263116 kb
Host smart-0eb7b7e3-bb83-45ca-ac13-ea747e79ed08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316596989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.2316596989
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.667028600
Short name T1212
Test name
Test status
Simulation time 309048000 ps
CPU time 19.5 seconds
Started Jul 22 06:18:39 PM PDT 24
Finished Jul 22 06:18:59 PM PDT 24
Peak memory 264152 kb
Host smart-cc64fe14-1263-4555-a031-557d34068cd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667028600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.667028600
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_derr.1257332040
Short name T211
Test name
Test status
Simulation time 8055009600 ps
CPU time 586.07 seconds
Started Jul 22 05:28:54 PM PDT 24
Finished Jul 22 05:38:41 PM PDT 24
Peak memory 333820 kb
Host smart-be783a3c-535d-40ae-ae87-66b46a2a0517
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257332040 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_rw_derr.1257332040
Directory /workspace/7.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.1799262968
Short name T102
Test name
Test status
Simulation time 14752900 ps
CPU time 15.6 seconds
Started Jul 22 05:33:33 PM PDT 24
Finished Jul 22 05:33:49 PM PDT 24
Peak memory 274872 kb
Host smart-18c5f221-9eb6-4d58-821d-55ec24a3b4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799262968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.1799262968
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.4158589503
Short name T86
Test name
Test status
Simulation time 1110467200 ps
CPU time 2890.19 seconds
Started Jul 22 05:28:52 PM PDT 24
Finished Jul 22 06:17:03 PM PDT 24
Peak memory 262064 kb
Host smart-c233e671-7b0f-41be-b1a7-f41e07ceef8e
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158589503 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.4158589503
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.4015184065
Short name T264
Test name
Test status
Simulation time 1578727600 ps
CPU time 464.49 seconds
Started Jul 22 06:20:42 PM PDT 24
Finished Jul 22 06:28:27 PM PDT 24
Peak memory 264020 kb
Host smart-d65eac42-5cae-4e52-90af-00356709cc0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015184065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.4015184065
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.2387311578
Short name T138
Test name
Test status
Simulation time 673519700 ps
CPU time 154.59 seconds
Started Jul 22 05:27:24 PM PDT 24
Finished Jul 22 05:29:59 PM PDT 24
Peak memory 282884 kb
Host smart-15a9d962-0e4f-4157-9a74-70452b645392
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2387311578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.2387311578
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.550414591
Short name T206
Test name
Test status
Simulation time 80136605300 ps
CPU time 817.89 seconds
Started Jul 22 05:31:57 PM PDT 24
Finished Jul 22 05:45:35 PM PDT 24
Peak memory 263500 kb
Host smart-d13e2fc0-ea8f-4687-8a4f-8aa24b29adb8
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550414591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.flash_ctrl_hw_rma_reset.550414591
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.2455931927
Short name T296
Test name
Test status
Simulation time 10031801900 ps
CPU time 59.42 seconds
Started Jul 22 05:31:24 PM PDT 24
Finished Jul 22 05:32:23 PM PDT 24
Peak memory 273236 kb
Host smart-914e9b5a-e497-4f1c-884c-c75e7747325e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455931927 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.2455931927
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.1098256419
Short name T343
Test name
Test status
Simulation time 11422700 ps
CPU time 21.89 seconds
Started Jul 22 05:26:07 PM PDT 24
Finished Jul 22 05:26:30 PM PDT 24
Peak memory 273564 kb
Host smart-f036cbd7-6940-4bb7-9129-fb39d40525c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098256419 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.1098256419
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.817847873
Short name T822
Test name
Test status
Simulation time 26676500 ps
CPU time 13.43 seconds
Started Jul 22 05:26:09 PM PDT 24
Finished Jul 22 05:26:23 PM PDT 24
Peak memory 260180 kb
Host smart-616f4d8c-a5c0-4050-a6bc-b4b2c77aa2a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817847873 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.817847873
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.878823239
Short name T350
Test name
Test status
Simulation time 5375860100 ps
CPU time 37.29 seconds
Started Jul 22 05:26:50 PM PDT 24
Finished Jul 22 05:27:27 PM PDT 24
Peak memory 264852 kb
Host smart-5dc3cdff-f570-4e4c-b79e-a0d85a58f70a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878823239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_fs_sup.878823239
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.3555473368
Short name T421
Test name
Test status
Simulation time 2342669100 ps
CPU time 69.84 seconds
Started Jul 22 05:32:53 PM PDT 24
Finished Jul 22 05:34:03 PM PDT 24
Peak memory 263812 kb
Host smart-401a5690-b13e-449c-a9c1-33c351bcb638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555473368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.3555473368
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.2162569437
Short name T792
Test name
Test status
Simulation time 2312449400 ps
CPU time 80.09 seconds
Started Jul 22 05:33:14 PM PDT 24
Finished Jul 22 05:34:35 PM PDT 24
Peak memory 263676 kb
Host smart-3000d54a-1c53-4e5f-8686-b6299c8f72d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162569437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.2162569437
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.218895494
Short name T29
Test name
Test status
Simulation time 29895654600 ps
CPU time 180.14 seconds
Started Jul 22 05:27:45 PM PDT 24
Finished Jul 22 05:30:46 PM PDT 24
Peak memory 260688 kb
Host smart-1c16b40a-5617-40c1-9162-d1084b151aeb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218
895494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.218895494
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.2195876026
Short name T123
Test name
Test status
Simulation time 806325100 ps
CPU time 22.17 seconds
Started Jul 22 05:26:51 PM PDT 24
Finished Jul 22 05:27:14 PM PDT 24
Peak memory 265428 kb
Host smart-094a9e28-19c2-4ead-83ed-0613553fdbad
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195876026 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.2195876026
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.1592414393
Short name T284
Test name
Test status
Simulation time 307323600 ps
CPU time 71.15 seconds
Started Jul 22 05:26:53 PM PDT 24
Finished Jul 22 05:28:04 PM PDT 24
Peak memory 265172 kb
Host smart-3da9b403-c566-4c6c-998b-41b34eb4fa31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1592414393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.1592414393
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.2998637392
Short name T125
Test name
Test status
Simulation time 846696700 ps
CPU time 17.46 seconds
Started Jul 22 05:26:31 PM PDT 24
Finished Jul 22 05:26:49 PM PDT 24
Peak memory 265584 kb
Host smart-06e10396-e964-423b-b05b-df41213da818
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998637392 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.2998637392
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.438661308
Short name T364
Test name
Test status
Simulation time 205626800 ps
CPU time 19.39 seconds
Started Jul 22 06:18:47 PM PDT 24
Finished Jul 22 06:19:07 PM PDT 24
Peak memory 272304 kb
Host smart-0f6cb59f-7431-4bf4-91ef-34027e3be598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438661308 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.438661308
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3954187237
Short name T367
Test name
Test status
Simulation time 205266200 ps
CPU time 386.69 seconds
Started Jul 22 06:20:05 PM PDT 24
Finished Jul 22 06:26:40 PM PDT 24
Peak memory 264104 kb
Host smart-d7f414aa-0be3-4b09-b682-091b09fa601c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954187237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.3954187237
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3270195891
Short name T374
Test name
Test status
Simulation time 331648200 ps
CPU time 898.17 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:34:06 PM PDT 24
Peak memory 264084 kb
Host smart-a8dbfc04-002b-4670-a131-b7effe925478
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270195891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.3270195891
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3470346453
Short name T244
Test name
Test status
Simulation time 255709400 ps
CPU time 382.49 seconds
Started Jul 22 06:18:48 PM PDT 24
Finished Jul 22 06:25:11 PM PDT 24
Peak memory 264092 kb
Host smart-552983b2-bef9-4007-9380-bd86b8e28891
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470346453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.3470346453
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.3623456222
Short name T255
Test name
Test status
Simulation time 74641700 ps
CPU time 13.71 seconds
Started Jul 22 05:26:08 PM PDT 24
Finished Jul 22 05:26:22 PM PDT 24
Peak memory 264964 kb
Host smart-02bcde9d-a1f5-416a-96a3-23eceff546a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623456222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.3623456222
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.582609458
Short name T152
Test name
Test status
Simulation time 81126819400 ps
CPU time 2512.74 seconds
Started Jul 22 05:25:47 PM PDT 24
Finished Jul 22 06:07:41 PM PDT 24
Peak memory 265220 kb
Host smart-e8db3a03-80a4-43de-8234-f5cc8480cdc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582609458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct
rl_full_mem_access.582609458
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.3022541824
Short name T251
Test name
Test status
Simulation time 18795000 ps
CPU time 20.85 seconds
Started Jul 22 05:26:36 PM PDT 24
Finished Jul 22 05:26:57 PM PDT 24
Peak memory 273508 kb
Host smart-bcb128b3-dc89-415b-859f-68e08f9a7ef8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022541824 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.3022541824
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.1698178741
Short name T974
Test name
Test status
Simulation time 20327100 ps
CPU time 21.8 seconds
Started Jul 22 05:30:14 PM PDT 24
Finished Jul 22 05:30:37 PM PDT 24
Peak memory 273612 kb
Host smart-d14a43b9-a28c-4943-a36d-da7eea4b0eec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698178741 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.1698178741
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.1641690973
Short name T1031
Test name
Test status
Simulation time 1020461800 ps
CPU time 88.07 seconds
Started Jul 22 05:29:56 PM PDT 24
Finished Jul 22 05:31:25 PM PDT 24
Peak memory 260660 kb
Host smart-a6658287-4605-40d9-8f80-252efba43dc6
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641690973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.1
641690973
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.2158299795
Short name T483
Test name
Test status
Simulation time 2571507500 ps
CPU time 63.89 seconds
Started Jul 22 05:30:38 PM PDT 24
Finished Jul 22 05:31:44 PM PDT 24
Peak memory 263120 kb
Host smart-f794349f-2b61-4fb7-9a8a-a3e0e13decbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158299795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.2158299795
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.4136087941
Short name T418
Test name
Test status
Simulation time 1705528900 ps
CPU time 62.5 seconds
Started Jul 22 05:30:58 PM PDT 24
Finished Jul 22 05:32:01 PM PDT 24
Peak memory 264856 kb
Host smart-abfe9dc2-1262-42fd-8298-8d59505e96b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136087941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.4136087941
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.1707557103
Short name T923
Test name
Test status
Simulation time 47111100 ps
CPU time 20.39 seconds
Started Jul 22 05:31:22 PM PDT 24
Finished Jul 22 05:31:43 PM PDT 24
Peak memory 273900 kb
Host smart-6cb5409d-a881-4e1e-ad8f-b7e064e92eb8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707557103 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.1707557103
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.1848436623
Short name T220
Test name
Test status
Simulation time 32910300 ps
CPU time 32.21 seconds
Started Jul 22 05:31:18 PM PDT 24
Finished Jul 22 05:31:50 PM PDT 24
Peak memory 275716 kb
Host smart-f6fd41c8-5528-4b99-8b20-4ecf3db3c94b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848436623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_rw_evict.1848436623
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.3337587491
Short name T186
Test name
Test status
Simulation time 142407400 ps
CPU time 111.14 seconds
Started Jul 22 05:31:32 PM PDT 24
Finished Jul 22 05:33:23 PM PDT 24
Peak memory 265392 kb
Host smart-dc64556e-8d8c-4b84-89b4-97068f68dfc5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337587491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.3337587491
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.2478474353
Short name T407
Test name
Test status
Simulation time 471583600 ps
CPU time 60.08 seconds
Started Jul 22 05:32:16 PM PDT 24
Finished Jul 22 05:33:16 PM PDT 24
Peak memory 263184 kb
Host smart-62aa2b53-6cb2-4da7-8eb9-76009d142fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478474353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.2478474353
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.1052549416
Short name T360
Test name
Test status
Simulation time 100766600 ps
CPU time 31.77 seconds
Started Jul 22 05:33:00 PM PDT 24
Finished Jul 22 05:33:32 PM PDT 24
Peak memory 275580 kb
Host smart-8f351473-b47f-4996-bd78-062195466048
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052549416 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.1052549416
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.1475750280
Short name T540
Test name
Test status
Simulation time 10797000 ps
CPU time 21.01 seconds
Started Jul 22 05:33:03 PM PDT 24
Finished Jul 22 05:33:25 PM PDT 24
Peak memory 273656 kb
Host smart-ac301882-924c-4b8a-b022-5bb8c1075cf4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475750280 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.1475750280
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.100016916
Short name T357
Test name
Test status
Simulation time 32130300 ps
CPU time 28.68 seconds
Started Jul 22 05:29:21 PM PDT 24
Finished Jul 22 05:29:50 PM PDT 24
Peak memory 275624 kb
Host smart-467c7891-e443-4d0a-b3b5-63ed534042a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100016916 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.100016916
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.3651955649
Short name T216
Test name
Test status
Simulation time 2297321100 ps
CPU time 143.69 seconds
Started Jul 22 05:26:34 PM PDT 24
Finished Jul 22 05:28:59 PM PDT 24
Peak memory 281696 kb
Host smart-eaa927f4-cf5e-4c20-a2e6-ce1fab98eeb5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3651955649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.3651955649
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.829689108
Short name T215
Test name
Test status
Simulation time 1273674400 ps
CPU time 164.02 seconds
Started Jul 22 05:28:36 PM PDT 24
Finished Jul 22 05:31:21 PM PDT 24
Peak memory 281900 kb
Host smart-e5a00847-448b-48c3-be7a-c21f1437e7e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
829689108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.829689108
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.2497390640
Short name T489
Test name
Test status
Simulation time 30120200 ps
CPU time 15.78 seconds
Started Jul 22 05:30:19 PM PDT 24
Finished Jul 22 05:30:36 PM PDT 24
Peak memory 274940 kb
Host smart-fe7b402f-4d37-4fe3-9b09-738cf7f288c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497390640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.2497390640
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.257140379
Short name T272
Test name
Test status
Simulation time 671857400 ps
CPU time 18.81 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 264124 kb
Host smart-dab99c95-af45-47ce-b425-3a55b0e203f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257140379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.257140379
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.2438345213
Short name T174
Test name
Test status
Simulation time 5795879200 ps
CPU time 361.25 seconds
Started Jul 22 05:28:52 PM PDT 24
Finished Jul 22 05:34:54 PM PDT 24
Peak memory 263504 kb
Host smart-dec5b3b6-d534-4b6b-9a2d-3d64efd26280
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2438345213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.2438345213
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.1658070587
Short name T38
Test name
Test status
Simulation time 646086800 ps
CPU time 42.79 seconds
Started Jul 22 05:26:08 PM PDT 24
Finished Jul 22 05:26:51 PM PDT 24
Peak memory 265208 kb
Host smart-19ed4be0-d415-42c2-8266-bc6593af8ca0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658070587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_fs_sup.1658070587
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.3802862476
Short name T229
Test name
Test status
Simulation time 60174300 ps
CPU time 16.14 seconds
Started Jul 22 05:26:06 PM PDT 24
Finished Jul 22 05:26:23 PM PDT 24
Peak memory 261808 kb
Host smart-87fce89d-2274-4d60-b428-e1506bccfdb4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3802862476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.3802862476
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.4205716074
Short name T188
Test name
Test status
Simulation time 80150972200 ps
CPU time 871.38 seconds
Started Jul 22 05:31:07 PM PDT 24
Finished Jul 22 05:45:39 PM PDT 24
Peak memory 265312 kb
Host smart-1589b5cb-36c6-4447-a316-1b2333a2200b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205716074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.4205716074
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.3163734922
Short name T88
Test name
Test status
Simulation time 47585575800 ps
CPU time 291.8 seconds
Started Jul 22 05:31:51 PM PDT 24
Finished Jul 22 05:36:43 PM PDT 24
Peak memory 293164 kb
Host smart-757f1ddc-2cb9-47ad-be05-019e05b860e6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163734922 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.3163734922
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3690379227
Short name T266
Test name
Test status
Simulation time 3139697900 ps
CPU time 384.4 seconds
Started Jul 22 06:18:45 PM PDT 24
Finished Jul 22 06:25:10 PM PDT 24
Peak memory 264116 kb
Host smart-18056a23-b4e3-4012-a8f3-19999c12c137
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690379227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.3690379227
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.2710707268
Short name T10
Test name
Test status
Simulation time 20118300 ps
CPU time 13.53 seconds
Started Jul 22 05:26:07 PM PDT 24
Finished Jul 22 05:26:21 PM PDT 24
Peak memory 261252 kb
Host smart-34cdb901-c822-48f8-ac3a-88463c6c9b7a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710707268 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.2710707268
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.1381876105
Short name T300
Test name
Test status
Simulation time 3134167500 ps
CPU time 2212.1 seconds
Started Jul 22 05:26:09 PM PDT 24
Finished Jul 22 06:03:02 PM PDT 24
Peak memory 262856 kb
Host smart-f55ec01c-4079-4412-95c8-256cc352c093
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1381876105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.1381876105
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.2974198520
Short name T52
Test name
Test status
Simulation time 118669000 ps
CPU time 23.3 seconds
Started Jul 22 05:26:15 PM PDT 24
Finished Jul 22 05:26:40 PM PDT 24
Peak memory 263448 kb
Host smart-2a136d8b-615c-4c3a-8b77-80930d9534f6
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974198520 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_fetch_code.2974198520
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.1578202881
Short name T207
Test name
Test status
Simulation time 253100954500 ps
CPU time 2630.69 seconds
Started Jul 22 05:26:16 PM PDT 24
Finished Jul 22 06:10:08 PM PDT 24
Peak memory 264088 kb
Host smart-3f8ccd47-5e52-4f7f-bce9-7efcde330c34
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578202881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.1578202881
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.2090247956
Short name T58
Test name
Test status
Simulation time 6104147300 ps
CPU time 4712.05 seconds
Started Jul 22 05:26:32 PM PDT 24
Finished Jul 22 06:45:05 PM PDT 24
Peak memory 295020 kb
Host smart-1cfabc80-34db-4396-91db-57bd65e2ac95
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090247956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.2090247956
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.1521974078
Short name T95
Test name
Test status
Simulation time 15866741600 ps
CPU time 640.06 seconds
Started Jul 22 05:28:13 PM PDT 24
Finished Jul 22 05:38:53 PM PDT 24
Peak memory 313088 kb
Host smart-7e04e5a8-1673-401a-8706-0fb1bf4602f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521974078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s
err.1521974078
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_derr.797357902
Short name T217
Test name
Test status
Simulation time 3497903500 ps
CPU time 585.72 seconds
Started Jul 22 05:29:35 PM PDT 24
Finished Jul 22 05:39:21 PM PDT 24
Peak memory 326688 kb
Host smart-ebb421af-a357-4b01-8d85-a04bd7dbe9d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797357902 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.flash_ctrl_rw_derr.797357902
Directory /workspace/9.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1663977529
Short name T1192
Test name
Test status
Simulation time 253004800 ps
CPU time 34.78 seconds
Started Jul 22 06:19:58 PM PDT 24
Finished Jul 22 06:20:34 PM PDT 24
Peak memory 261688 kb
Host smart-febec02d-d8e7-4c87-be6b-cede6bc88f0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663977529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.1663977529
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3678119396
Short name T1234
Test name
Test status
Simulation time 4939297800 ps
CPU time 47.17 seconds
Started Jul 22 06:19:58 PM PDT 24
Finished Jul 22 06:20:47 PM PDT 24
Peak memory 261688 kb
Host smart-bdcb75ac-a265-42b7-a22c-55e667984829
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678119396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.3678119396
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1213651750
Short name T241
Test name
Test status
Simulation time 161147900 ps
CPU time 19.65 seconds
Started Jul 22 06:18:47 PM PDT 24
Finished Jul 22 06:19:07 PM PDT 24
Peak memory 279572 kb
Host smart-592b52c5-ee21-462d-ab2f-2da86ccbad6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213651750 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.1213651750
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1623782545
Short name T1125
Test name
Test status
Simulation time 131113300 ps
CPU time 17.02 seconds
Started Jul 22 06:18:39 PM PDT 24
Finished Jul 22 06:18:57 PM PDT 24
Peak memory 261500 kb
Host smart-d06404c6-5519-49ec-81a3-da26737f0998
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623782545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.1623782545
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.4102643934
Short name T1120
Test name
Test status
Simulation time 29241900 ps
CPU time 13.94 seconds
Started Jul 22 06:18:39 PM PDT 24
Finished Jul 22 06:18:54 PM PDT 24
Peak memory 261476 kb
Host smart-9d243002-eba1-47df-85cd-999016605c9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102643934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.4
102643934
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1394965360
Short name T245
Test name
Test status
Simulation time 24536600 ps
CPU time 13.55 seconds
Started Jul 22 06:18:36 PM PDT 24
Finished Jul 22 06:18:49 PM PDT 24
Peak memory 262424 kb
Host smart-2f834986-85de-4778-9df2-333228dc99bd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394965360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.1394965360
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1754978345
Short name T1254
Test name
Test status
Simulation time 195963200 ps
CPU time 13.45 seconds
Started Jul 22 06:18:38 PM PDT 24
Finished Jul 22 06:18:52 PM PDT 24
Peak memory 261388 kb
Host smart-d6f4fff3-ddf4-45f0-86cc-70511d2c763b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754978345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.1754978345
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.729302272
Short name T308
Test name
Test status
Simulation time 425807800 ps
CPU time 18.83 seconds
Started Jul 22 06:18:39 PM PDT 24
Finished Jul 22 06:18:58 PM PDT 24
Peak memory 260696 kb
Host smart-c92cf8b7-e168-4a2a-90e6-a077799676a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729302272 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.729302272
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.136646673
Short name T1223
Test name
Test status
Simulation time 34667400 ps
CPU time 16.02 seconds
Started Jul 22 06:18:38 PM PDT 24
Finished Jul 22 06:18:55 PM PDT 24
Peak memory 253104 kb
Host smart-5f8496ba-ab0a-433e-aee9-9f4fc6ea0b61
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136646673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.136646673
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3493820047
Short name T1114
Test name
Test status
Simulation time 24646000 ps
CPU time 15.88 seconds
Started Jul 22 06:18:38 PM PDT 24
Finished Jul 22 06:18:55 PM PDT 24
Peak memory 253220 kb
Host smart-ab75f089-de6e-4344-a432-692790897d71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493820047 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.3493820047
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2689859587
Short name T1236
Test name
Test status
Simulation time 83257800 ps
CPU time 19.43 seconds
Started Jul 22 06:18:37 PM PDT 24
Finished Jul 22 06:18:57 PM PDT 24
Peak memory 264056 kb
Host smart-555716ab-718f-4c69-985a-787fd12895f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689859587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.2
689859587
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.741654075
Short name T368
Test name
Test status
Simulation time 690304800 ps
CPU time 911 seconds
Started Jul 22 06:18:39 PM PDT 24
Finished Jul 22 06:33:50 PM PDT 24
Peak memory 264092 kb
Host smart-85ef3bab-bf49-48b6-b51b-d0ce088fa93a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741654075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_
tl_intg_err.741654075
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.941494023
Short name T1123
Test name
Test status
Simulation time 452295300 ps
CPU time 31.93 seconds
Started Jul 22 06:19:24 PM PDT 24
Finished Jul 22 06:19:58 PM PDT 24
Peak memory 261632 kb
Host smart-f51d54ec-f7e9-41c1-a63d-09046ba94799
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941494023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.flash_ctrl_csr_aliasing.941494023
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1112048870
Short name T66
Test name
Test status
Simulation time 6362931900 ps
CPU time 42.17 seconds
Started Jul 22 06:18:47 PM PDT 24
Finished Jul 22 06:19:30 PM PDT 24
Peak memory 261612 kb
Host smart-e859f892-a53c-4a8f-8bec-10041591884c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112048870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.1112048870
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1215512363
Short name T1191
Test name
Test status
Simulation time 45300700 ps
CPU time 46.46 seconds
Started Jul 22 06:18:38 PM PDT 24
Finished Jul 22 06:19:25 PM PDT 24
Peak memory 261308 kb
Host smart-9bcdbefb-a382-4e59-8194-1b47433171b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215512363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.1215512363
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3139209518
Short name T1241
Test name
Test status
Simulation time 59628100 ps
CPU time 16.64 seconds
Started Jul 22 06:19:33 PM PDT 24
Finished Jul 22 06:19:51 PM PDT 24
Peak memory 264052 kb
Host smart-557f297e-dfb8-4217-80f4-a497b9cdd901
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139209518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.3139209518
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3032884024
Short name T1140
Test name
Test status
Simulation time 50900500 ps
CPU time 13.41 seconds
Started Jul 22 06:18:36 PM PDT 24
Finished Jul 22 06:18:50 PM PDT 24
Peak memory 261556 kb
Host smart-55d1a0e7-fffb-4fc6-86b2-7cddb10357c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032884024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.3
032884024
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.4214935477
Short name T249
Test name
Test status
Simulation time 18630200 ps
CPU time 14.06 seconds
Started Jul 22 06:18:37 PM PDT 24
Finished Jul 22 06:18:52 PM PDT 24
Peak memory 263012 kb
Host smart-8ea42085-54e4-4a63-b62d-6e24046be98c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214935477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.4214935477
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3145452852
Short name T1154
Test name
Test status
Simulation time 18442700 ps
CPU time 13.96 seconds
Started Jul 22 06:18:37 PM PDT 24
Finished Jul 22 06:18:52 PM PDT 24
Peak memory 261432 kb
Host smart-7f68177d-12bd-4de6-9f3c-dc8925a62b50
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145452852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.3145452852
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3384828583
Short name T1195
Test name
Test status
Simulation time 1014538700 ps
CPU time 16.75 seconds
Started Jul 22 06:18:45 PM PDT 24
Finished Jul 22 06:19:03 PM PDT 24
Peak memory 263992 kb
Host smart-0abb7d1b-ac0d-4476-8903-bf5048922dbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384828583 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.3384828583
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3756461370
Short name T1194
Test name
Test status
Simulation time 34334000 ps
CPU time 16.17 seconds
Started Jul 22 06:18:39 PM PDT 24
Finished Jul 22 06:18:56 PM PDT 24
Peak memory 253268 kb
Host smart-6c0856e8-765d-4919-88bb-214974263c75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756461370 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.3756461370
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2425873192
Short name T1109
Test name
Test status
Simulation time 42063200 ps
CPU time 15.63 seconds
Started Jul 22 06:18:36 PM PDT 24
Finished Jul 22 06:18:53 PM PDT 24
Peak memory 253412 kb
Host smart-99242c67-61d9-421e-a196-00dd88c0d607
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425873192 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.2425873192
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1732368010
Short name T239
Test name
Test status
Simulation time 220697700 ps
CPU time 17.23 seconds
Started Jul 22 06:18:56 PM PDT 24
Finished Jul 22 06:19:14 PM PDT 24
Peak memory 272272 kb
Host smart-01fd3966-4c37-4e5d-93b0-c610774bb055
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732368010 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.1732368010
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3551401593
Short name T1161
Test name
Test status
Simulation time 84487200 ps
CPU time 17.38 seconds
Started Jul 22 06:19:28 PM PDT 24
Finished Jul 22 06:19:46 PM PDT 24
Peak memory 264056 kb
Host smart-40a56c06-e7a1-4bb2-a4a8-e720ceb20e9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551401593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.3551401593
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3592956914
Short name T1224
Test name
Test status
Simulation time 24624200 ps
CPU time 13.25 seconds
Started Jul 22 06:18:54 PM PDT 24
Finished Jul 22 06:19:08 PM PDT 24
Peak memory 261528 kb
Host smart-a199f26b-8ed6-4846-8ed1-696cbf158ae9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592956914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
3592956914
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1565301290
Short name T305
Test name
Test status
Simulation time 1548055500 ps
CPU time 21.59 seconds
Started Jul 22 06:18:59 PM PDT 24
Finished Jul 22 06:19:21 PM PDT 24
Peak memory 261852 kb
Host smart-f4e526a5-a86c-48ed-97e7-700f7a26205b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565301290 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.1565301290
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2273029403
Short name T1246
Test name
Test status
Simulation time 21997900 ps
CPU time 16.1 seconds
Started Jul 22 06:18:57 PM PDT 24
Finished Jul 22 06:19:14 PM PDT 24
Peak memory 253236 kb
Host smart-0f61da25-24c8-4de9-8fd9-439b5333a1f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273029403 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.2273029403
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2789436431
Short name T1231
Test name
Test status
Simulation time 13150800 ps
CPU time 15.92 seconds
Started Jul 22 06:19:08 PM PDT 24
Finished Jul 22 06:19:25 PM PDT 24
Peak memory 253072 kb
Host smart-e9e43238-bc00-4dd4-994f-a83af69ac597
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789436431 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.2789436431
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2847588187
Short name T1240
Test name
Test status
Simulation time 110719700 ps
CPU time 16 seconds
Started Jul 22 06:18:55 PM PDT 24
Finished Jul 22 06:19:12 PM PDT 24
Peak memory 264120 kb
Host smart-3de49e9e-e3bf-49ef-9f0d-abb83fef5588
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847588187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
2847588187
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.841674609
Short name T1227
Test name
Test status
Simulation time 25087800 ps
CPU time 15.33 seconds
Started Jul 22 06:19:24 PM PDT 24
Finished Jul 22 06:19:42 PM PDT 24
Peak memory 276916 kb
Host smart-d3f04099-7315-4480-b062-0a34ff9045b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841674609 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.841674609
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2209468540
Short name T257
Test name
Test status
Simulation time 69854900 ps
CPU time 18.03 seconds
Started Jul 22 06:20:43 PM PDT 24
Finished Jul 22 06:21:02 PM PDT 24
Peak memory 264012 kb
Host smart-34698b00-e8db-41d6-b0b2-22bc9ce20867
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209468540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.2209468540
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2206680263
Short name T1142
Test name
Test status
Simulation time 33745000 ps
CPU time 13.38 seconds
Started Jul 22 06:18:55 PM PDT 24
Finished Jul 22 06:19:10 PM PDT 24
Peak memory 261540 kb
Host smart-c732f057-906f-480c-b97d-693f8a3002b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206680263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
2206680263
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.644036240
Short name T1132
Test name
Test status
Simulation time 257680500 ps
CPU time 34.44 seconds
Started Jul 22 06:20:43 PM PDT 24
Finished Jul 22 06:21:18 PM PDT 24
Peak memory 263848 kb
Host smart-81451c08-3d75-4eec-baee-a7ac863f26c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644036240 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.644036240
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2635587636
Short name T1222
Test name
Test status
Simulation time 147322800 ps
CPU time 16.1 seconds
Started Jul 22 06:18:56 PM PDT 24
Finished Jul 22 06:19:13 PM PDT 24
Peak memory 253188 kb
Host smart-1aa33eef-4956-40b0-811f-1a0856a089c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635587636 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.2635587636
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3384529432
Short name T1124
Test name
Test status
Simulation time 17129700 ps
CPU time 16.18 seconds
Started Jul 22 06:18:57 PM PDT 24
Finished Jul 22 06:19:14 PM PDT 24
Peak memory 253104 kb
Host smart-813a9e55-8e7c-4266-b466-e7d985ecf873
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384529432 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.3384529432
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3568614854
Short name T224
Test name
Test status
Simulation time 54173600 ps
CPU time 19.72 seconds
Started Jul 22 06:18:55 PM PDT 24
Finished Jul 22 06:19:16 PM PDT 24
Peak memory 264072 kb
Host smart-d582efea-afd3-43d5-8833-2a365a965f41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568614854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
3568614854
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.833925058
Short name T371
Test name
Test status
Simulation time 4278012300 ps
CPU time 770.82 seconds
Started Jul 22 06:18:56 PM PDT 24
Finished Jul 22 06:31:48 PM PDT 24
Peak memory 264084 kb
Host smart-bc1edf3f-75bb-470e-b2dd-c5a77062868a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833925058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl
_tl_intg_err.833925058
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.593317730
Short name T303
Test name
Test status
Simulation time 102437700 ps
CPU time 17.19 seconds
Started Jul 22 06:20:43 PM PDT 24
Finished Jul 22 06:21:01 PM PDT 24
Peak memory 270688 kb
Host smart-1aa64557-dd21-411d-8b79-96868de6ca7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593317730 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.593317730
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3348661504
Short name T1179
Test name
Test status
Simulation time 32978600 ps
CPU time 16.96 seconds
Started Jul 22 06:18:56 PM PDT 24
Finished Jul 22 06:19:14 PM PDT 24
Peak memory 264208 kb
Host smart-344b6cb3-d34d-459e-bf43-261cb2eab774
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348661504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.3348661504
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3446121808
Short name T1148
Test name
Test status
Simulation time 49898100 ps
CPU time 13.54 seconds
Started Jul 22 06:19:08 PM PDT 24
Finished Jul 22 06:19:23 PM PDT 24
Peak memory 261528 kb
Host smart-666254c0-cc45-4a58-a590-1d29a637f665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446121808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
3446121808
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2396410063
Short name T304
Test name
Test status
Simulation time 1184540900 ps
CPU time 16.49 seconds
Started Jul 22 06:18:57 PM PDT 24
Finished Jul 22 06:19:14 PM PDT 24
Peak memory 262664 kb
Host smart-6c3239b5-1fb9-4b8c-acf6-2bea670b0381
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396410063 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.2396410063
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3761423272
Short name T1117
Test name
Test status
Simulation time 14926200 ps
CPU time 13.17 seconds
Started Jul 22 06:19:36 PM PDT 24
Finished Jul 22 06:19:50 PM PDT 24
Peak memory 253228 kb
Host smart-d8cf8431-23c1-4534-9e7f-3c9933482f02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761423272 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.3761423272
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3539920200
Short name T1197
Test name
Test status
Simulation time 30987200 ps
CPU time 15.73 seconds
Started Jul 22 06:19:33 PM PDT 24
Finished Jul 22 06:19:49 PM PDT 24
Peak memory 253308 kb
Host smart-485f7595-39a9-46ad-8f36-1f40f91b451e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539920200 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.3539920200
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.686765876
Short name T365
Test name
Test status
Simulation time 1596685800 ps
CPU time 917.01 seconds
Started Jul 22 06:18:56 PM PDT 24
Finished Jul 22 06:34:14 PM PDT 24
Peak memory 264084 kb
Host smart-e1d6b5f7-4af0-40ea-b54d-cb28cff6fd36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686765876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl
_tl_intg_err.686765876
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2099113584
Short name T1165
Test name
Test status
Simulation time 75641200 ps
CPU time 14.93 seconds
Started Jul 22 06:19:05 PM PDT 24
Finished Jul 22 06:19:20 PM PDT 24
Peak memory 264088 kb
Host smart-ca0447d9-fc2a-4451-a9b0-e217fb9c1d88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099113584 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.2099113584
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.188321281
Short name T1251
Test name
Test status
Simulation time 83991700 ps
CPU time 16.46 seconds
Started Jul 22 06:19:09 PM PDT 24
Finished Jul 22 06:19:26 PM PDT 24
Peak memory 264072 kb
Host smart-5e66b8d7-3291-4e3a-a298-d63f6d57bdc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188321281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.flash_ctrl_csr_rw.188321281
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1206974848
Short name T1193
Test name
Test status
Simulation time 31535900 ps
CPU time 13.78 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 261492 kb
Host smart-5d1a5ef2-e756-402d-be06-1e397fd48991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206974848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.
1206974848
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2671900517
Short name T1196
Test name
Test status
Simulation time 164229700 ps
CPU time 18.25 seconds
Started Jul 22 06:19:04 PM PDT 24
Finished Jul 22 06:19:23 PM PDT 24
Peak memory 264108 kb
Host smart-e0b58e6d-5113-445a-a439-b02c9ee7691a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671900517 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.2671900517
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.705892872
Short name T1182
Test name
Test status
Simulation time 13848800 ps
CPU time 15.69 seconds
Started Jul 22 06:19:21 PM PDT 24
Finished Jul 22 06:19:39 PM PDT 24
Peak memory 253148 kb
Host smart-2cbc5280-1522-42ac-86e8-d119d6d8ab2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705892872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.705892872
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.4255326860
Short name T1209
Test name
Test status
Simulation time 44357900 ps
CPU time 13.03 seconds
Started Jul 22 06:19:31 PM PDT 24
Finished Jul 22 06:19:45 PM PDT 24
Peak memory 253252 kb
Host smart-94924061-221b-417d-ac0a-953de38da704
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255326860 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.4255326860
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2482322486
Short name T1220
Test name
Test status
Simulation time 53681700 ps
CPU time 18.46 seconds
Started Jul 22 06:19:04 PM PDT 24
Finished Jul 22 06:19:23 PM PDT 24
Peak memory 264068 kb
Host smart-a19a0445-a947-40d6-b3b2-4e428bc14e3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482322486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
2482322486
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1649697238
Short name T370
Test name
Test status
Simulation time 452493100 ps
CPU time 461.18 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:26:50 PM PDT 24
Peak memory 264080 kb
Host smart-f4763ab5-a6eb-4376-af76-046ad845bdc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649697238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.1649697238
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2184286714
Short name T1252
Test name
Test status
Simulation time 253576700 ps
CPU time 18.37 seconds
Started Jul 22 06:20:05 PM PDT 24
Finished Jul 22 06:20:24 PM PDT 24
Peak memory 272276 kb
Host smart-1501cf18-8f55-459d-a64f-23dc7b4546b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184286714 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.2184286714
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1505134165
Short name T1127
Test name
Test status
Simulation time 45264600 ps
CPU time 14.52 seconds
Started Jul 22 06:19:38 PM PDT 24
Finished Jul 22 06:19:53 PM PDT 24
Peak memory 261672 kb
Host smart-2dbe2d11-ba8e-4979-802b-207817b8ed0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505134165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.1505134165
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2478512756
Short name T1189
Test name
Test status
Simulation time 59027000 ps
CPU time 13.33 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:20 PM PDT 24
Peak memory 261476 kb
Host smart-8a290883-726c-4bb9-af81-e08868348fcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478512756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
2478512756
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.4043711267
Short name T1198
Test name
Test status
Simulation time 37292400 ps
CPU time 17.75 seconds
Started Jul 22 06:19:03 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 264044 kb
Host smart-80a80d2f-92b4-40ce-8f3f-5c89998f2df3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043711267 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.4043711267
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3703646720
Short name T1164
Test name
Test status
Simulation time 14654800 ps
CPU time 15.57 seconds
Started Jul 22 06:19:08 PM PDT 24
Finished Jul 22 06:19:25 PM PDT 24
Peak memory 253216 kb
Host smart-90a906f5-423a-4feb-bc38-c1ae64f3ec26
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703646720 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.3703646720
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3399547757
Short name T1110
Test name
Test status
Simulation time 49302000 ps
CPU time 16.19 seconds
Started Jul 22 06:19:04 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 253284 kb
Host smart-6f67629c-2817-405f-9a07-4117d339217a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399547757 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.3399547757
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2159344815
Short name T1204
Test name
Test status
Simulation time 423886700 ps
CPU time 19.91 seconds
Started Jul 22 06:19:04 PM PDT 24
Finished Jul 22 06:19:25 PM PDT 24
Peak memory 272236 kb
Host smart-7b9397dc-8ded-428d-bd10-02a63a0f8411
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159344815 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.2159344815
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1074373243
Short name T302
Test name
Test status
Simulation time 71787200 ps
CPU time 17.45 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:26 PM PDT 24
Peak memory 264088 kb
Host smart-030a822d-1d05-402c-9370-024a9bc626c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074373243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.1074373243
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3881408997
Short name T1139
Test name
Test status
Simulation time 56062900 ps
CPU time 13.36 seconds
Started Jul 22 06:19:23 PM PDT 24
Finished Jul 22 06:19:38 PM PDT 24
Peak memory 261560 kb
Host smart-1e91e0ac-b5d7-405a-a7fe-9aa7168c61f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881408997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
3881408997
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2219024601
Short name T1143
Test name
Test status
Simulation time 55054900 ps
CPU time 15.24 seconds
Started Jul 22 06:19:05 PM PDT 24
Finished Jul 22 06:19:21 PM PDT 24
Peak memory 262664 kb
Host smart-2cfe1054-6a75-4a8e-801c-e784d8e077a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219024601 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.2219024601
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2851963250
Short name T1244
Test name
Test status
Simulation time 19427300 ps
CPU time 12.85 seconds
Started Jul 22 06:20:05 PM PDT 24
Finished Jul 22 06:20:18 PM PDT 24
Peak memory 253292 kb
Host smart-0330c2f9-abf6-4120-9cd1-30179dcf1010
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851963250 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.2851963250
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2781478851
Short name T1229
Test name
Test status
Simulation time 14056000 ps
CPU time 15.89 seconds
Started Jul 22 06:19:03 PM PDT 24
Finished Jul 22 06:19:19 PM PDT 24
Peak memory 253268 kb
Host smart-0d305439-7942-4619-9a1f-828e95be3f78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781478851 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.2781478851
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.464307182
Short name T1215
Test name
Test status
Simulation time 55081400 ps
CPU time 19.45 seconds
Started Jul 22 06:19:08 PM PDT 24
Finished Jul 22 06:19:29 PM PDT 24
Peak memory 264012 kb
Host smart-1f641529-bb93-4192-92d3-0056d453c66c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464307182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.464307182
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1587724379
Short name T243
Test name
Test status
Simulation time 743080800 ps
CPU time 389.92 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:25:38 PM PDT 24
Peak memory 264100 kb
Host smart-2bd21f11-090a-4656-ac12-fdee05e0e48f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587724379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.1587724379
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3692430095
Short name T1239
Test name
Test status
Simulation time 226987700 ps
CPU time 17.99 seconds
Started Jul 22 06:19:04 PM PDT 24
Finished Jul 22 06:19:23 PM PDT 24
Peak memory 271448 kb
Host smart-445cc893-7cf1-406e-b360-2a9b75e90b84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692430095 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.3692430095
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2146435514
Short name T67
Test name
Test status
Simulation time 114843400 ps
CPU time 17.01 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:26 PM PDT 24
Peak memory 264108 kb
Host smart-b972f7fc-08b3-44ff-be76-bea937b17f33
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146435514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.2146435514
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.226841236
Short name T1256
Test name
Test status
Simulation time 107172000 ps
CPU time 13.57 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 261508 kb
Host smart-e1e0159e-b61e-4f94-a5e2-72877f487c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226841236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.226841236
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1909226048
Short name T1171
Test name
Test status
Simulation time 2283190100 ps
CPU time 21.68 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:30 PM PDT 24
Peak memory 262852 kb
Host smart-79ac11c2-ad43-420b-b0ae-8847910d9f58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909226048 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.1909226048
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3442471869
Short name T1116
Test name
Test status
Simulation time 35755500 ps
CPU time 15.68 seconds
Started Jul 22 06:19:05 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 253220 kb
Host smart-0735a9e8-44a1-4b91-a4c0-c0411380d114
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442471869 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.3442471869
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1231883303
Short name T1144
Test name
Test status
Simulation time 11119300 ps
CPU time 13.26 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:21 PM PDT 24
Peak memory 253304 kb
Host smart-7e2cdb75-4510-4db3-953b-b87f7bd0e0c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231883303 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.1231883303
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1678339510
Short name T259
Test name
Test status
Simulation time 54055400 ps
CPU time 18.92 seconds
Started Jul 22 06:19:07 PM PDT 24
Finished Jul 22 06:19:28 PM PDT 24
Peak memory 264248 kb
Host smart-08ab1dae-cbd2-43f7-adb4-fb13b0d93f98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678339510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
1678339510
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2200825547
Short name T270
Test name
Test status
Simulation time 52935100 ps
CPU time 14.85 seconds
Started Jul 22 06:19:08 PM PDT 24
Finished Jul 22 06:19:25 PM PDT 24
Peak memory 264096 kb
Host smart-e8147f6d-2676-4b6b-af79-439b020e9800
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200825547 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.2200825547
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3319228592
Short name T1160
Test name
Test status
Simulation time 67720400 ps
CPU time 16.85 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:25 PM PDT 24
Peak memory 264060 kb
Host smart-e73fd958-f9cd-413a-a45d-12d0e9cf8b4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319228592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.3319228592
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2768041224
Short name T1134
Test name
Test status
Simulation time 64627900 ps
CPU time 13.04 seconds
Started Jul 22 06:20:05 PM PDT 24
Finished Jul 22 06:20:19 PM PDT 24
Peak memory 261428 kb
Host smart-e8fb246e-36cb-4600-abe8-7aee280eafc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768041224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
2768041224
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3024577095
Short name T1221
Test name
Test status
Simulation time 190883700 ps
CPU time 21.02 seconds
Started Jul 22 06:19:05 PM PDT 24
Finished Jul 22 06:19:28 PM PDT 24
Peak memory 264020 kb
Host smart-a11eaf75-04bc-4a0b-a1da-9088af54ff52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024577095 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.3024577095
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4123590622
Short name T1118
Test name
Test status
Simulation time 14332300 ps
CPU time 15.67 seconds
Started Jul 22 06:19:04 PM PDT 24
Finished Jul 22 06:19:21 PM PDT 24
Peak memory 253316 kb
Host smart-6d8a1937-2bd2-471e-98c1-ed1814aa8366
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123590622 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.4123590622
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.11213530
Short name T1255
Test name
Test status
Simulation time 37407600 ps
CPU time 15.65 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:24 PM PDT 24
Peak memory 253420 kb
Host smart-612881b3-8dd3-48e4-aa75-f260c33b6c4f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11213530 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.11213530
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2146678117
Short name T273
Test name
Test status
Simulation time 33567600 ps
CPU time 16.2 seconds
Started Jul 22 06:19:07 PM PDT 24
Finished Jul 22 06:19:25 PM PDT 24
Peak memory 264116 kb
Host smart-67f2dc94-4721-4bcc-976c-94f72618b98e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146678117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
2146678117
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1209830601
Short name T274
Test name
Test status
Simulation time 426577800 ps
CPU time 391.8 seconds
Started Jul 22 06:19:09 PM PDT 24
Finished Jul 22 06:25:42 PM PDT 24
Peak memory 264104 kb
Host smart-33ac2be4-9bfa-4208-b24f-ce62756323c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209830601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.1209830601
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3737821089
Short name T104
Test name
Test status
Simulation time 396252000 ps
CPU time 14.91 seconds
Started Jul 22 06:19:08 PM PDT 24
Finished Jul 22 06:19:24 PM PDT 24
Peak memory 272284 kb
Host smart-704dd777-e90e-46e1-9a21-2145e133d1e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737821089 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.3737821089
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.929980845
Short name T1190
Test name
Test status
Simulation time 399704500 ps
CPU time 15.11 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:23 PM PDT 24
Peak memory 261696 kb
Host smart-0aa1bba3-a5d4-4d1f-960e-eb515383ba00
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929980845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.flash_ctrl_csr_rw.929980845
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2533262186
Short name T1170
Test name
Test status
Simulation time 31207100 ps
CPU time 13.76 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 261436 kb
Host smart-5eed6ac4-ca24-4c45-ab24-c19a2935671c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533262186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
2533262186
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.4027112685
Short name T301
Test name
Test status
Simulation time 889281800 ps
CPU time 36.54 seconds
Started Jul 22 06:19:38 PM PDT 24
Finished Jul 22 06:20:15 PM PDT 24
Peak memory 263948 kb
Host smart-a1d298b6-373e-434c-bbc9-2575b850026d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027112685 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.4027112685
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1657881817
Short name T1202
Test name
Test status
Simulation time 32938600 ps
CPU time 15.75 seconds
Started Jul 22 06:19:07 PM PDT 24
Finished Jul 22 06:19:25 PM PDT 24
Peak memory 253444 kb
Host smart-35152720-48cd-4435-b58f-efb28f4f2c3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657881817 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.1657881817
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1757302516
Short name T1253
Test name
Test status
Simulation time 13507400 ps
CPU time 15.94 seconds
Started Jul 22 06:19:05 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 253292 kb
Host smart-cad321b2-a6a2-486e-bb0e-9598e436bb7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757302516 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.1757302516
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1817619230
Short name T1216
Test name
Test status
Simulation time 175216200 ps
CPU time 18.02 seconds
Started Jul 22 06:19:04 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 263556 kb
Host smart-19ca2bf2-48f4-4c5a-9897-e7ab62d82a55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817619230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
1817619230
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.290355257
Short name T1242
Test name
Test status
Simulation time 668577200 ps
CPU time 763.96 seconds
Started Jul 22 06:19:09 PM PDT 24
Finished Jul 22 06:31:54 PM PDT 24
Peak memory 264096 kb
Host smart-d324a579-8242-4d2d-a382-c4750e82c279
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290355257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl
_tl_intg_err.290355257
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3232620116
Short name T1230
Test name
Test status
Simulation time 102311700 ps
CPU time 18.94 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:26 PM PDT 24
Peak memory 272228 kb
Host smart-4b5802fb-42bb-421d-a928-026dcd4a30e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232620116 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.3232620116
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3356993019
Short name T1173
Test name
Test status
Simulation time 44622900 ps
CPU time 14.57 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 264100 kb
Host smart-c910a2ce-995e-4a90-bb3a-db52d2d738ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356993019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.3356993019
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.314881900
Short name T1133
Test name
Test status
Simulation time 50283600 ps
CPU time 13.54 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:21 PM PDT 24
Peak memory 261472 kb
Host smart-2f36b380-1176-404b-bf08-433b3ef72036
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314881900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.314881900
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2425416320
Short name T1248
Test name
Test status
Simulation time 284079900 ps
CPU time 18.26 seconds
Started Jul 22 06:20:04 PM PDT 24
Finished Jul 22 06:20:23 PM PDT 24
Peak memory 261556 kb
Host smart-41d7d94c-ca4b-487c-a242-6bab7d1c3223
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425416320 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.2425416320
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2642340852
Short name T1111
Test name
Test status
Simulation time 35204100 ps
CPU time 15.47 seconds
Started Jul 22 06:19:05 PM PDT 24
Finished Jul 22 06:19:21 PM PDT 24
Peak memory 253124 kb
Host smart-aa78d83d-91b5-4fdd-9822-44df9d0e6e10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642340852 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.2642340852
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.4032082621
Short name T1203
Test name
Test status
Simulation time 44726300 ps
CPU time 12.84 seconds
Started Jul 22 06:20:05 PM PDT 24
Finished Jul 22 06:20:19 PM PDT 24
Peak memory 253336 kb
Host smart-9de8ba89-7a0f-49ae-b3d4-80049796c4fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032082621 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.4032082621
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.933727408
Short name T1211
Test name
Test status
Simulation time 200372500 ps
CPU time 18.83 seconds
Started Jul 22 06:19:09 PM PDT 24
Finished Jul 22 06:19:29 PM PDT 24
Peak memory 264100 kb
Host smart-08cf3d0b-6c1c-4b31-8535-e13c534779a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933727408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.933727408
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2517187313
Short name T373
Test name
Test status
Simulation time 10426220900 ps
CPU time 779.54 seconds
Started Jul 22 06:19:07 PM PDT 24
Finished Jul 22 06:32:09 PM PDT 24
Peak memory 264232 kb
Host smart-52928e74-0f4b-4b3b-8156-7dd65c8e9cf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517187313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.2517187313
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1617987927
Short name T1157
Test name
Test status
Simulation time 5469934600 ps
CPU time 57.72 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:19:48 PM PDT 24
Peak memory 261556 kb
Host smart-8e538ae1-6025-42c3-ac91-54e7f840088e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617987927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.1617987927
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.4075925215
Short name T1217
Test name
Test status
Simulation time 4902657200 ps
CPU time 46.67 seconds
Started Jul 22 06:18:47 PM PDT 24
Finished Jul 22 06:19:34 PM PDT 24
Peak memory 261604 kb
Host smart-d93aa6b0-d91a-40bd-a6ab-0d245ba84b40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075925215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.4075925215
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.850318673
Short name T1199
Test name
Test status
Simulation time 107829200 ps
CPU time 26.2 seconds
Started Jul 22 06:18:47 PM PDT 24
Finished Jul 22 06:19:14 PM PDT 24
Peak memory 263880 kb
Host smart-826d25e1-90d9-43f3-bcf8-eee97595b5db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850318673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_hw_reset.850318673
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4224154856
Short name T240
Test name
Test status
Simulation time 49802700 ps
CPU time 18.05 seconds
Started Jul 22 06:19:32 PM PDT 24
Finished Jul 22 06:19:51 PM PDT 24
Peak memory 278304 kb
Host smart-e6532970-85de-4d89-9bad-f3a4fe915c02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224154856 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.4224154856
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.4028606945
Short name T1180
Test name
Test status
Simulation time 28110800 ps
CPU time 14.77 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:19:05 PM PDT 24
Peak memory 264104 kb
Host smart-0092d9ef-bc2b-4ef7-a443-1a5e2ef7a8a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028606945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.4028606945
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1956310662
Short name T1184
Test name
Test status
Simulation time 79911700 ps
CPU time 13.65 seconds
Started Jul 22 06:18:46 PM PDT 24
Finished Jul 22 06:19:01 PM PDT 24
Peak memory 261376 kb
Host smart-80402de8-e271-4b04-97fb-7b875f71169e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956310662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.1
956310662
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1921658566
Short name T246
Test name
Test status
Simulation time 32843600 ps
CPU time 13.77 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:19:04 PM PDT 24
Peak memory 262396 kb
Host smart-754ac22f-25da-4d35-b581-da985decdfe1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921658566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.1921658566
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1299132403
Short name T1233
Test name
Test status
Simulation time 25230500 ps
CPU time 13.51 seconds
Started Jul 22 06:18:45 PM PDT 24
Finished Jul 22 06:18:59 PM PDT 24
Peak memory 261556 kb
Host smart-50e1a1d8-24e8-42c9-a790-3c66b343ef23
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299132403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.1299132403
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1628177186
Short name T1166
Test name
Test status
Simulation time 590054100 ps
CPU time 29.8 seconds
Started Jul 22 06:18:46 PM PDT 24
Finished Jul 22 06:19:17 PM PDT 24
Peak memory 262976 kb
Host smart-ecf3b17b-59c7-4e1e-b9f7-dc3f3ceba371
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628177186 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.1628177186
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.169272129
Short name T1178
Test name
Test status
Simulation time 18873700 ps
CPU time 16.22 seconds
Started Jul 22 06:18:50 PM PDT 24
Finished Jul 22 06:19:07 PM PDT 24
Peak memory 253240 kb
Host smart-8230c99a-f2df-4ec4-b48d-ac694f9e7ac2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169272129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.169272129
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1057948458
Short name T1112
Test name
Test status
Simulation time 35934500 ps
CPU time 13.31 seconds
Started Jul 22 06:18:50 PM PDT 24
Finished Jul 22 06:19:04 PM PDT 24
Peak memory 253244 kb
Host smart-0826ff51-5270-4a94-b412-8be6bf1acd8b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057948458 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.1057948458
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3041576266
Short name T267
Test name
Test status
Simulation time 66870600 ps
CPU time 20.82 seconds
Started Jul 22 06:18:47 PM PDT 24
Finished Jul 22 06:19:08 PM PDT 24
Peak memory 264144 kb
Host smart-4eac7b4b-3d1b-42a4-bde3-1761174cf965
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041576266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.3
041576266
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1297714623
Short name T369
Test name
Test status
Simulation time 2713426100 ps
CPU time 912 seconds
Started Jul 22 06:18:56 PM PDT 24
Finished Jul 22 06:34:09 PM PDT 24
Peak memory 264052 kb
Host smart-33083c35-7d49-4083-88e2-174be27630bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297714623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.1297714623
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.4126411834
Short name T1232
Test name
Test status
Simulation time 24562400 ps
CPU time 13.49 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:21 PM PDT 24
Peak memory 261572 kb
Host smart-8f700e97-f330-48fd-8f79-f61082e0246d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126411834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
4126411834
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3717255243
Short name T1129
Test name
Test status
Simulation time 26520800 ps
CPU time 13.43 seconds
Started Jul 22 06:19:08 PM PDT 24
Finished Jul 22 06:19:23 PM PDT 24
Peak memory 261468 kb
Host smart-2d39f388-5dc9-4e89-85b4-d6665d1686f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717255243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
3717255243
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2832407686
Short name T1175
Test name
Test status
Simulation time 26201800 ps
CPU time 14.02 seconds
Started Jul 22 06:19:08 PM PDT 24
Finished Jul 22 06:19:24 PM PDT 24
Peak memory 261400 kb
Host smart-bff5fcb9-7a14-48e2-9f6c-138a9817ef24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832407686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
2832407686
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1385658127
Short name T261
Test name
Test status
Simulation time 66574300 ps
CPU time 13.32 seconds
Started Jul 22 06:19:04 PM PDT 24
Finished Jul 22 06:19:18 PM PDT 24
Peak memory 261656 kb
Host smart-c11575f2-05ba-44c7-ac7e-c4b570c17348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385658127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
1385658127
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3687991018
Short name T1228
Test name
Test status
Simulation time 45922200 ps
CPU time 13.58 seconds
Started Jul 22 06:19:07 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 261376 kb
Host smart-cbb96557-8eaf-40b6-909a-4763a22140da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687991018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
3687991018
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2564702266
Short name T1172
Test name
Test status
Simulation time 46673500 ps
CPU time 13.47 seconds
Started Jul 22 06:20:05 PM PDT 24
Finished Jul 22 06:20:19 PM PDT 24
Peak memory 261428 kb
Host smart-ec0c0673-5a81-4023-ba1b-6ec37b6435db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564702266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
2564702266
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2735247108
Short name T1219
Test name
Test status
Simulation time 24517300 ps
CPU time 13.6 seconds
Started Jul 22 06:19:05 PM PDT 24
Finished Jul 22 06:19:19 PM PDT 24
Peak memory 261372 kb
Host smart-12a2990a-6573-4842-b735-36ee8ad3eaae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735247108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
2735247108
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1254410409
Short name T1130
Test name
Test status
Simulation time 38878300 ps
CPU time 13.47 seconds
Started Jul 22 06:20:06 PM PDT 24
Finished Jul 22 06:20:21 PM PDT 24
Peak memory 261428 kb
Host smart-fd52084e-917e-4111-8918-f6acab4c0041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254410409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
1254410409
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3505993110
Short name T263
Test name
Test status
Simulation time 15321300 ps
CPU time 13.26 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:21 PM PDT 24
Peak memory 261476 kb
Host smart-b70e84f7-1f90-4f2b-9846-60eb40b5c932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505993110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
3505993110
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.557244708
Short name T307
Test name
Test status
Simulation time 789900500 ps
CPU time 40.33 seconds
Started Jul 22 06:18:48 PM PDT 24
Finished Jul 22 06:19:29 PM PDT 24
Peak memory 261536 kb
Host smart-f9cc3c1d-8be4-4c4d-bdcf-f1f94bf66f2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557244708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_aliasing.557244708
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1636787930
Short name T1174
Test name
Test status
Simulation time 3790273100 ps
CPU time 47.71 seconds
Started Jul 22 06:18:47 PM PDT 24
Finished Jul 22 06:19:35 PM PDT 24
Peak memory 261692 kb
Host smart-ec654ca8-924c-49bf-ac54-80079bbb8d4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636787930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_bit_bash.1636787930
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1822279348
Short name T1250
Test name
Test status
Simulation time 75335900 ps
CPU time 45.74 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:19:35 PM PDT 24
Peak memory 261548 kb
Host smart-f46f87f0-b753-4a28-8048-5e0145063f04
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822279348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.1822279348
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.118233020
Short name T1155
Test name
Test status
Simulation time 142487300 ps
CPU time 17.96 seconds
Started Jul 22 06:18:46 PM PDT 24
Finished Jul 22 06:19:04 PM PDT 24
Peak memory 271724 kb
Host smart-ca4e939f-016b-4c9d-93ca-5cccce855891
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118233020 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.118233020
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3614945912
Short name T1247
Test name
Test status
Simulation time 98614700 ps
CPU time 17.3 seconds
Started Jul 22 06:18:55 PM PDT 24
Finished Jul 22 06:19:13 PM PDT 24
Peak memory 264072 kb
Host smart-c62127cf-5424-4d7c-8b82-c415809471aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614945912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.3614945912
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2359461111
Short name T1149
Test name
Test status
Simulation time 14633100 ps
CPU time 14.4 seconds
Started Jul 22 06:18:48 PM PDT 24
Finished Jul 22 06:19:03 PM PDT 24
Peak memory 261316 kb
Host smart-a4df2d1d-11da-4120-97ba-313a0243118d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359461111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.2
359461111
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2130118634
Short name T1226
Test name
Test status
Simulation time 14291200 ps
CPU time 13.22 seconds
Started Jul 22 06:18:47 PM PDT 24
Finished Jul 22 06:19:01 PM PDT 24
Peak memory 261448 kb
Host smart-a8a9881f-db94-4cce-af3d-c521bfceddfb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130118634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.2130118634
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1302894481
Short name T1141
Test name
Test status
Simulation time 86757600 ps
CPU time 17.62 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:19:07 PM PDT 24
Peak memory 262976 kb
Host smart-2908a62c-575f-4bdb-929c-d750f5ccd59d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302894481 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.1302894481
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3875755326
Short name T1115
Test name
Test status
Simulation time 11931600 ps
CPU time 16.13 seconds
Started Jul 22 06:18:46 PM PDT 24
Finished Jul 22 06:19:03 PM PDT 24
Peak memory 253236 kb
Host smart-e530ec50-ba89-4ae8-8f73-092e23b633ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875755326 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.3875755326
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2735949062
Short name T1113
Test name
Test status
Simulation time 26615600 ps
CPU time 15.8 seconds
Started Jul 22 06:18:56 PM PDT 24
Finished Jul 22 06:19:12 PM PDT 24
Peak memory 253140 kb
Host smart-cabb84ce-cb31-4933-8cba-0cdef124eb88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735949062 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.2735949062
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2600526681
Short name T227
Test name
Test status
Simulation time 782778400 ps
CPU time 19.45 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:19:09 PM PDT 24
Peak memory 264036 kb
Host smart-965fc63d-eea9-47ad-8505-2b45c21baa64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600526681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.2
600526681
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.32161651
Short name T1147
Test name
Test status
Simulation time 38521100 ps
CPU time 13.22 seconds
Started Jul 22 06:20:05 PM PDT 24
Finished Jul 22 06:20:19 PM PDT 24
Peak memory 261488 kb
Host smart-7d6c3651-d5d8-4b70-816b-6ae73d0d147e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32161651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.32161651
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.4262683194
Short name T1167
Test name
Test status
Simulation time 33275300 ps
CPU time 13.28 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:21 PM PDT 24
Peak memory 261544 kb
Host smart-45317b4e-fd11-45c0-8da8-62108838dd18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262683194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
4262683194
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2559253153
Short name T1210
Test name
Test status
Simulation time 16795300 ps
CPU time 13.27 seconds
Started Jul 22 06:19:07 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 261520 kb
Host smart-1384f984-a92e-45ca-ba74-de7e4fcfbfc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559253153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
2559253153
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3057527229
Short name T1186
Test name
Test status
Simulation time 31108900 ps
CPU time 13.52 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:20 PM PDT 24
Peak memory 261488 kb
Host smart-5c766e79-c009-4df5-b65c-47d2c7513c74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057527229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
3057527229
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1355683114
Short name T1131
Test name
Test status
Simulation time 15883300 ps
CPU time 14.2 seconds
Started Jul 22 06:19:12 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 261404 kb
Host smart-5cdb3007-99a4-485b-92b0-163732b9a8ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355683114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
1355683114
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3833008180
Short name T1249
Test name
Test status
Simulation time 61344700 ps
CPU time 13.45 seconds
Started Jul 22 06:19:13 PM PDT 24
Finished Jul 22 06:19:28 PM PDT 24
Peak memory 261492 kb
Host smart-f607eae4-c479-4f77-8104-32e1dbe99864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833008180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
3833008180
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1896153948
Short name T1150
Test name
Test status
Simulation time 32149700 ps
CPU time 13.31 seconds
Started Jul 22 06:19:14 PM PDT 24
Finished Jul 22 06:19:28 PM PDT 24
Peak memory 261568 kb
Host smart-3f2a8c67-4547-4c4f-a1b0-6e0e1b36f0bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896153948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
1896153948
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1069887554
Short name T1152
Test name
Test status
Simulation time 25460300 ps
CPU time 13.33 seconds
Started Jul 22 06:19:14 PM PDT 24
Finished Jul 22 06:19:28 PM PDT 24
Peak memory 261484 kb
Host smart-c3a091d0-6b88-4ef3-9a5f-336d6268a53b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069887554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
1069887554
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.790711686
Short name T330
Test name
Test status
Simulation time 162355600 ps
CPU time 13.49 seconds
Started Jul 22 06:19:14 PM PDT 24
Finished Jul 22 06:19:29 PM PDT 24
Peak memory 261560 kb
Host smart-66994ef4-fc86-4ec4-9be7-663f98ac6c63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790711686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.790711686
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3186196603
Short name T256
Test name
Test status
Simulation time 438745200 ps
CPU time 50.33 seconds
Started Jul 22 06:18:47 PM PDT 24
Finished Jul 22 06:19:38 PM PDT 24
Peak memory 261380 kb
Host smart-ee63f093-95dc-4d6a-be77-b23bb92146d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186196603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.3186196603
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.510775886
Short name T1208
Test name
Test status
Simulation time 2744359900 ps
CPU time 67.35 seconds
Started Jul 22 06:19:32 PM PDT 24
Finished Jul 22 06:20:40 PM PDT 24
Peak memory 261252 kb
Host smart-6ec9390a-e04a-48ec-8d7f-07d4823bb384
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510775886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_bit_bash.510775886
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.552452753
Short name T1168
Test name
Test status
Simulation time 80787000 ps
CPU time 31.06 seconds
Started Jul 22 06:18:56 PM PDT 24
Finished Jul 22 06:19:28 PM PDT 24
Peak memory 261668 kb
Host smart-9ed31110-d6a5-4341-954b-8ffa37fa422f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552452753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_hw_reset.552452753
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3763323428
Short name T1128
Test name
Test status
Simulation time 44492200 ps
CPU time 14.69 seconds
Started Jul 22 06:19:05 PM PDT 24
Finished Jul 22 06:19:21 PM PDT 24
Peak memory 264056 kb
Host smart-d078ba61-1ffe-4f0e-bb06-4eb88caafa03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763323428 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.3763323428
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2192720920
Short name T1176
Test name
Test status
Simulation time 117299900 ps
CPU time 13.85 seconds
Started Jul 22 06:19:07 PM PDT 24
Finished Jul 22 06:19:23 PM PDT 24
Peak memory 264024 kb
Host smart-cf8fe24a-897d-4976-808f-b2c7da753aca
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192720920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.2192720920
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2445336312
Short name T1245
Test name
Test status
Simulation time 34665800 ps
CPU time 14.15 seconds
Started Jul 22 06:18:50 PM PDT 24
Finished Jul 22 06:19:05 PM PDT 24
Peak memory 261488 kb
Host smart-1fa2fbd2-a467-4fa6-957d-fdafd2cbe25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445336312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2
445336312
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1481548329
Short name T247
Test name
Test status
Simulation time 35227400 ps
CPU time 13.36 seconds
Started Jul 22 06:19:00 PM PDT 24
Finished Jul 22 06:19:13 PM PDT 24
Peak memory 262228 kb
Host smart-b10f53bd-8346-40ab-88aa-3d65d308e560
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481548329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_mem_partial_access.1481548329
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1755474021
Short name T1126
Test name
Test status
Simulation time 44023300 ps
CPU time 13.56 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:19:04 PM PDT 24
Peak memory 261408 kb
Host smart-33871d1e-7355-4374-80d3-c87a6df1f8ea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755474021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.1755474021
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3558684875
Short name T1153
Test name
Test status
Simulation time 167228000 ps
CPU time 36.22 seconds
Started Jul 22 06:18:50 PM PDT 24
Finished Jul 22 06:19:28 PM PDT 24
Peak memory 262696 kb
Host smart-f622072d-cb9f-478b-9653-e86ada4245ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558684875 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.3558684875
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.4237747180
Short name T1185
Test name
Test status
Simulation time 31510900 ps
CPU time 13.61 seconds
Started Jul 22 06:18:48 PM PDT 24
Finished Jul 22 06:19:02 PM PDT 24
Peak memory 253152 kb
Host smart-c3bc6547-ff66-49a8-91f7-5542ba4d7193
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237747180 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.4237747180
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3758753184
Short name T1237
Test name
Test status
Simulation time 35113300 ps
CPU time 15.63 seconds
Started Jul 22 06:18:47 PM PDT 24
Finished Jul 22 06:19:03 PM PDT 24
Peak memory 253316 kb
Host smart-8334705e-d996-48a3-bba8-e097d88cd021
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758753184 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.3758753184
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1363772723
Short name T1214
Test name
Test status
Simulation time 124799100 ps
CPU time 20.19 seconds
Started Jul 22 06:18:51 PM PDT 24
Finished Jul 22 06:19:12 PM PDT 24
Peak memory 264160 kb
Host smart-a469d4ea-f875-4746-b190-da4789cdba48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363772723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.1
363772723
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1791489499
Short name T1206
Test name
Test status
Simulation time 18103300 ps
CPU time 13.4 seconds
Started Jul 22 06:19:14 PM PDT 24
Finished Jul 22 06:19:28 PM PDT 24
Peak memory 261428 kb
Host smart-e42ccfb1-b4a6-4050-9d64-9b650ab8cc4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791489499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
1791489499
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.4126064518
Short name T1159
Test name
Test status
Simulation time 20193100 ps
CPU time 13.48 seconds
Started Jul 22 06:19:12 PM PDT 24
Finished Jul 22 06:19:26 PM PDT 24
Peak memory 261604 kb
Host smart-d3b574d5-9b73-4579-8b73-c675d51e4fb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126064518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
4126064518
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1097997359
Short name T1145
Test name
Test status
Simulation time 185187600 ps
CPU time 13.77 seconds
Started Jul 22 06:19:13 PM PDT 24
Finished Jul 22 06:19:28 PM PDT 24
Peak memory 261496 kb
Host smart-abe8497a-1c48-446d-9a7b-88db08dfc7d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097997359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
1097997359
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3876543043
Short name T1205
Test name
Test status
Simulation time 48255100 ps
CPU time 13.62 seconds
Started Jul 22 06:19:13 PM PDT 24
Finished Jul 22 06:19:28 PM PDT 24
Peak memory 261580 kb
Host smart-3a753990-e948-4e7c-bd97-82abcf801e99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876543043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
3876543043
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.4190705326
Short name T1188
Test name
Test status
Simulation time 25475000 ps
CPU time 14.07 seconds
Started Jul 22 06:19:15 PM PDT 24
Finished Jul 22 06:19:30 PM PDT 24
Peak memory 261432 kb
Host smart-4a82ece5-aebc-4d8b-8527-b13f1c2eb3e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190705326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
4190705326
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3315878332
Short name T1163
Test name
Test status
Simulation time 43568400 ps
CPU time 14.04 seconds
Started Jul 22 06:19:12 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 261496 kb
Host smart-e523818a-a99a-4c8d-ad16-e460e54a8c3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315878332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
3315878332
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2859119862
Short name T1138
Test name
Test status
Simulation time 65226600 ps
CPU time 13.45 seconds
Started Jul 22 06:19:27 PM PDT 24
Finished Jul 22 06:19:42 PM PDT 24
Peak memory 261504 kb
Host smart-5251cb2a-5938-472c-afb7-967fb71907ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859119862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
2859119862
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2583385004
Short name T1158
Test name
Test status
Simulation time 38102700 ps
CPU time 14.16 seconds
Started Jul 22 06:19:27 PM PDT 24
Finished Jul 22 06:19:42 PM PDT 24
Peak memory 261312 kb
Host smart-80c666ca-b3ae-45ad-a269-593273fb1f20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583385004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
2583385004
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.4286660868
Short name T1258
Test name
Test status
Simulation time 23527500 ps
CPU time 13.93 seconds
Started Jul 22 06:19:13 PM PDT 24
Finished Jul 22 06:19:29 PM PDT 24
Peak memory 261400 kb
Host smart-4333f9c8-58fd-4f69-ae7c-48aede8e1b51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286660868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
4286660868
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.597135585
Short name T1201
Test name
Test status
Simulation time 173939800 ps
CPU time 13.62 seconds
Started Jul 22 06:19:22 PM PDT 24
Finished Jul 22 06:19:38 PM PDT 24
Peak memory 261440 kb
Host smart-46e0b7b3-cb61-44d4-95ea-46ea97eb1f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597135585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.597135585
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.631506530
Short name T1259
Test name
Test status
Simulation time 51927200 ps
CPU time 17.06 seconds
Started Jul 22 06:19:07 PM PDT 24
Finished Jul 22 06:19:26 PM PDT 24
Peak memory 264272 kb
Host smart-90c4c224-8b34-42e7-9c15-3a990323d387
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631506530 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.631506530
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2481347033
Short name T1137
Test name
Test status
Simulation time 742384900 ps
CPU time 18.28 seconds
Started Jul 22 06:18:48 PM PDT 24
Finished Jul 22 06:19:06 PM PDT 24
Peak memory 261616 kb
Host smart-f003d5c2-8456-4619-b82b-09f957a9b5f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481347033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.2481347033
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.829074598
Short name T1156
Test name
Test status
Simulation time 50582400 ps
CPU time 13.64 seconds
Started Jul 22 06:18:48 PM PDT 24
Finished Jul 22 06:19:02 PM PDT 24
Peak memory 261508 kb
Host smart-40b83828-cd92-4aa1-95e4-0945ffa11e91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829074598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.829074598
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1300104017
Short name T310
Test name
Test status
Simulation time 455072600 ps
CPU time 21.85 seconds
Started Jul 22 06:18:48 PM PDT 24
Finished Jul 22 06:19:11 PM PDT 24
Peak memory 264060 kb
Host smart-1b532097-3192-4587-9a43-3c9803377512
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300104017 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.1300104017
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1022617379
Short name T1218
Test name
Test status
Simulation time 11732400 ps
CPU time 13.31 seconds
Started Jul 22 06:19:04 PM PDT 24
Finished Jul 22 06:19:18 PM PDT 24
Peak memory 253232 kb
Host smart-0fd13250-d114-48db-8b94-56c4e264ee60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022617379 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.1022617379
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3791522289
Short name T1135
Test name
Test status
Simulation time 75105100 ps
CPU time 13.28 seconds
Started Jul 22 06:19:05 PM PDT 24
Finished Jul 22 06:19:19 PM PDT 24
Peak memory 253052 kb
Host smart-4e0ad668-20b3-4ae7-b0d6-81d377fc46bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791522289 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.3791522289
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2591645553
Short name T268
Test name
Test status
Simulation time 73181900 ps
CPU time 19.6 seconds
Started Jul 22 06:18:50 PM PDT 24
Finished Jul 22 06:19:11 PM PDT 24
Peak memory 264012 kb
Host smart-0d35223a-383e-4460-812c-dc013bd90b72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591645553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.2
591645553
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2884383954
Short name T1122
Test name
Test status
Simulation time 277685500 ps
CPU time 17.69 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:19:08 PM PDT 24
Peak memory 263920 kb
Host smart-64fd7bec-3655-4413-8194-2d36ab529ecb
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884383954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.2884383954
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3340879750
Short name T333
Test name
Test status
Simulation time 36827000 ps
CPU time 13.48 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:19:04 PM PDT 24
Peak memory 261348 kb
Host smart-3be5d2fe-d1d9-4bce-9116-dc460d3c3e21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340879750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.3
340879750
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1536550885
Short name T1200
Test name
Test status
Simulation time 159208500 ps
CPU time 17.56 seconds
Started Jul 22 06:18:52 PM PDT 24
Finished Jul 22 06:19:10 PM PDT 24
Peak memory 261680 kb
Host smart-5f29a5d7-dab0-4c09-82e2-e1c77275c5a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536550885 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.1536550885
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.56869892
Short name T1187
Test name
Test status
Simulation time 19077500 ps
CPU time 13 seconds
Started Jul 22 06:18:47 PM PDT 24
Finished Jul 22 06:19:01 PM PDT 24
Peak memory 253204 kb
Host smart-a35e7307-d6d9-46ff-b40f-b6efa099ca94
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56869892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.56869892
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1739203132
Short name T1225
Test name
Test status
Simulation time 38414700 ps
CPU time 16.37 seconds
Started Jul 22 06:18:51 PM PDT 24
Finished Jul 22 06:19:08 PM PDT 24
Peak memory 253292 kb
Host smart-4c297222-a48f-4002-a82c-2f22e36db818
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739203132 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.1739203132
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1023240998
Short name T271
Test name
Test status
Simulation time 36871700 ps
CPU time 16.37 seconds
Started Jul 22 06:18:48 PM PDT 24
Finished Jul 22 06:19:06 PM PDT 24
Peak memory 263476 kb
Host smart-95f6709a-6792-4050-b91a-bfd873f53960
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023240998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.1
023240998
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2580193330
Short name T1146
Test name
Test status
Simulation time 1705554300 ps
CPU time 460.39 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:26:30 PM PDT 24
Peak memory 264028 kb
Host smart-7fbd42b1-0e1e-43d0-9e0c-df0fac734bf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580193330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.2580193330
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.203367849
Short name T1183
Test name
Test status
Simulation time 37472700 ps
CPU time 18.85 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:19:09 PM PDT 24
Peak memory 272248 kb
Host smart-c8d70f9c-400b-4878-a64a-91149e572d08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203367849 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.203367849
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.566131506
Short name T1121
Test name
Test status
Simulation time 103400800 ps
CPU time 16.8 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:19:06 PM PDT 24
Peak memory 264072 kb
Host smart-d1f8231d-e71e-45ac-a1d5-37e6154559fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566131506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_csr_rw.566131506
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2219972575
Short name T1151
Test name
Test status
Simulation time 57360400 ps
CPU time 13.59 seconds
Started Jul 22 06:19:24 PM PDT 24
Finished Jul 22 06:19:40 PM PDT 24
Peak memory 261288 kb
Host smart-71e3909c-a48a-40a7-8b13-7d4bf1dbb0e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219972575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.2
219972575
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3422359514
Short name T1181
Test name
Test status
Simulation time 141432300 ps
CPU time 17.79 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:19:08 PM PDT 24
Peak memory 262824 kb
Host smart-791d008b-7e74-41d2-bee2-1a34896b3138
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422359514 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.3422359514
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2628005124
Short name T1177
Test name
Test status
Simulation time 31053600 ps
CPU time 15.92 seconds
Started Jul 22 06:18:51 PM PDT 24
Finished Jul 22 06:19:08 PM PDT 24
Peak memory 252420 kb
Host smart-25887a5b-7889-43f8-8df1-1c1129a4ab2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628005124 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2628005124
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1478324749
Short name T1257
Test name
Test status
Simulation time 12514200 ps
CPU time 13.49 seconds
Started Jul 22 06:18:50 PM PDT 24
Finished Jul 22 06:19:05 PM PDT 24
Peak memory 253204 kb
Host smart-0beb0b8c-53d6-44f7-832a-04c462fcc8cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478324749 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.1478324749
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1768728708
Short name T226
Test name
Test status
Simulation time 424398700 ps
CPU time 394.2 seconds
Started Jul 22 06:19:24 PM PDT 24
Finished Jul 22 06:26:01 PM PDT 24
Peak memory 272020 kb
Host smart-2444fe1f-5a67-43b9-800c-ca5e11597cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768728708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.1768728708
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1600292110
Short name T1213
Test name
Test status
Simulation time 142901000 ps
CPU time 17.67 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:19:08 PM PDT 24
Peak memory 272260 kb
Host smart-d4762194-b6d0-4500-93ce-e5a4c6f20100
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600292110 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.1600292110
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.575279727
Short name T1243
Test name
Test status
Simulation time 21619000 ps
CPU time 16.67 seconds
Started Jul 22 06:18:55 PM PDT 24
Finished Jul 22 06:19:12 PM PDT 24
Peak memory 261660 kb
Host smart-c70f2780-d350-480b-aa8d-254d7057136e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575279727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_csr_rw.575279727
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2195286841
Short name T1238
Test name
Test status
Simulation time 47087800 ps
CPU time 13.37 seconds
Started Jul 22 06:19:32 PM PDT 24
Finished Jul 22 06:19:46 PM PDT 24
Peak memory 261472 kb
Host smart-cd06dc48-95f7-4f0a-8d92-61aac30b4297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195286841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.2
195286841
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.907098438
Short name T258
Test name
Test status
Simulation time 905455700 ps
CPU time 21.76 seconds
Started Jul 22 06:18:55 PM PDT 24
Finished Jul 22 06:19:18 PM PDT 24
Peak memory 262816 kb
Host smart-4147a1ac-3da5-42cd-9245-e202010e9e54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907098438 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.907098438
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2036131709
Short name T1119
Test name
Test status
Simulation time 39857100 ps
CPU time 15.71 seconds
Started Jul 22 06:19:32 PM PDT 24
Finished Jul 22 06:19:48 PM PDT 24
Peak memory 252948 kb
Host smart-6c4ec37e-cc9b-4997-a98f-4b4ad49bc907
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036131709 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.2036131709
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2590236520
Short name T1169
Test name
Test status
Simulation time 17326300 ps
CPU time 13.34 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:19:04 PM PDT 24
Peak memory 253360 kb
Host smart-6471b32e-f336-4ed2-bfac-cac37c44a108
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590236520 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.2590236520
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.204943556
Short name T265
Test name
Test status
Simulation time 74498100 ps
CPU time 16.85 seconds
Started Jul 22 06:18:46 PM PDT 24
Finished Jul 22 06:19:03 PM PDT 24
Peak memory 264120 kb
Host smart-034b955d-677b-4bd5-b951-a24d5cca477e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204943556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.204943556
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.4044067919
Short name T372
Test name
Test status
Simulation time 1278659400 ps
CPU time 763.67 seconds
Started Jul 22 06:18:49 PM PDT 24
Finished Jul 22 06:31:34 PM PDT 24
Peak memory 264036 kb
Host smart-9e9b39f3-c17f-418c-ad4c-2623d03086f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044067919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.4044067919
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.188335774
Short name T103
Test name
Test status
Simulation time 189549700 ps
CPU time 19.58 seconds
Started Jul 22 06:18:56 PM PDT 24
Finished Jul 22 06:19:17 PM PDT 24
Peak memory 270572 kb
Host smart-146a1e57-abcc-4e01-82bc-8cc8119d7c63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188335774 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.188335774
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1472903245
Short name T1136
Test name
Test status
Simulation time 236511000 ps
CPU time 17.98 seconds
Started Jul 22 06:18:55 PM PDT 24
Finished Jul 22 06:19:14 PM PDT 24
Peak memory 261488 kb
Host smart-1185635d-fc81-4289-b98a-4476e9f0f4c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472903245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.1472903245
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1727124510
Short name T331
Test name
Test status
Simulation time 31463400 ps
CPU time 13.52 seconds
Started Jul 22 06:18:55 PM PDT 24
Finished Jul 22 06:19:10 PM PDT 24
Peak memory 261460 kb
Host smart-c0cc47c6-cb2b-4223-a45a-a21e58c537c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727124510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.1
727124510
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1117297055
Short name T306
Test name
Test status
Simulation time 403579200 ps
CPU time 20.78 seconds
Started Jul 22 06:19:26 PM PDT 24
Finished Jul 22 06:19:48 PM PDT 24
Peak memory 261600 kb
Host smart-a95d6c17-45ff-40f4-a23c-4215ddb9ac39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117297055 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.1117297055
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2226170439
Short name T1162
Test name
Test status
Simulation time 31554100 ps
CPU time 15.35 seconds
Started Jul 22 06:18:54 PM PDT 24
Finished Jul 22 06:19:10 PM PDT 24
Peak memory 253176 kb
Host smart-9cc97212-573f-48e6-b0d1-870d70d9a173
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226170439 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.2226170439
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2817374026
Short name T1207
Test name
Test status
Simulation time 13334600 ps
CPU time 15.74 seconds
Started Jul 22 06:18:56 PM PDT 24
Finished Jul 22 06:19:13 PM PDT 24
Peak memory 253208 kb
Host smart-702fee73-39e4-457b-b11a-68c51abc0fc3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817374026 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.2817374026
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2772452760
Short name T1235
Test name
Test status
Simulation time 67967600 ps
CPU time 17.02 seconds
Started Jul 22 06:20:43 PM PDT 24
Finished Jul 22 06:21:01 PM PDT 24
Peak memory 263980 kb
Host smart-6b5bde07-ec15-458b-bd1a-2dfc6e5a8828
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772452760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.2
772452760
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1272380717
Short name T366
Test name
Test status
Simulation time 965772300 ps
CPU time 458.73 seconds
Started Jul 22 06:20:41 PM PDT 24
Finished Jul 22 06:28:21 PM PDT 24
Peak memory 264024 kb
Host smart-6152b41c-bf61-49e5-b6ff-fbb22467e07b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272380717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.1272380717
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.3107972709
Short name T557
Test name
Test status
Simulation time 37513800 ps
CPU time 13.5 seconds
Started Jul 22 05:26:09 PM PDT 24
Finished Jul 22 05:26:23 PM PDT 24
Peak memory 258280 kb
Host smart-e43b14e3-271f-4ce6-8064-d0fdfd59466b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107972709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.3
107972709
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.447826922
Short name T429
Test name
Test status
Simulation time 39676600 ps
CPU time 16.14 seconds
Started Jul 22 05:26:07 PM PDT 24
Finished Jul 22 05:26:24 PM PDT 24
Peak memory 284284 kb
Host smart-0ad1a772-b60e-441f-a9ca-80f50de3d1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447826922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.447826922
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.1344172901
Short name T886
Test name
Test status
Simulation time 1601171000 ps
CPU time 1027.3 seconds
Started Jul 22 05:25:49 PM PDT 24
Finished Jul 22 05:42:57 PM PDT 24
Peak memory 270328 kb
Host smart-705b8ad5-aae1-4483-b904-24eba5d07e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344172901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.1344172901
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_addr_infection.1422568228
Short name T660
Test name
Test status
Simulation time 39877000 ps
CPU time 29.67 seconds
Started Jul 22 05:26:08 PM PDT 24
Finished Jul 22 05:26:39 PM PDT 24
Peak memory 268456 kb
Host smart-93c66768-cd4b-445e-815d-fd58f03fa617
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422568228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_host_addr_infection.1422568228
Directory /workspace/0.flash_ctrl_host_addr_infection/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.160137218
Short name T935
Test name
Test status
Simulation time 941349368800 ps
CPU time 2421.45 seconds
Started Jul 22 05:25:51 PM PDT 24
Finished Jul 22 06:06:14 PM PDT 24
Peak memory 264496 kb
Host smart-71840c12-6d32-4b1f-8828-2af83fee1809
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160137218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.flash_ctrl_host_ctrl_arb.160137218
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.2900619499
Short name T725
Test name
Test status
Simulation time 256713500 ps
CPU time 121.95 seconds
Started Jul 22 05:25:49 PM PDT 24
Finished Jul 22 05:27:52 PM PDT 24
Peak memory 265256 kb
Host smart-af9cfff5-04ad-4484-ac4c-5d15757f7721
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2900619499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.2900619499
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.1350563126
Short name T213
Test name
Test status
Simulation time 10058740300 ps
CPU time 50.83 seconds
Started Jul 22 05:26:07 PM PDT 24
Finished Jul 22 05:26:59 PM PDT 24
Peak memory 273736 kb
Host smart-322b6760-066a-4638-8b30-8e416e223740
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350563126 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.1350563126
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.1480633195
Short name T1107
Test name
Test status
Simulation time 340358540300 ps
CPU time 1962.54 seconds
Started Jul 22 05:25:47 PM PDT 24
Finished Jul 22 05:58:30 PM PDT 24
Peak memory 264692 kb
Host smart-84281586-490c-4082-82da-6c5f0449292d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480633195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.1480633195
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.140894098
Short name T204
Test name
Test status
Simulation time 40126549600 ps
CPU time 849.52 seconds
Started Jul 22 05:25:51 PM PDT 24
Finished Jul 22 05:40:02 PM PDT 24
Peak memory 264084 kb
Host smart-97f064ef-485a-4bf9-94c2-d69d3475e968
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140894098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_hw_rma_reset.140894098
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.870436528
Short name T675
Test name
Test status
Simulation time 3928926900 ps
CPU time 171.99 seconds
Started Jul 22 05:27:42 PM PDT 24
Finished Jul 22 05:30:35 PM PDT 24
Peak memory 263332 kb
Host smart-ff633cd4-be42-4a7e-80da-0ce408936c36
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870436528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw
_sec_otp.870436528
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.3761082769
Short name T677
Test name
Test status
Simulation time 548287200 ps
CPU time 135.79 seconds
Started Jul 22 05:25:59 PM PDT 24
Finished Jul 22 05:28:15 PM PDT 24
Peak memory 290976 kb
Host smart-7c39376d-f9c4-4aba-9f35-b9988c1b1b5a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761082769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_intr_rd.3761082769
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.616437626
Short name T782
Test name
Test status
Simulation time 166806371600 ps
CPU time 266.27 seconds
Started Jul 22 05:25:58 PM PDT 24
Finished Jul 22 05:30:25 PM PDT 24
Peak memory 292048 kb
Host smart-fb672ebe-9abd-4151-b295-7f6a328733ce
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616437626 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.616437626
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.3322516834
Short name T648
Test name
Test status
Simulation time 1995192800 ps
CPU time 67.99 seconds
Started Jul 22 05:27:42 PM PDT 24
Finished Jul 22 05:28:51 PM PDT 24
Peak memory 260692 kb
Host smart-462475c3-f233-4105-b1b1-5dcf3ba71aba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322516834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.3322516834
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.4154950834
Short name T1083
Test name
Test status
Simulation time 108237265500 ps
CPU time 269.06 seconds
Started Jul 22 05:26:08 PM PDT 24
Finished Jul 22 05:30:37 PM PDT 24
Peak memory 260496 kb
Host smart-2a31ebe5-61ef-48ba-b5b8-fb403a006b61
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415
4950834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.4154950834
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.1379521826
Short name T888
Test name
Test status
Simulation time 2069313500 ps
CPU time 90.03 seconds
Started Jul 22 05:25:50 PM PDT 24
Finished Jul 22 05:27:20 PM PDT 24
Peak memory 260512 kb
Host smart-bd306982-02b8-4965-8730-cd61a51fbaf3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379521826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.1379521826
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.634057867
Short name T705
Test name
Test status
Simulation time 107946200 ps
CPU time 13.61 seconds
Started Jul 22 05:26:07 PM PDT 24
Finished Jul 22 05:26:21 PM PDT 24
Peak memory 264964 kb
Host smart-ab75533d-0cea-4b04-92ca-5e84ef8b85db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634057867 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.634057867
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.3179864832
Short name T92
Test name
Test status
Simulation time 3939455000 ps
CPU time 74.11 seconds
Started Jul 22 05:25:52 PM PDT 24
Finished Jul 22 05:27:06 PM PDT 24
Peak memory 260752 kb
Host smart-c90305dd-0fd4-437a-b06d-b82c87960484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179864832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.3179864832
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.735178403
Short name T157
Test name
Test status
Simulation time 20959479300 ps
CPU time 294.44 seconds
Started Jul 22 05:25:49 PM PDT 24
Finished Jul 22 05:30:44 PM PDT 24
Peak memory 274796 kb
Host smart-3dce6885-4525-4475-82d0-5f9a4da6ed88
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735178403 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.735178403
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.1549975004
Short name T517
Test name
Test status
Simulation time 194457300 ps
CPU time 109.18 seconds
Started Jul 22 05:26:03 PM PDT 24
Finished Jul 22 05:27:52 PM PDT 24
Peak memory 261108 kb
Host smart-6e88b38d-b726-4fe0-a12a-eff579b6e22e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549975004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.1549975004
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.2698297953
Short name T1086
Test name
Test status
Simulation time 4775513600 ps
CPU time 192.03 seconds
Started Jul 22 05:26:01 PM PDT 24
Finished Jul 22 05:29:14 PM PDT 24
Peak memory 290364 kb
Host smart-811711b0-2c41-4cd8-9b4a-c82a01f43e9b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698297953 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.2698297953
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.3778374089
Short name T166
Test name
Test status
Simulation time 132837000 ps
CPU time 111.66 seconds
Started Jul 22 05:25:50 PM PDT 24
Finished Jul 22 05:27:42 PM PDT 24
Peak memory 263136 kb
Host smart-99bde961-7f12-4e98-aeb8-588458e8a550
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3778374089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.3778374089
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.3597678089
Short name T124
Test name
Test status
Simulation time 905882200 ps
CPU time 17.62 seconds
Started Jul 22 05:26:08 PM PDT 24
Finished Jul 22 05:26:27 PM PDT 24
Peak memory 265492 kb
Host smart-b827b1e5-1150-4e5e-bdf2-659697a789a4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597678089 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.3597678089
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.4255686077
Short name T1087
Test name
Test status
Simulation time 28399300 ps
CPU time 14.66 seconds
Started Jul 22 05:27:08 PM PDT 24
Finished Jul 22 05:27:23 PM PDT 24
Peak memory 265536 kb
Host smart-a1eb7106-946d-475e-9dc4-340bf8239124
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255686077 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.4255686077
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.3214143803
Short name T468
Test name
Test status
Simulation time 22728000 ps
CPU time 13.66 seconds
Started Jul 22 05:26:07 PM PDT 24
Finished Jul 22 05:26:22 PM PDT 24
Peak memory 265256 kb
Host smart-b3618558-64f5-441d-886a-9cf055bb87eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214143803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.flash_ctrl_prog_reset.3214143803
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.1756390525
Short name T529
Test name
Test status
Simulation time 724852200 ps
CPU time 105.36 seconds
Started Jul 22 05:25:47 PM PDT 24
Finished Jul 22 05:27:34 PM PDT 24
Peak memory 262812 kb
Host smart-17544741-4f1f-478b-bc94-ad1447444696
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1756390525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.1756390525
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.1350127783
Short name T747
Test name
Test status
Simulation time 65277800 ps
CPU time 29.38 seconds
Started Jul 22 05:26:08 PM PDT 24
Finished Jul 22 05:26:38 PM PDT 24
Peak memory 268444 kb
Host smart-d85d22b2-0ccb-4519-8b22-7b927e577a08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350127783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.1350127783
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.2626177668
Short name T534
Test name
Test status
Simulation time 269960300 ps
CPU time 46.13 seconds
Started Jul 22 05:27:10 PM PDT 24
Finished Jul 22 05:27:56 PM PDT 24
Peak memory 275768 kb
Host smart-d396c6e6-8f04-48d7-b016-e29fdb91f46e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626177668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.2626177668
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.4232898563
Short name T354
Test name
Test status
Simulation time 286826400 ps
CPU time 31.51 seconds
Started Jul 22 05:26:08 PM PDT 24
Finished Jul 22 05:26:40 PM PDT 24
Peak memory 268600 kb
Host smart-7d0d56a1-fa24-4e3f-a5f6-c988a47fd7cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232898563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.4232898563
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.3329720473
Short name T444
Test name
Test status
Simulation time 25193900 ps
CPU time 14.24 seconds
Started Jul 22 05:25:47 PM PDT 24
Finished Jul 22 05:26:03 PM PDT 24
Peak memory 265264 kb
Host smart-45ae076a-58cc-4046-ada2-8906263bc221
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3329720473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.3329720473
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.4110286632
Short name T914
Test name
Test status
Simulation time 62234300 ps
CPU time 23.14 seconds
Started Jul 22 05:25:59 PM PDT 24
Finished Jul 22 05:26:22 PM PDT 24
Peak memory 264920 kb
Host smart-2bcc80fc-ae76-41a5-beac-c0e021dfb4eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110286632 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.4110286632
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.2709700851
Short name T511
Test name
Test status
Simulation time 24860400 ps
CPU time 21.86 seconds
Started Jul 22 05:25:57 PM PDT 24
Finished Jul 22 05:26:19 PM PDT 24
Peak memory 265360 kb
Host smart-ab137b18-b7e4-491a-8874-286c40fd512d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709700851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.2709700851
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.480969756
Short name T197
Test name
Test status
Simulation time 95757353700 ps
CPU time 1354.4 seconds
Started Jul 22 05:26:48 PM PDT 24
Finished Jul 22 05:49:23 PM PDT 24
Peak memory 568104 kb
Host smart-412e57be-389e-4281-af9d-867da1764cb6
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480969756 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.480969756
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.1090250430
Short name T223
Test name
Test status
Simulation time 1293430700 ps
CPU time 103.2 seconds
Started Jul 22 05:25:52 PM PDT 24
Finished Jul 22 05:27:36 PM PDT 24
Peak memory 289364 kb
Host smart-150ae2d4-7c1c-4530-a977-830e1d6dbf6b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090250430 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_ro.1090250430
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.2901232585
Short name T751
Test name
Test status
Simulation time 2516733200 ps
CPU time 144.91 seconds
Started Jul 22 05:25:58 PM PDT 24
Finished Jul 22 05:28:23 PM PDT 24
Peak memory 281816 kb
Host smart-69ee81db-78c3-4a75-b099-6152f0dfca67
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2901232585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.2901232585
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.326017743
Short name T784
Test name
Test status
Simulation time 568807400 ps
CPU time 167.59 seconds
Started Jul 22 05:26:05 PM PDT 24
Finished Jul 22 05:28:53 PM PDT 24
Peak memory 295476 kb
Host smart-de776b24-05fe-45ea-ab66-744342e6b7e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326017743 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.326017743
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.1174168823
Short name T618
Test name
Test status
Simulation time 3787830500 ps
CPU time 503.65 seconds
Started Jul 22 05:27:11 PM PDT 24
Finished Jul 22 05:35:35 PM PDT 24
Peak memory 309592 kb
Host smart-d2a1272c-7de1-4830-9fc6-b0104e62b265
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174168823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_rw.1174168823
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.3530215520
Short name T559
Test name
Test status
Simulation time 44413200 ps
CPU time 30.56 seconds
Started Jul 22 05:26:06 PM PDT 24
Finished Jul 22 05:26:38 PM PDT 24
Peak memory 275636 kb
Host smart-b370b2e8-ef7f-4be7-b88c-603eec47a78d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530215520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.3530215520
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.1974797807
Short name T971
Test name
Test status
Simulation time 67043400 ps
CPU time 31.44 seconds
Started Jul 22 05:26:08 PM PDT 24
Finished Jul 22 05:26:40 PM PDT 24
Peak memory 273592 kb
Host smart-e09dfcb4-5d5c-49ce-b3ea-2f687573fa24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974797807 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.1974797807
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_serr.2162154922
Short name T827
Test name
Test status
Simulation time 7510028100 ps
CPU time 676.39 seconds
Started Jul 22 05:26:01 PM PDT 24
Finished Jul 22 05:37:18 PM PDT 24
Peak memory 313024 kb
Host smart-8f48fb2d-e7ec-4006-bbac-771fc711980d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162154922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_s
err.2162154922
Directory /workspace/0.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.1935223242
Short name T402
Test name
Test status
Simulation time 1740273600 ps
CPU time 64.34 seconds
Started Jul 22 05:27:23 PM PDT 24
Finished Jul 22 05:28:28 PM PDT 24
Peak memory 264776 kb
Host smart-9e57c5ba-87e6-470a-b57b-8953e4423b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935223242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.1935223242
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.3938063299
Short name T907
Test name
Test status
Simulation time 722513500 ps
CPU time 51.87 seconds
Started Jul 22 05:25:58 PM PDT 24
Finished Jul 22 05:26:50 PM PDT 24
Peak memory 273556 kb
Host smart-75a539a7-3235-4a13-8df1-8931bacb11ec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938063299 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.3938063299
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.1800736962
Short name T979
Test name
Test status
Simulation time 27025300 ps
CPU time 172.19 seconds
Started Jul 22 05:25:45 PM PDT 24
Finished Jul 22 05:28:39 PM PDT 24
Peak memory 280512 kb
Host smart-58bb5870-0e5a-47b9-9cbc-4ef99b8a06ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800736962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.1800736962
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.1432063454
Short name T23
Test name
Test status
Simulation time 58270700 ps
CPU time 25.86 seconds
Started Jul 22 05:25:46 PM PDT 24
Finished Jul 22 05:26:13 PM PDT 24
Peak memory 259692 kb
Host smart-0cf0ac95-f229-4e77-abf8-b78e7a16da3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432063454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.1432063454
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.544672222
Short name T388
Test name
Test status
Simulation time 355887800 ps
CPU time 1631.1 seconds
Started Jul 22 05:26:09 PM PDT 24
Finished Jul 22 05:53:21 PM PDT 24
Peak memory 291004 kb
Host smart-31fcc4a2-adca-4215-91b9-92a544d77e81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544672222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress
_all.544672222
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.1646330042
Short name T772
Test name
Test status
Simulation time 257461400 ps
CPU time 26.26 seconds
Started Jul 22 05:25:52 PM PDT 24
Finished Jul 22 05:26:19 PM PDT 24
Peak memory 262560 kb
Host smart-90724358-6da3-4bb5-8492-a06babc4758d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646330042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.1646330042
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.76219022
Short name T855
Test name
Test status
Simulation time 22384790600 ps
CPU time 210.91 seconds
Started Jul 22 05:25:50 PM PDT 24
Finished Jul 22 05:29:21 PM PDT 24
Peak memory 260104 kb
Host smart-2dfd284d-8274-4f87-b467-b0a4ff31f8ad
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76219022 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_wo.76219022
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.1660076837
Short name T234
Test name
Test status
Simulation time 43025000 ps
CPU time 14.96 seconds
Started Jul 22 05:26:10 PM PDT 24
Finished Jul 22 05:26:26 PM PDT 24
Peak memory 260984 kb
Host smart-db3e1340-efc0-42a2-9bd9-5e2bd529b4e7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660076837 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.1660076837
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.1134041296
Short name T860
Test name
Test status
Simulation time 148096400 ps
CPU time 15.49 seconds
Started Jul 22 05:25:56 PM PDT 24
Finished Jul 22 05:26:12 PM PDT 24
Peak memory 265072 kb
Host smart-ede37f9a-13a7-48cd-9ba1-d4ab51080ba9
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1134041296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.1134041296
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.1984309028
Short name T868
Test name
Test status
Simulation time 335932800 ps
CPU time 13.67 seconds
Started Jul 22 05:27:07 PM PDT 24
Finished Jul 22 05:27:21 PM PDT 24
Peak memory 265280 kb
Host smart-b0710c88-597f-4715-9df7-899a3b550ac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984309028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.1
984309028
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.3144474025
Short name T946
Test name
Test status
Simulation time 20243800 ps
CPU time 13.95 seconds
Started Jul 22 05:26:32 PM PDT 24
Finished Jul 22 05:26:47 PM PDT 24
Peak memory 264892 kb
Host smart-f2c4c955-5735-4484-9b13-eadde92811a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144474025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.3144474025
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.3805435790
Short name T881
Test name
Test status
Simulation time 17272000 ps
CPU time 15.91 seconds
Started Jul 22 05:26:35 PM PDT 24
Finished Jul 22 05:26:52 PM PDT 24
Peak memory 274904 kb
Host smart-ac597966-b5be-43c2-863b-511a38e40484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805435790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.3805435790
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.1588669366
Short name T950
Test name
Test status
Simulation time 179334900 ps
CPU time 241.34 seconds
Started Jul 22 05:26:18 PM PDT 24
Finished Jul 22 05:30:21 PM PDT 24
Peak memory 263376 kb
Host smart-d7b6752a-636b-4572-9de1-660eb72aaa8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1588669366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.1588669366
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.2002200871
Short name T805
Test name
Test status
Simulation time 10906135800 ps
CPU time 2179.85 seconds
Started Jul 22 05:26:18 PM PDT 24
Finished Jul 22 06:02:39 PM PDT 24
Peak memory 262852 kb
Host smart-30f7511c-4079-4533-9e64-06d2bdae0f56
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2002200871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.2002200871
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.1581733182
Short name T911
Test name
Test status
Simulation time 3462558100 ps
CPU time 2013.03 seconds
Started Jul 22 05:26:18 PM PDT 24
Finished Jul 22 05:59:52 PM PDT 24
Peak memory 265016 kb
Host smart-09aa8682-4769-4740-968a-815bc7473881
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581733182 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.1581733182
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.2023285129
Short name T484
Test name
Test status
Simulation time 3386204300 ps
CPU time 900.66 seconds
Started Jul 22 05:26:17 PM PDT 24
Finished Jul 22 05:41:19 PM PDT 24
Peak memory 272752 kb
Host smart-e859eedf-2bf8-419c-9fcd-4149a9445a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023285129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2023285129
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.618442890
Short name T487
Test name
Test status
Simulation time 1292768000 ps
CPU time 38.46 seconds
Started Jul 22 05:26:33 PM PDT 24
Finished Jul 22 05:27:12 PM PDT 24
Peak memory 262952 kb
Host smart-396014c9-8642-42a5-8c62-d1f9f0bc2417
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618442890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_fs_sup.618442890
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.4166578631
Short name T128
Test name
Test status
Simulation time 60653293100 ps
CPU time 4059.18 seconds
Started Jul 22 05:26:18 PM PDT 24
Finished Jul 22 06:33:58 PM PDT 24
Peak memory 265168 kb
Host smart-da1b8945-099c-488d-8d4b-4d28b9546ded
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166578631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.4166578631
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_addr_infection.2504335082
Short name T718
Test name
Test status
Simulation time 27747400 ps
CPU time 27.14 seconds
Started Jul 22 05:26:34 PM PDT 24
Finished Jul 22 05:27:02 PM PDT 24
Peak memory 275524 kb
Host smart-906a4338-f58f-4eab-a927-ba823bd8783b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504335082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_host_addr_infection.2504335082
Directory /workspace/1.flash_ctrl_host_addr_infection/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.538882545
Short name T212
Test name
Test status
Simulation time 65634000 ps
CPU time 113.63 seconds
Started Jul 22 05:26:16 PM PDT 24
Finished Jul 22 05:28:10 PM PDT 24
Peak memory 265268 kb
Host smart-05d366c6-1cf7-44f5-b6c3-de1d67304582
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538882545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.538882545
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.3633698113
Short name T818
Test name
Test status
Simulation time 29497000 ps
CPU time 13.25 seconds
Started Jul 22 05:26:31 PM PDT 24
Finished Jul 22 05:26:45 PM PDT 24
Peak memory 258516 kb
Host smart-5d75d8cf-6a10-470b-adfd-3673e9d9b9f1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633698113 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.3633698113
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.1934730420
Short name T1019
Test name
Test status
Simulation time 94820631000 ps
CPU time 1887.01 seconds
Started Jul 22 05:26:16 PM PDT 24
Finished Jul 22 05:57:44 PM PDT 24
Peak memory 260612 kb
Host smart-e8333f04-4271-4951-95c7-6cb647c363f4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934730420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.1934730420
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2007792722
Short name T752
Test name
Test status
Simulation time 80145994600 ps
CPU time 883.58 seconds
Started Jul 22 05:26:17 PM PDT 24
Finished Jul 22 05:41:01 PM PDT 24
Peak memory 260988 kb
Host smart-4b20126a-fcf1-467a-a8fc-92bf7671c138
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007792722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.2007792722
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.991874098
Short name T1053
Test name
Test status
Simulation time 26072667300 ps
CPU time 165.56 seconds
Started Jul 22 05:26:19 PM PDT 24
Finished Jul 22 05:29:05 PM PDT 24
Peak memory 263212 kb
Host smart-01235661-d7b3-4692-b96c-b2b5fff62750
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991874098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw
_sec_otp.991874098
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.4184818366
Short name T694
Test name
Test status
Simulation time 15345036200 ps
CPU time 712.34 seconds
Started Jul 22 05:26:24 PM PDT 24
Finished Jul 22 05:38:17 PM PDT 24
Peak memory 337944 kb
Host smart-bb777ab3-9c92-4cbd-9aae-0fb772ed1f43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184818366 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.4184818366
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.3199351002
Short name T861
Test name
Test status
Simulation time 8100307000 ps
CPU time 189.78 seconds
Started Jul 22 05:26:34 PM PDT 24
Finished Jul 22 05:29:44 PM PDT 24
Peak memory 291008 kb
Host smart-7ebf6e25-1fc4-4629-9eb4-10c5619d1565
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199351002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_intr_rd.3199351002
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.3192602904
Short name T671
Test name
Test status
Simulation time 12204294200 ps
CPU time 147.25 seconds
Started Jul 22 05:26:34 PM PDT 24
Finished Jul 22 05:29:02 PM PDT 24
Peak memory 297936 kb
Host smart-b67c3dc0-cad3-4a9c-902f-2321994e0ebd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192602904 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.3192602904
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.139405949
Short name T533
Test name
Test status
Simulation time 2370161400 ps
CPU time 69.11 seconds
Started Jul 22 05:26:32 PM PDT 24
Finished Jul 22 05:27:42 PM PDT 24
Peak memory 265376 kb
Host smart-ea79c5f8-714c-4443-b9ec-f1a3585cace2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139405949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_intr_wr.139405949
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.1438347858
Short name T824
Test name
Test status
Simulation time 56559466300 ps
CPU time 215.08 seconds
Started Jul 22 05:26:23 PM PDT 24
Finished Jul 22 05:29:59 PM PDT 24
Peak memory 260600 kb
Host smart-22c6da55-cdee-4f3f-9625-71e874c55775
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143
8347858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.1438347858
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.235416098
Short name T1069
Test name
Test status
Simulation time 8631107400 ps
CPU time 75.22 seconds
Started Jul 22 05:26:16 PM PDT 24
Finished Jul 22 05:27:32 PM PDT 24
Peak memory 260604 kb
Host smart-b68ad0b1-ad3a-4022-ac63-719798105a8d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235416098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.235416098
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.205684608
Short name T91
Test name
Test status
Simulation time 10568825200 ps
CPU time 68.72 seconds
Started Jul 22 05:26:17 PM PDT 24
Finished Jul 22 05:27:26 PM PDT 24
Peak memory 260728 kb
Host smart-fdc0980f-c41b-4ab9-afbb-a1d4f9a21783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205684608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.205684608
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.3678351590
Short name T133
Test name
Test status
Simulation time 4982042900 ps
CPU time 402.3 seconds
Started Jul 22 05:26:17 PM PDT 24
Finished Jul 22 05:33:00 PM PDT 24
Peak memory 273728 kb
Host smart-3444eaa2-6cb8-42ed-ae1b-b164008c146b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678351590 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.3678351590
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.3134083294
Short name T1033
Test name
Test status
Simulation time 229830200 ps
CPU time 134.14 seconds
Started Jul 22 05:26:18 PM PDT 24
Finished Jul 22 05:28:33 PM PDT 24
Peak memory 260212 kb
Host smart-60af9185-3748-437c-b386-afa3d18c6017
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134083294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.3134083294
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.2613392035
Short name T1103
Test name
Test status
Simulation time 2633171000 ps
CPU time 224.12 seconds
Started Jul 22 05:26:33 PM PDT 24
Finished Jul 22 05:30:18 PM PDT 24
Peak memory 281808 kb
Host smart-f4154f2d-4cc0-4ebb-b0ce-40008e4222a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613392035 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.2613392035
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.3322845706
Short name T79
Test name
Test status
Simulation time 79643300 ps
CPU time 16.11 seconds
Started Jul 22 05:26:23 PM PDT 24
Finished Jul 22 05:26:39 PM PDT 24
Peak memory 265136 kb
Host smart-64737ef8-971c-4329-978c-75fe34f81a67
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3322845706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.3322845706
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.1932720637
Short name T600
Test name
Test status
Simulation time 74845100 ps
CPU time 148.63 seconds
Started Jul 22 05:26:17 PM PDT 24
Finished Jul 22 05:28:46 PM PDT 24
Peak memory 263236 kb
Host smart-39202957-a13f-496f-b79b-4fef2ea09021
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932720637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.1932720637
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.1122863730
Short name T177
Test name
Test status
Simulation time 23971900 ps
CPU time 13.99 seconds
Started Jul 22 05:26:22 PM PDT 24
Finished Jul 22 05:26:36 PM PDT 24
Peak memory 265352 kb
Host smart-65533bfc-a8d8-4bcf-a859-50d2ed8d0a6d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122863730 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.1122863730
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.2772044536
Short name T1008
Test name
Test status
Simulation time 74920400 ps
CPU time 13.52 seconds
Started Jul 22 05:26:35 PM PDT 24
Finished Jul 22 05:26:49 PM PDT 24
Peak memory 259268 kb
Host smart-8e5a50b2-79b1-4c4c-84bf-6917cd141a1c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772044536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.flash_ctrl_prog_reset.2772044536
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.2017423716
Short name T781
Test name
Test status
Simulation time 220728000 ps
CPU time 407.62 seconds
Started Jul 22 05:26:07 PM PDT 24
Finished Jul 22 05:32:55 PM PDT 24
Peak memory 281596 kb
Host smart-486418d1-9652-4536-bdc2-4d1f7ee21f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017423716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.2017423716
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.3317998462
Short name T285
Test name
Test status
Simulation time 139286600 ps
CPU time 100.02 seconds
Started Jul 22 05:26:16 PM PDT 24
Finished Jul 22 05:27:56 PM PDT 24
Peak memory 262748 kb
Host smart-f8a049e3-0822-47ba-b2a9-4092b90d0336
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3317998462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.3317998462
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.820021803
Short name T570
Test name
Test status
Simulation time 62879300 ps
CPU time 34.82 seconds
Started Jul 22 05:26:32 PM PDT 24
Finished Jul 22 05:27:07 PM PDT 24
Peak memory 268520 kb
Host smart-b716289e-f422-46a7-9f44-7108be5e8926
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820021803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_re_evict.820021803
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.1449807908
Short name T57
Test name
Test status
Simulation time 60877700 ps
CPU time 21.48 seconds
Started Jul 22 05:26:33 PM PDT 24
Finished Jul 22 05:26:55 PM PDT 24
Peak memory 265432 kb
Host smart-c6b5dafd-1c1e-4d5d-ac24-f46d8cd48c6f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449807908 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.1449807908
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.3855669690
Short name T1082
Test name
Test status
Simulation time 24994900 ps
CPU time 21.1 seconds
Started Jul 22 05:26:19 PM PDT 24
Finished Jul 22 05:26:41 PM PDT 24
Peak memory 265400 kb
Host smart-9c8b5b12-8a9d-4dca-8199-761121a57f10
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855669690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.3855669690
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.2061995681
Short name T734
Test name
Test status
Simulation time 2207409700 ps
CPU time 136.1 seconds
Started Jul 22 05:26:16 PM PDT 24
Finished Jul 22 05:28:33 PM PDT 24
Peak memory 281732 kb
Host smart-c3fda39b-fea4-4124-aba7-25829e727a15
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061995681 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_ro.2061995681
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.2351340875
Short name T56
Test name
Test status
Simulation time 1315474600 ps
CPU time 157.31 seconds
Started Jul 22 05:26:25 PM PDT 24
Finished Jul 22 05:29:03 PM PDT 24
Peak memory 283032 kb
Host smart-d0037d33-7106-4f58-9cec-6068be148e6c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2351340875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.2351340875
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.2307936250
Short name T869
Test name
Test status
Simulation time 908354100 ps
CPU time 153 seconds
Started Jul 22 05:26:16 PM PDT 24
Finished Jul 22 05:28:50 PM PDT 24
Peak memory 294980 kb
Host smart-b48bdda2-a0ee-47df-a47a-3503dfe04c2b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307936250 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.2307936250
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.2567262376
Short name T219
Test name
Test status
Simulation time 6177253600 ps
CPU time 544.73 seconds
Started Jul 22 05:26:18 PM PDT 24
Finished Jul 22 05:35:23 PM PDT 24
Peak memory 314668 kb
Host smart-ebda1a83-8809-4faf-a51c-b46451a9e32b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567262376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.flash_ctrl_rw.2567262376
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.444885207
Short name T482
Test name
Test status
Simulation time 62006900 ps
CPU time 28.69 seconds
Started Jul 22 05:26:31 PM PDT 24
Finished Jul 22 05:27:00 PM PDT 24
Peak memory 267376 kb
Host smart-92c32a0e-9bbc-43df-9f18-60e84a84298d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444885207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_rw_evict.444885207
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.2195905495
Short name T1091
Test name
Test status
Simulation time 27427900 ps
CPU time 30.76 seconds
Started Jul 22 05:26:27 PM PDT 24
Finished Jul 22 05:26:58 PM PDT 24
Peak memory 275672 kb
Host smart-0c41398f-8fa5-4eb2-b1b8-23deb2f41fe4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195905495 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.2195905495
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.1817717133
Short name T410
Test name
Test status
Simulation time 3198727300 ps
CPU time 68.1 seconds
Started Jul 22 05:26:30 PM PDT 24
Finished Jul 22 05:27:38 PM PDT 24
Peak memory 263648 kb
Host smart-0c333c08-501e-4c52-a9f2-aa5fde924186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817717133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.1817717133
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.3577851824
Short name T741
Test name
Test status
Simulation time 2551348600 ps
CPU time 65.03 seconds
Started Jul 22 05:26:17 PM PDT 24
Finished Jul 22 05:27:23 PM PDT 24
Peak memory 273620 kb
Host smart-c4ad4a3d-e50b-4bd9-b056-1d7640020989
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577851824 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.3577851824
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.2432247730
Short name T127
Test name
Test status
Simulation time 2453238700 ps
CPU time 65.82 seconds
Started Jul 22 05:26:15 PM PDT 24
Finished Jul 22 05:27:21 PM PDT 24
Peak memory 273464 kb
Host smart-41a189cf-a319-4501-9e8f-5a91048c1e2f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432247730 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.2432247730
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.3643520858
Short name T476
Test name
Test status
Simulation time 116238900 ps
CPU time 123.68 seconds
Started Jul 22 05:26:08 PM PDT 24
Finished Jul 22 05:28:12 PM PDT 24
Peak memory 276388 kb
Host smart-e857f0a2-832f-4756-b532-770906a52a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643520858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3643520858
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.1552826527
Short name T825
Test name
Test status
Simulation time 15524500 ps
CPU time 26.48 seconds
Started Jul 22 05:26:06 PM PDT 24
Finished Jul 22 05:26:33 PM PDT 24
Peak memory 259672 kb
Host smart-452c2762-c1b0-4502-89bb-6c1400530d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552826527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.1552826527
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.2513730719
Short name T1040
Test name
Test status
Simulation time 1315043900 ps
CPU time 1443.18 seconds
Started Jul 22 05:28:02 PM PDT 24
Finished Jul 22 05:52:05 PM PDT 24
Peak memory 289900 kb
Host smart-4c5bcb9d-b14b-4a05-978b-f8fcf8b85166
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513730719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.2513730719
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.1125463752
Short name T524
Test name
Test status
Simulation time 36848200 ps
CPU time 26.94 seconds
Started Jul 22 05:26:17 PM PDT 24
Finished Jul 22 05:26:44 PM PDT 24
Peak memory 259904 kb
Host smart-10cfa2af-ba6c-4b74-99e4-601e2459295b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125463752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.1125463752
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.4287333995
Short name T1029
Test name
Test status
Simulation time 4565157300 ps
CPU time 161.54 seconds
Started Jul 22 05:27:23 PM PDT 24
Finished Jul 22 05:30:05 PM PDT 24
Peak memory 265320 kb
Host smart-8ddf38c4-2da8-4d2b-8e00-2a912b2fac99
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287333995 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_wo.4287333995
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.1750904962
Short name T425
Test name
Test status
Simulation time 17974400 ps
CPU time 13.47 seconds
Started Jul 22 05:30:09 PM PDT 24
Finished Jul 22 05:30:24 PM PDT 24
Peak memory 258272 kb
Host smart-2f8b3c72-46ca-42b8-aee5-8125f3b9f599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750904962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
1750904962
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.1998461756
Short name T458
Test name
Test status
Simulation time 22645900 ps
CPU time 13.81 seconds
Started Jul 22 05:30:05 PM PDT 24
Finished Jul 22 05:30:19 PM PDT 24
Peak memory 274784 kb
Host smart-e58786f9-078d-4552-b528-4f3df52d7b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998461756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.1998461756
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2710080798
Short name T493
Test name
Test status
Simulation time 10031555300 ps
CPU time 65.98 seconds
Started Jul 22 05:30:05 PM PDT 24
Finished Jul 22 05:31:11 PM PDT 24
Peak memory 294804 kb
Host smart-34055107-622a-46ba-a569-db53e3722479
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710080798 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.2710080798
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.43635546
Short name T1074
Test name
Test status
Simulation time 14974300 ps
CPU time 13.41 seconds
Started Jul 22 05:30:09 PM PDT 24
Finished Jul 22 05:30:23 PM PDT 24
Peak memory 260168 kb
Host smart-149f4e58-2778-4cb7-86e9-c45e2fe6da60
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43635546 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.43635546
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.1375404011
Short name T614
Test name
Test status
Simulation time 40122722000 ps
CPU time 860.8 seconds
Started Jul 22 05:29:46 PM PDT 24
Finished Jul 22 05:44:08 PM PDT 24
Peak memory 261148 kb
Host smart-d511011e-cd48-4f8b-8803-1e6730e0c28f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375404011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.1375404011
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.3664020974
Short name T326
Test name
Test status
Simulation time 2252890800 ps
CPU time 189.38 seconds
Started Jul 22 05:29:47 PM PDT 24
Finished Jul 22 05:32:56 PM PDT 24
Peak memory 261056 kb
Host smart-89255929-0ab7-48eb-b0c6-8027dc7aba40
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664020974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.3664020974
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.2307106143
Short name T339
Test name
Test status
Simulation time 2759156500 ps
CPU time 213.66 seconds
Started Jul 22 05:29:56 PM PDT 24
Finished Jul 22 05:33:30 PM PDT 24
Peak memory 284972 kb
Host smart-3b68d8e2-dd4e-4494-ba10-3cef7bb388a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307106143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.2307106143
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.4122036363
Short name T666
Test name
Test status
Simulation time 52163999200 ps
CPU time 299.25 seconds
Started Jul 22 05:29:58 PM PDT 24
Finished Jul 22 05:34:57 PM PDT 24
Peak memory 285320 kb
Host smart-9e45001a-6fa1-4043-b072-074cf5e5e685
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122036363 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.4122036363
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.1969553681
Short name T993
Test name
Test status
Simulation time 22413400 ps
CPU time 13.83 seconds
Started Jul 22 05:30:03 PM PDT 24
Finished Jul 22 05:30:17 PM PDT 24
Peak memory 260816 kb
Host smart-1981ab94-fea5-46ee-9896-53bebbad593b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969553681 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.1969553681
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.1462952934
Short name T643
Test name
Test status
Simulation time 6759981300 ps
CPU time 242.78 seconds
Started Jul 22 05:29:57 PM PDT 24
Finished Jul 22 05:34:00 PM PDT 24
Peak memory 265304 kb
Host smart-f5116187-9e16-40af-97c2-31bfbc9c6caf
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462952934 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.1462952934
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.2018785837
Short name T858
Test name
Test status
Simulation time 490150400 ps
CPU time 130.47 seconds
Started Jul 22 05:29:57 PM PDT 24
Finished Jul 22 05:32:08 PM PDT 24
Peak memory 259948 kb
Host smart-e266f924-8d94-4427-9241-94e0f7f35494
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018785837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.2018785837
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.3721020325
Short name T963
Test name
Test status
Simulation time 1985913600 ps
CPU time 512.77 seconds
Started Jul 22 05:29:46 PM PDT 24
Finished Jul 22 05:38:19 PM PDT 24
Peak memory 263240 kb
Host smart-4fd58515-67f9-4213-870f-de3bd81f115f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3721020325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3721020325
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.1475333594
Short name T392
Test name
Test status
Simulation time 32543500 ps
CPU time 13.45 seconds
Started Jul 22 05:29:57 PM PDT 24
Finished Jul 22 05:30:11 PM PDT 24
Peak memory 259228 kb
Host smart-7c7e107f-4caf-4d8f-a374-272bf7546c5f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475333594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.flash_ctrl_prog_reset.1475333594
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.3148693715
Short name T167
Test name
Test status
Simulation time 29595100 ps
CPU time 150.64 seconds
Started Jul 22 05:30:06 PM PDT 24
Finished Jul 22 05:32:37 PM PDT 24
Peak memory 273832 kb
Host smart-6ba66539-d349-4a2f-8aa7-2e77d368865a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148693715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.3148693715
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.1429812625
Short name T513
Test name
Test status
Simulation time 218070500 ps
CPU time 35.26 seconds
Started Jul 22 05:29:56 PM PDT 24
Finished Jul 22 05:30:32 PM PDT 24
Peak memory 275716 kb
Host smart-c11b0491-f19d-4f67-ae65-2833f4c6d840
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429812625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.1429812625
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.2425106542
Short name T597
Test name
Test status
Simulation time 1526543300 ps
CPU time 101.02 seconds
Started Jul 22 05:30:01 PM PDT 24
Finished Jul 22 05:31:42 PM PDT 24
Peak memory 281036 kb
Host smart-73c17ece-d7e0-4a54-bd58-36e8a287401c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425106542 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.flash_ctrl_ro.2425106542
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.2955508093
Short name T1075
Test name
Test status
Simulation time 7291663800 ps
CPU time 600.5 seconds
Started Jul 22 05:30:01 PM PDT 24
Finished Jul 22 05:40:02 PM PDT 24
Peak memory 317704 kb
Host smart-99d4c4f7-2562-4f33-bc8d-72fc7005bb97
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955508093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.flash_ctrl_rw.2955508093
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.44442354
Short name T733
Test name
Test status
Simulation time 30279400 ps
CPU time 29.1 seconds
Started Jul 22 05:29:58 PM PDT 24
Finished Jul 22 05:30:27 PM PDT 24
Peak memory 275680 kb
Host smart-8efda5ab-2ee2-49c6-9792-784fe8015e50
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44442354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flas
h_ctrl_rw_evict.44442354
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.3410407555
Short name T955
Test name
Test status
Simulation time 69348300 ps
CPU time 30.98 seconds
Started Jul 22 05:29:58 PM PDT 24
Finished Jul 22 05:30:30 PM PDT 24
Peak memory 275716 kb
Host smart-4d170410-dbc7-44f8-9f4e-571614195564
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410407555 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.3410407555
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.125392436
Short name T990
Test name
Test status
Simulation time 2112116500 ps
CPU time 81.65 seconds
Started Jul 22 05:30:04 PM PDT 24
Finished Jul 22 05:31:27 PM PDT 24
Peak memory 263160 kb
Host smart-77dba6e9-fb35-4843-beaf-d42321e5f0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125392436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.125392436
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.1720236947
Short name T651
Test name
Test status
Simulation time 97912100 ps
CPU time 120.31 seconds
Started Jul 22 05:30:06 PM PDT 24
Finished Jul 22 05:32:07 PM PDT 24
Peak memory 276388 kb
Host smart-bf5b6c03-4f33-49ad-9990-75f5a8e77096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720236947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.1720236947
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.4095770120
Short name T681
Test name
Test status
Simulation time 13367950300 ps
CPU time 180.05 seconds
Started Jul 22 05:29:57 PM PDT 24
Finished Jul 22 05:32:58 PM PDT 24
Peak memory 260092 kb
Host smart-b88acd59-69cb-4338-8c52-0c5b95cc73dd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095770120 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.flash_ctrl_wo.4095770120
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.914981814
Short name T160
Test name
Test status
Simulation time 39507700 ps
CPU time 13.89 seconds
Started Jul 22 05:30:27 PM PDT 24
Finished Jul 22 05:30:41 PM PDT 24
Peak memory 258368 kb
Host smart-7c9c4808-561a-41d5-b669-a99eaaaa25a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914981814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.914981814
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.1256556054
Short name T399
Test name
Test status
Simulation time 37373400 ps
CPU time 22.16 seconds
Started Jul 22 05:30:21 PM PDT 24
Finished Jul 22 05:30:44 PM PDT 24
Peak memory 273664 kb
Host smart-7c5f73ea-8915-41ad-b049-185cdeb0a058
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256556054 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.1256556054
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.1830998693
Short name T926
Test name
Test status
Simulation time 10018354700 ps
CPU time 79.92 seconds
Started Jul 22 05:30:22 PM PDT 24
Finished Jul 22 05:31:43 PM PDT 24
Peak memory 311272 kb
Host smart-67d55d67-d45a-4d1e-8bfe-d0a08440e474
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830998693 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.1830998693
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.3402800323
Short name T853
Test name
Test status
Simulation time 29832600 ps
CPU time 13.76 seconds
Started Jul 22 05:30:21 PM PDT 24
Finished Jul 22 05:30:35 PM PDT 24
Peak memory 258608 kb
Host smart-633e14cf-4e48-4c36-9151-8a55027d8732
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402800323 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.3402800323
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.3385810694
Short name T684
Test name
Test status
Simulation time 110158581500 ps
CPU time 865.8 seconds
Started Jul 22 05:30:09 PM PDT 24
Finished Jul 22 05:44:36 PM PDT 24
Peak memory 264180 kb
Host smart-b4b70059-7264-402a-892d-9956f979be01
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385810694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.3385810694
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.128976116
Short name T1021
Test name
Test status
Simulation time 10333338900 ps
CPU time 177.28 seconds
Started Jul 22 05:30:06 PM PDT 24
Finished Jul 22 05:33:04 PM PDT 24
Peak memory 261080 kb
Host smart-dfbd82c5-8099-45ed-984f-dce3d427510d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128976116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_h
w_sec_otp.128976116
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.1652037915
Short name T277
Test name
Test status
Simulation time 1899493300 ps
CPU time 193.02 seconds
Started Jul 22 05:30:14 PM PDT 24
Finished Jul 22 05:33:28 PM PDT 24
Peak memory 284852 kb
Host smart-68e45ed9-de4f-43e6-a691-c01cabec4164
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652037915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.1652037915
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.553652295
Short name T1100
Test name
Test status
Simulation time 1331817100 ps
CPU time 87.27 seconds
Started Jul 22 05:30:05 PM PDT 24
Finished Jul 22 05:31:33 PM PDT 24
Peak memory 260612 kb
Host smart-910520db-8575-4248-8803-0e7b1e9ba9f8
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553652295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.553652295
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.454378523
Short name T625
Test name
Test status
Simulation time 29687100 ps
CPU time 13.56 seconds
Started Jul 22 05:30:24 PM PDT 24
Finished Jul 22 05:30:38 PM PDT 24
Peak memory 259852 kb
Host smart-a0d7ea31-3cf8-4b70-9bfa-f95158e92d1f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454378523 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.454378523
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.2467471758
Short name T566
Test name
Test status
Simulation time 21938018900 ps
CPU time 186.09 seconds
Started Jul 22 05:30:05 PM PDT 24
Finished Jul 22 05:33:11 PM PDT 24
Peak memory 265304 kb
Host smart-1f027340-971c-482e-8ab6-b612ebdd10dd
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467471758 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.2467471758
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.3098050037
Short name T994
Test name
Test status
Simulation time 26414600 ps
CPU time 65.85 seconds
Started Jul 22 05:30:04 PM PDT 24
Finished Jul 22 05:31:11 PM PDT 24
Peak memory 263176 kb
Host smart-86a1cbfa-c22a-4e8b-913d-429a6c159f43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3098050037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.3098050037
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.1349903122
Short name T182
Test name
Test status
Simulation time 21513000 ps
CPU time 13.56 seconds
Started Jul 22 05:30:13 PM PDT 24
Finished Jul 22 05:30:27 PM PDT 24
Peak memory 259076 kb
Host smart-e75748c0-1d84-4728-8cad-0ab86cbe919f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349903122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.flash_ctrl_prog_reset.1349903122
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.600907832
Short name T654
Test name
Test status
Simulation time 155584600 ps
CPU time 315.65 seconds
Started Jul 22 05:30:21 PM PDT 24
Finished Jul 22 05:35:37 PM PDT 24
Peak memory 274172 kb
Host smart-bc99a231-081a-4b69-9c47-60f6dbfe2bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600907832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.600907832
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.2869413360
Short name T730
Test name
Test status
Simulation time 6068176000 ps
CPU time 116.58 seconds
Started Jul 22 05:31:02 PM PDT 24
Finished Jul 22 05:32:59 PM PDT 24
Peak memory 281760 kb
Host smart-b5249544-917b-4fea-b535-e6bcb8a8e8fb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869413360 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.flash_ctrl_ro.2869413360
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.3994963577
Short name T922
Test name
Test status
Simulation time 9499938400 ps
CPU time 645.7 seconds
Started Jul 22 05:30:12 PM PDT 24
Finished Jul 22 05:40:58 PM PDT 24
Peak memory 314620 kb
Host smart-b5e1c673-a2a5-45db-8b3c-93aa54091121
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994963577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.flash_ctrl_rw.3994963577
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.488103965
Short name T1071
Test name
Test status
Simulation time 26697700 ps
CPU time 31.08 seconds
Started Jul 22 05:30:14 PM PDT 24
Finished Jul 22 05:30:45 PM PDT 24
Peak memory 275588 kb
Host smart-e07d9d41-d485-4b4e-9611-88e981bfb73c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488103965 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.488103965
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.3368574757
Short name T987
Test name
Test status
Simulation time 26891700 ps
CPU time 120.39 seconds
Started Jul 22 05:30:10 PM PDT 24
Finished Jul 22 05:32:11 PM PDT 24
Peak memory 268708 kb
Host smart-2441d401-3eed-446e-9162-95f83ef7ff4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368574757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.3368574757
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.903143226
Short name T941
Test name
Test status
Simulation time 4819584900 ps
CPU time 193.45 seconds
Started Jul 22 05:30:13 PM PDT 24
Finished Jul 22 05:33:27 PM PDT 24
Peak memory 265220 kb
Host smart-e07c7419-2bb0-4755-af6f-985c015ef2d8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903143226 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.flash_ctrl_wo.903143226
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.1086586937
Short name T311
Test name
Test status
Simulation time 71681400 ps
CPU time 13.68 seconds
Started Jul 22 05:30:37 PM PDT 24
Finished Jul 22 05:30:52 PM PDT 24
Peak memory 258616 kb
Host smart-a3af27b5-c162-40e0-b084-2c67ff9d120b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086586937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
1086586937
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.3735482843
Short name T816
Test name
Test status
Simulation time 13626500 ps
CPU time 15.99 seconds
Started Jul 22 05:30:38 PM PDT 24
Finished Jul 22 05:30:55 PM PDT 24
Peak memory 274976 kb
Host smart-cc4e7c5e-32f9-4b39-82fd-2f668666cebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735482843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.3735482843
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.1686199922
Short name T1014
Test name
Test status
Simulation time 19531800 ps
CPU time 21.12 seconds
Started Jul 22 05:30:36 PM PDT 24
Finished Jul 22 05:30:58 PM PDT 24
Peak memory 273624 kb
Host smart-d66f2e08-157c-4dec-9856-47ee8133c9b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686199922 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.1686199922
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2426802572
Short name T190
Test name
Test status
Simulation time 10020024400 ps
CPU time 99.91 seconds
Started Jul 22 05:30:36 PM PDT 24
Finished Jul 22 05:32:17 PM PDT 24
Peak memory 332296 kb
Host smart-1ad5d2e3-5923-40fd-980c-615788442cdb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426802572 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.2426802572
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.1085532136
Short name T783
Test name
Test status
Simulation time 17301300 ps
CPU time 13.65 seconds
Started Jul 22 05:30:37 PM PDT 24
Finished Jul 22 05:30:52 PM PDT 24
Peak memory 260188 kb
Host smart-f6a1e3c9-4cb6-47ad-b0d5-f356281aeb0c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085532136 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.1085532136
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.123604880
Short name T107
Test name
Test status
Simulation time 40125536400 ps
CPU time 869.48 seconds
Started Jul 22 05:30:28 PM PDT 24
Finished Jul 22 05:44:58 PM PDT 24
Peak memory 260984 kb
Host smart-38bd4d90-af9b-4b3f-b263-11f2c65c5c27
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123604880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.flash_ctrl_hw_rma_reset.123604880
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.3151993483
Short name T638
Test name
Test status
Simulation time 4391073800 ps
CPU time 55.51 seconds
Started Jul 22 05:30:30 PM PDT 24
Finished Jul 22 05:31:26 PM PDT 24
Peak memory 260928 kb
Host smart-c2ac5d86-620f-41cc-8c39-3af376c6a550
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151993483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.3151993483
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.2612520109
Short name T336
Test name
Test status
Simulation time 10481819400 ps
CPU time 165.3 seconds
Started Jul 22 05:30:40 PM PDT 24
Finished Jul 22 05:33:26 PM PDT 24
Peak memory 294276 kb
Host smart-55f264f5-991f-475e-969a-46b524d85d62
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612520109 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.2612520109
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.101967087
Short name T829
Test name
Test status
Simulation time 996142400 ps
CPU time 79.55 seconds
Started Jul 22 05:30:29 PM PDT 24
Finished Jul 22 05:31:49 PM PDT 24
Peak memory 263376 kb
Host smart-b355cf3e-90fc-4a3f-8698-2210991a7d75
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101967087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.101967087
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.2720121873
Short name T1058
Test name
Test status
Simulation time 33477200 ps
CPU time 13.63 seconds
Started Jul 22 05:30:36 PM PDT 24
Finished Jul 22 05:30:50 PM PDT 24
Peak memory 265028 kb
Host smart-9aba8926-2936-460d-9ad4-4c1af3cfcaab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720121873 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.2720121873
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.1604771557
Short name T136
Test name
Test status
Simulation time 173584914000 ps
CPU time 340.81 seconds
Started Jul 22 05:30:30 PM PDT 24
Finished Jul 22 05:36:11 PM PDT 24
Peak memory 274628 kb
Host smart-b7a8a9ef-8cbc-4a8a-9cc7-497acd684ec4
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604771557 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.1604771557
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.2387531880
Short name T73
Test name
Test status
Simulation time 66486800 ps
CPU time 132.23 seconds
Started Jul 22 05:30:30 PM PDT 24
Finished Jul 22 05:32:43 PM PDT 24
Peak memory 264736 kb
Host smart-68047ef1-9149-4b1b-ab9b-077d6214dc3f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387531880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.2387531880
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.3972737255
Short name T616
Test name
Test status
Simulation time 337251400 ps
CPU time 394.16 seconds
Started Jul 22 05:30:31 PM PDT 24
Finished Jul 22 05:37:06 PM PDT 24
Peak memory 263124 kb
Host smart-bf0d8412-9d36-4a01-9ca8-30898ef8cdd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3972737255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.3972737255
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.1724479312
Short name T843
Test name
Test status
Simulation time 1966617500 ps
CPU time 145.59 seconds
Started Jul 22 05:30:39 PM PDT 24
Finished Jul 22 05:33:05 PM PDT 24
Peak memory 259988 kb
Host smart-1d8e475c-706e-4a10-acfa-d9210120d809
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724479312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.flash_ctrl_prog_reset.1724479312
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.1860838951
Short name T1095
Test name
Test status
Simulation time 187864400 ps
CPU time 875.48 seconds
Started Jul 22 05:30:29 PM PDT 24
Finished Jul 22 05:45:06 PM PDT 24
Peak memory 287140 kb
Host smart-0b62ea55-86ba-48f2-9555-1b0594d7778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860838951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.1860838951
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.2196078395
Short name T837
Test name
Test status
Simulation time 113643900 ps
CPU time 35.96 seconds
Started Jul 22 05:30:40 PM PDT 24
Finished Jul 22 05:31:16 PM PDT 24
Peak memory 275668 kb
Host smart-6071e1b3-6f59-44da-b4f7-306942279abe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196078395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.2196078395
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.1104509586
Short name T505
Test name
Test status
Simulation time 62285400 ps
CPU time 30.68 seconds
Started Jul 22 05:30:37 PM PDT 24
Finished Jul 22 05:31:09 PM PDT 24
Peak memory 273900 kb
Host smart-fb031eb2-4e83-47a0-a364-d163167e9295
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104509586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_rw_evict.1104509586
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.1742572662
Short name T704
Test name
Test status
Simulation time 190830800 ps
CPU time 30.63 seconds
Started Jul 22 05:30:37 PM PDT 24
Finished Jul 22 05:31:09 PM PDT 24
Peak memory 268500 kb
Host smart-cc4b47db-66a9-479b-9af8-f9ceeac0ca10
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742572662 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.1742572662
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.1900439784
Short name T970
Test name
Test status
Simulation time 7203035000 ps
CPU time 79.69 seconds
Started Jul 22 05:30:37 PM PDT 24
Finished Jul 22 05:31:58 PM PDT 24
Peak memory 263740 kb
Host smart-c427fb8c-82f6-405a-8ed4-a995ff214756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900439784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.1900439784
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.2715090703
Short name T799
Test name
Test status
Simulation time 31849200 ps
CPU time 120.6 seconds
Started Jul 22 05:30:30 PM PDT 24
Finished Jul 22 05:32:31 PM PDT 24
Peak memory 276264 kb
Host smart-ad1a7743-8b6f-47fa-a016-dd76f2c792f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715090703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2715090703
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.2888912109
Short name T571
Test name
Test status
Simulation time 3223041000 ps
CPU time 220.45 seconds
Started Jul 22 05:30:31 PM PDT 24
Finished Jul 22 05:34:12 PM PDT 24
Peak memory 265328 kb
Host smart-0e033417-f617-4554-9caf-fa18bddebf24
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888912109 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.flash_ctrl_wo.2888912109
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.3471274021
Short name T668
Test name
Test status
Simulation time 270466300 ps
CPU time 13.52 seconds
Started Jul 22 05:30:54 PM PDT 24
Finished Jul 22 05:31:08 PM PDT 24
Peak memory 258324 kb
Host smart-be5040f2-fffa-4e6f-aabf-53ade1ed7e40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471274021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
3471274021
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.7549663
Short name T110
Test name
Test status
Simulation time 23274500 ps
CPU time 16.21 seconds
Started Jul 22 05:30:55 PM PDT 24
Finished Jul 22 05:31:12 PM PDT 24
Peak memory 274796 kb
Host smart-bb8008ac-b402-4e1c-b36c-5d122a0c43f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7549663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.7549663
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.572564322
Short name T1028
Test name
Test status
Simulation time 12709600 ps
CPU time 20.72 seconds
Started Jul 22 05:30:44 PM PDT 24
Finished Jul 22 05:31:05 PM PDT 24
Peak memory 273580 kb
Host smart-3bec8e3d-80bc-4256-b071-b24b68dbfaae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572564322 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.572564322
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.3551574455
Short name T178
Test name
Test status
Simulation time 18456300 ps
CPU time 13.65 seconds
Started Jul 22 05:30:53 PM PDT 24
Finished Jul 22 05:31:07 PM PDT 24
Peak memory 258416 kb
Host smart-6ab7d2e0-3750-4802-92c4-9a7f27b89dee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551574455 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3551574455
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.863944103
Short name T108
Test name
Test status
Simulation time 170196426000 ps
CPU time 1024.51 seconds
Started Jul 22 05:30:37 PM PDT 24
Finished Jul 22 05:47:42 PM PDT 24
Peak memory 264020 kb
Host smart-36f3a86d-2aaf-4c51-9d7f-9c4c05c80141
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863944103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.flash_ctrl_hw_rma_reset.863944103
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.3808628420
Short name T674
Test name
Test status
Simulation time 4149457600 ps
CPU time 102.34 seconds
Started Jul 22 05:30:37 PM PDT 24
Finished Jul 22 05:32:21 PM PDT 24
Peak memory 263320 kb
Host smart-6af80eed-ee41-433a-bed1-639610d1a38a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808628420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.3808628420
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.42248302
Short name T622
Test name
Test status
Simulation time 8231375700 ps
CPU time 193.16 seconds
Started Jul 22 05:30:47 PM PDT 24
Finished Jul 22 05:34:00 PM PDT 24
Peak memory 284876 kb
Host smart-6f89e60f-7b76-4c8f-9062-86132a002145
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42248302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash
_ctrl_intr_rd.42248302
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.4195729823
Short name T934
Test name
Test status
Simulation time 22770334200 ps
CPU time 248.85 seconds
Started Jul 22 05:30:44 PM PDT 24
Finished Jul 22 05:34:53 PM PDT 24
Peak memory 290988 kb
Host smart-e6f58e50-5748-4a8f-9998-a00639815b1e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195729823 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.4195729823
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.3421775265
Short name T683
Test name
Test status
Simulation time 6982640800 ps
CPU time 93.71 seconds
Started Jul 22 05:30:46 PM PDT 24
Finished Jul 22 05:32:20 PM PDT 24
Peak memory 260804 kb
Host smart-ec2d8ccc-078d-4eaa-b939-82565c797775
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421775265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3
421775265
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.3680253791
Short name T952
Test name
Test status
Simulation time 72338300 ps
CPU time 13.97 seconds
Started Jul 22 05:30:49 PM PDT 24
Finished Jul 22 05:31:04 PM PDT 24
Peak memory 260012 kb
Host smart-a54fd5ff-a189-4789-9862-ed6473a64ebf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680253791 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.3680253791
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.1873144630
Short name T590
Test name
Test status
Simulation time 19487343900 ps
CPU time 149.8 seconds
Started Jul 22 05:30:45 PM PDT 24
Finished Jul 22 05:33:15 PM PDT 24
Peak memory 265232 kb
Host smart-7d6bb605-a0a5-40cf-9488-0078ea906b6e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873144630 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.1873144630
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.1390247296
Short name T739
Test name
Test status
Simulation time 192809000 ps
CPU time 133.84 seconds
Started Jul 22 05:30:46 PM PDT 24
Finished Jul 22 05:33:00 PM PDT 24
Peak memory 260228 kb
Host smart-52e34b54-e5be-4e89-b261-7037a8912d00
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390247296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.1390247296
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.3375958789
Short name T608
Test name
Test status
Simulation time 111987900 ps
CPU time 152.38 seconds
Started Jul 22 05:30:39 PM PDT 24
Finished Jul 22 05:33:12 PM PDT 24
Peak memory 263172 kb
Host smart-cd555175-6349-47cb-a7f8-e100c0f62570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3375958789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.3375958789
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.3357689905
Short name T546
Test name
Test status
Simulation time 78530900 ps
CPU time 13.48 seconds
Started Jul 22 05:30:44 PM PDT 24
Finished Jul 22 05:30:58 PM PDT 24
Peak memory 265300 kb
Host smart-f566306b-0a08-4c10-89cc-25b498cc8f0a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357689905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.flash_ctrl_prog_reset.3357689905
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.2730602497
Short name T761
Test name
Test status
Simulation time 131559700 ps
CPU time 501.47 seconds
Started Jul 22 05:30:39 PM PDT 24
Finished Jul 22 05:39:02 PM PDT 24
Peak memory 284248 kb
Host smart-2b12d1d1-e9de-4707-a11b-c1f0eeba4d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730602497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.2730602497
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.1155445264
Short name T929
Test name
Test status
Simulation time 145848800 ps
CPU time 34.98 seconds
Started Jul 22 05:30:45 PM PDT 24
Finished Jul 22 05:31:21 PM PDT 24
Peak memory 273620 kb
Host smart-245793e9-9004-4853-a31e-ed726836bc0d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155445264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.1155445264
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.3114102971
Short name T521
Test name
Test status
Simulation time 868996600 ps
CPU time 95.67 seconds
Started Jul 22 05:31:03 PM PDT 24
Finished Jul 22 05:32:39 PM PDT 24
Peak memory 281732 kb
Host smart-3968c0c4-6ebc-4938-bf8c-9de666e9a5f3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114102971 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.flash_ctrl_ro.3114102971
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.1001142645
Short name T450
Test name
Test status
Simulation time 3343721200 ps
CPU time 642.46 seconds
Started Jul 22 05:30:45 PM PDT 24
Finished Jul 22 05:41:28 PM PDT 24
Peak memory 314180 kb
Host smart-9b852fb6-69ed-4ca7-bb48-dced75cdea4c
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001142645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.flash_ctrl_rw.1001142645
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.3455968710
Short name T149
Test name
Test status
Simulation time 191674600 ps
CPU time 32.05 seconds
Started Jul 22 05:30:49 PM PDT 24
Finished Jul 22 05:31:22 PM PDT 24
Peak memory 275640 kb
Host smart-ef4eed1b-b1dd-4bf2-8fe4-15809b06a063
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455968710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_rw_evict.3455968710
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.569772725
Short name T884
Test name
Test status
Simulation time 30376600 ps
CPU time 31.43 seconds
Started Jul 22 05:30:44 PM PDT 24
Finished Jul 22 05:31:16 PM PDT 24
Peak memory 268420 kb
Host smart-f4189781-cc0a-4175-a442-d93727a239c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569772725 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.569772725
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.2146080569
Short name T1066
Test name
Test status
Simulation time 75157000 ps
CPU time 76.84 seconds
Started Jul 22 05:30:37 PM PDT 24
Finished Jul 22 05:31:55 PM PDT 24
Peak memory 275552 kb
Host smart-cbdf4942-deb1-4398-83f9-483e03edd055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146080569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.2146080569
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.1422632668
Short name T937
Test name
Test status
Simulation time 7526113900 ps
CPU time 168.25 seconds
Started Jul 22 05:30:45 PM PDT 24
Finished Jul 22 05:33:34 PM PDT 24
Peak memory 265200 kb
Host smart-8ca69def-1882-4fda-9932-240c40651df0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422632668 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.flash_ctrl_wo.1422632668
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.3938864439
Short name T936
Test name
Test status
Simulation time 112646900 ps
CPU time 13.58 seconds
Started Jul 22 05:31:07 PM PDT 24
Finished Jul 22 05:31:21 PM PDT 24
Peak memory 258300 kb
Host smart-1ac67274-a98c-445c-b6b0-263b59838be1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938864439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
3938864439
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.197235463
Short name T810
Test name
Test status
Simulation time 20776300 ps
CPU time 15.38 seconds
Started Jul 22 05:31:54 PM PDT 24
Finished Jul 22 05:32:10 PM PDT 24
Peak memory 284428 kb
Host smart-3361a487-bed9-4fc7-8f6e-5fcc4842736a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197235463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.197235463
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.1291051944
Short name T885
Test name
Test status
Simulation time 10970100 ps
CPU time 22.07 seconds
Started Jul 22 05:31:01 PM PDT 24
Finished Jul 22 05:31:24 PM PDT 24
Peak memory 273216 kb
Host smart-5f63fc66-3a58-458b-be48-4ca96daca62b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291051944 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.1291051944
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.3430269860
Short name T82
Test name
Test status
Simulation time 10011809100 ps
CPU time 320.94 seconds
Started Jul 22 05:31:08 PM PDT 24
Finished Jul 22 05:36:30 PM PDT 24
Peak memory 317356 kb
Host smart-df633737-ef7e-4273-a991-d9286a5560a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430269860 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.3430269860
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.1048354660
Short name T930
Test name
Test status
Simulation time 26033000 ps
CPU time 13.57 seconds
Started Jul 22 05:31:08 PM PDT 24
Finished Jul 22 05:31:22 PM PDT 24
Peak memory 265088 kb
Host smart-1640d568-3bae-48db-898e-c17f1426d5ec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048354660 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.1048354660
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.4202577386
Short name T793
Test name
Test status
Simulation time 80154418200 ps
CPU time 946.59 seconds
Started Jul 22 05:30:52 PM PDT 24
Finished Jul 22 05:46:39 PM PDT 24
Peak memory 262192 kb
Host smart-6db91272-5c27-4151-a17e-f050986bea9b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202577386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.4202577386
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.172085880
Short name T436
Test name
Test status
Simulation time 3907549700 ps
CPU time 151.99 seconds
Started Jul 22 05:30:51 PM PDT 24
Finished Jul 22 05:33:23 PM PDT 24
Peak memory 261448 kb
Host smart-54251049-90d6-4f3c-a50e-55e8e39498fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172085880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_h
w_sec_otp.172085880
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.3216890395
Short name T883
Test name
Test status
Simulation time 2697365400 ps
CPU time 147.63 seconds
Started Jul 22 05:30:59 PM PDT 24
Finished Jul 22 05:33:27 PM PDT 24
Peak memory 293060 kb
Host smart-87bafe44-c824-4988-b739-1239fcaff0b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216890395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.3216890395
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3834239680
Short name T1030
Test name
Test status
Simulation time 11484573600 ps
CPU time 161.56 seconds
Started Jul 22 05:31:03 PM PDT 24
Finished Jul 22 05:33:45 PM PDT 24
Peak memory 292704 kb
Host smart-ec61998b-d3a2-431f-a431-f39fc7a7155e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834239680 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.3834239680
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.350783125
Short name T347
Test name
Test status
Simulation time 4801181200 ps
CPU time 71.45 seconds
Started Jul 22 05:30:52 PM PDT 24
Finished Jul 22 05:32:04 PM PDT 24
Peak memory 262804 kb
Host smart-88950695-9b1a-4be5-84e9-b6b23e813c43
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350783125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.350783125
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.3107135067
Short name T235
Test name
Test status
Simulation time 27707852000 ps
CPU time 177.83 seconds
Started Jul 22 05:30:53 PM PDT 24
Finished Jul 22 05:33:51 PM PDT 24
Peak memory 263452 kb
Host smart-fca8e840-d523-4687-924a-47c05f9212af
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107135067 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.3107135067
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.3895945297
Short name T469
Test name
Test status
Simulation time 35871700 ps
CPU time 129.95 seconds
Started Jul 22 05:30:52 PM PDT 24
Finished Jul 22 05:33:02 PM PDT 24
Peak memory 264556 kb
Host smart-b465bdd7-bb5b-4fd9-8c6b-690cf41a5c1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895945297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.3895945297
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.978937849
Short name T646
Test name
Test status
Simulation time 1362724500 ps
CPU time 175.98 seconds
Started Jul 22 05:31:00 PM PDT 24
Finished Jul 22 05:33:56 PM PDT 24
Peak memory 263124 kb
Host smart-c1b1f892-c4d6-498c-ab8f-54ebb1c3e1ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=978937849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.978937849
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.655551737
Short name T527
Test name
Test status
Simulation time 22997100 ps
CPU time 13.74 seconds
Started Jul 22 05:30:59 PM PDT 24
Finished Jul 22 05:31:14 PM PDT 24
Peak memory 265408 kb
Host smart-ca5c43d0-17a2-44d1-b6b8-d8dd0970b9df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655551737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.flash_ctrl_prog_reset.655551737
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.353439798
Short name T744
Test name
Test status
Simulation time 2813053000 ps
CPU time 327.68 seconds
Started Jul 22 05:30:54 PM PDT 24
Finished Jul 22 05:36:22 PM PDT 24
Peak memory 281636 kb
Host smart-c4228828-17b9-4ff9-af3c-ecce630ec99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353439798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.353439798
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.3014514130
Short name T553
Test name
Test status
Simulation time 279103900 ps
CPU time 34.38 seconds
Started Jul 22 05:31:00 PM PDT 24
Finished Jul 22 05:31:35 PM PDT 24
Peak memory 275612 kb
Host smart-32cb55d8-09f4-4e3f-91e2-54efae1a8d34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014514130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.3014514130
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.43259824
Short name T767
Test name
Test status
Simulation time 2148587700 ps
CPU time 129.95 seconds
Started Jul 22 05:31:00 PM PDT 24
Finished Jul 22 05:33:10 PM PDT 24
Peak memory 290004 kb
Host smart-18a02430-986f-40fd-bd66-cc659667a79d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43259824 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.flash_ctrl_ro.43259824
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.3386407389
Short name T780
Test name
Test status
Simulation time 81638101700 ps
CPU time 691.17 seconds
Started Jul 22 05:30:58 PM PDT 24
Finished Jul 22 05:42:30 PM PDT 24
Peak memory 314376 kb
Host smart-8f3c4c94-2f64-42a7-b334-9f6742682daf
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386407389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_rw.3386407389
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.1738730064
Short name T461
Test name
Test status
Simulation time 46313700 ps
CPU time 28.78 seconds
Started Jul 22 05:30:57 PM PDT 24
Finished Jul 22 05:31:26 PM PDT 24
Peak memory 267512 kb
Host smart-8e18c487-df05-4111-b16c-f9932f2b6913
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738730064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.1738730064
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.3576612756
Short name T996
Test name
Test status
Simulation time 30097400 ps
CPU time 31.41 seconds
Started Jul 22 05:31:00 PM PDT 24
Finished Jul 22 05:31:31 PM PDT 24
Peak memory 268380 kb
Host smart-91827fe3-a8d3-4eb9-ba9a-1ce0d9482ddd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576612756 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.3576612756
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.741922011
Short name T387
Test name
Test status
Simulation time 121692800 ps
CPU time 218.54 seconds
Started Jul 22 05:30:51 PM PDT 24
Finished Jul 22 05:34:30 PM PDT 24
Peak memory 281644 kb
Host smart-2e11d239-6b95-4a29-aea4-ecef7a9a4fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741922011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.741922011
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.278955984
Short name T1
Test name
Test status
Simulation time 4666483100 ps
CPU time 201.19 seconds
Started Jul 22 05:31:00 PM PDT 24
Finished Jul 22 05:34:21 PM PDT 24
Peak memory 259520 kb
Host smart-c2bf0943-76d8-442d-b123-27dac5a0e868
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278955984 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.flash_ctrl_wo.278955984
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.1078227896
Short name T1011
Test name
Test status
Simulation time 28446300 ps
CPU time 13.87 seconds
Started Jul 22 05:31:25 PM PDT 24
Finished Jul 22 05:31:39 PM PDT 24
Peak memory 258384 kb
Host smart-72c397b8-e548-4957-aab9-282268c583ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078227896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
1078227896
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.3551018255
Short name T933
Test name
Test status
Simulation time 65421700 ps
CPU time 13.48 seconds
Started Jul 22 05:31:23 PM PDT 24
Finished Jul 22 05:31:37 PM PDT 24
Peak memory 274900 kb
Host smart-4ce68120-e914-46b0-9f97-e4d5e009e324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551018255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.3551018255
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.2641483483
Short name T919
Test name
Test status
Simulation time 3370972800 ps
CPU time 135.45 seconds
Started Jul 22 05:31:09 PM PDT 24
Finished Jul 22 05:33:25 PM PDT 24
Peak memory 260672 kb
Host smart-c857fa37-acff-4b7c-8351-fab42bcc02fb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641483483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.2641483483
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.591390999
Short name T685
Test name
Test status
Simulation time 3760253600 ps
CPU time 235.12 seconds
Started Jul 22 05:31:13 PM PDT 24
Finished Jul 22 05:35:09 PM PDT 24
Peak memory 284936 kb
Host smart-6dc177b3-2923-45cc-a601-0d603bfd5e74
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591390999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flas
h_ctrl_intr_rd.591390999
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.2635504995
Short name T463
Test name
Test status
Simulation time 23262492100 ps
CPU time 306.65 seconds
Started Jul 22 05:31:15 PM PDT 24
Finished Jul 22 05:36:22 PM PDT 24
Peak memory 291568 kb
Host smart-183b20a6-0107-4a12-9920-b628c85f6912
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635504995 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.2635504995
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.4055072596
Short name T525
Test name
Test status
Simulation time 6505658200 ps
CPU time 75.6 seconds
Started Jul 22 05:31:10 PM PDT 24
Finished Jul 22 05:32:26 PM PDT 24
Peak memory 263508 kb
Host smart-49a7cc1e-88ae-40de-958a-6357ad5a74b6
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055072596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.4
055072596
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.3492470822
Short name T655
Test name
Test status
Simulation time 48190100 ps
CPU time 13.64 seconds
Started Jul 22 05:31:24 PM PDT 24
Finished Jul 22 05:31:38 PM PDT 24
Peak memory 260836 kb
Host smart-48b4f5ea-bdbe-4ecf-97c4-328d1bdc2eb7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492470822 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.3492470822
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.4255356214
Short name T132
Test name
Test status
Simulation time 26603393100 ps
CPU time 1132.12 seconds
Started Jul 22 05:31:15 PM PDT 24
Finished Jul 22 05:50:08 PM PDT 24
Peak memory 274900 kb
Host smart-c27d7f9b-9ad2-4be9-be81-109e0fdb7355
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255356214 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.4255356214
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.3733737850
Short name T997
Test name
Test status
Simulation time 44167600 ps
CPU time 130.17 seconds
Started Jul 22 05:31:10 PM PDT 24
Finished Jul 22 05:33:21 PM PDT 24
Peak memory 263168 kb
Host smart-7ad1fc8d-1a4b-4627-a667-47837644917d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733737850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.3733737850
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.4075041778
Short name T236
Test name
Test status
Simulation time 745101200 ps
CPU time 347.01 seconds
Started Jul 22 05:31:11 PM PDT 24
Finished Jul 22 05:36:59 PM PDT 24
Peak memory 263112 kb
Host smart-99bf854a-39c1-4938-bc87-adb4c9ada339
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4075041778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.4075041778
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.2971883499
Short name T550
Test name
Test status
Simulation time 142814500 ps
CPU time 14.01 seconds
Started Jul 22 05:34:22 PM PDT 24
Finished Jul 22 05:34:37 PM PDT 24
Peak memory 258776 kb
Host smart-2ee24d73-326c-4398-8711-56398b968949
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971883499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.flash_ctrl_prog_reset.2971883499
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.3026051465
Short name T581
Test name
Test status
Simulation time 748882300 ps
CPU time 432.61 seconds
Started Jul 22 05:31:09 PM PDT 24
Finished Jul 22 05:38:22 PM PDT 24
Peak memory 282668 kb
Host smart-4de87863-875b-4716-849d-db4b7dfed42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026051465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.3026051465
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.2106152855
Short name T892
Test name
Test status
Simulation time 78393700 ps
CPU time 30.76 seconds
Started Jul 22 05:34:22 PM PDT 24
Finished Jul 22 05:34:54 PM PDT 24
Peak memory 273128 kb
Host smart-3f01e5e7-81a8-489d-b441-bbebace9097c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106152855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.2106152855
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.2132100703
Short name T564
Test name
Test status
Simulation time 430847500 ps
CPU time 119.2 seconds
Started Jul 22 05:31:17 PM PDT 24
Finished Jul 22 05:33:16 PM PDT 24
Peak memory 281804 kb
Host smart-54faba83-fa9d-4398-bd03-13f568812a05
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132100703 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.flash_ctrl_ro.2132100703
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.187914423
Short name T480
Test name
Test status
Simulation time 3428950300 ps
CPU time 540.92 seconds
Started Jul 22 05:31:15 PM PDT 24
Finished Jul 22 05:40:16 PM PDT 24
Peak memory 318980 kb
Host smart-b6cd6787-77ef-45b4-940d-6e829a864db0
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187914423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.flash_ctrl_rw.187914423
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.956210073
Short name T40
Test name
Test status
Simulation time 44126900 ps
CPU time 30.56 seconds
Started Jul 22 05:34:23 PM PDT 24
Finished Jul 22 05:34:53 PM PDT 24
Peak memory 275360 kb
Host smart-6825a04c-f6da-49db-a512-3f8c94fc8f1c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956210073 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.956210073
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.3574434565
Short name T417
Test name
Test status
Simulation time 2281533700 ps
CPU time 67.68 seconds
Started Jul 22 05:31:23 PM PDT 24
Finished Jul 22 05:32:31 PM PDT 24
Peak memory 263788 kb
Host smart-cb93ca32-b406-44df-b6fb-7c2299451c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574434565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.3574434565
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.3361579101
Short name T865
Test name
Test status
Simulation time 50107800 ps
CPU time 170.52 seconds
Started Jul 22 05:31:10 PM PDT 24
Finished Jul 22 05:34:01 PM PDT 24
Peak memory 277188 kb
Host smart-fcad002a-8972-4acc-8731-f6e1383b4ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361579101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.3361579101
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.834602789
Short name T645
Test name
Test status
Simulation time 2598167400 ps
CPU time 205.91 seconds
Started Jul 22 05:31:14 PM PDT 24
Finished Jul 22 05:34:40 PM PDT 24
Peak memory 259592 kb
Host smart-1629752a-df98-415f-9645-7a49dee31f81
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834602789 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.flash_ctrl_wo.834602789
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.3778067146
Short name T94
Test name
Test status
Simulation time 40307600 ps
CPU time 13.63 seconds
Started Jul 22 05:31:37 PM PDT 24
Finished Jul 22 05:31:51 PM PDT 24
Peak memory 258384 kb
Host smart-0f228aca-8de5-48e8-8f6b-d7a4741d38cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778067146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
3778067146
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.615137404
Short name T985
Test name
Test status
Simulation time 82834800 ps
CPU time 15.48 seconds
Started Jul 22 05:31:38 PM PDT 24
Finished Jul 22 05:31:54 PM PDT 24
Peak memory 274868 kb
Host smart-e8667e26-360f-455c-9c0b-271732db48aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615137404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.615137404
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.634852490
Short name T202
Test name
Test status
Simulation time 51260800 ps
CPU time 21.49 seconds
Started Jul 22 05:31:29 PM PDT 24
Finished Jul 22 05:31:51 PM PDT 24
Peak memory 273676 kb
Host smart-5a3ba163-d153-46be-9459-04d2f8075150
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634852490 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.634852490
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2002035409
Short name T874
Test name
Test status
Simulation time 10107247000 ps
CPU time 45.45 seconds
Started Jul 22 05:31:42 PM PDT 24
Finished Jul 22 05:32:28 PM PDT 24
Peak memory 265484 kb
Host smart-0b5774e7-f459-4c7b-a651-526eea98bd2c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002035409 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.2002035409
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.3757890687
Short name T291
Test name
Test status
Simulation time 28805200 ps
CPU time 13.58 seconds
Started Jul 22 05:31:40 PM PDT 24
Finished Jul 22 05:31:54 PM PDT 24
Peak memory 265132 kb
Host smart-6d1dc044-e05a-45a4-b905-8f1056c407ce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757890687 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.3757890687
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.2336194105
Short name T876
Test name
Test status
Simulation time 180167477300 ps
CPU time 802.76 seconds
Started Jul 22 05:31:29 PM PDT 24
Finished Jul 22 05:44:52 PM PDT 24
Peak memory 265032 kb
Host smart-c7d91334-e130-4a8d-b60f-066d194f6246
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336194105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.2336194105
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.1498930022
Short name T531
Test name
Test status
Simulation time 30126851200 ps
CPU time 108.53 seconds
Started Jul 22 05:31:21 PM PDT 24
Finished Jul 22 05:33:10 PM PDT 24
Peak memory 262728 kb
Host smart-3f6daaf5-0717-45cd-9c98-efd04c4839d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498930022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.1498930022
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.4111836506
Short name T657
Test name
Test status
Simulation time 2714018400 ps
CPU time 167.16 seconds
Started Jul 22 05:31:29 PM PDT 24
Finished Jul 22 05:34:17 PM PDT 24
Peak memory 294004 kb
Host smart-080f82e6-2abe-4e3e-a590-a9108bcd6b0d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111836506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_intr_rd.4111836506
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.2797612795
Short name T363
Test name
Test status
Simulation time 51981070900 ps
CPU time 321.71 seconds
Started Jul 22 05:31:31 PM PDT 24
Finished Jul 22 05:36:53 PM PDT 24
Peak memory 290920 kb
Host smart-d89540f1-3673-4d9f-bd83-f4bd62ec3f29
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797612795 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.2797612795
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.2641553379
Short name T342
Test name
Test status
Simulation time 6776677200 ps
CPU time 75.57 seconds
Started Jul 22 05:31:30 PM PDT 24
Finished Jul 22 05:32:46 PM PDT 24
Peak memory 262708 kb
Host smart-255aba3e-52fc-4be5-aff2-cbbf41c8ceb3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641553379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.2
641553379
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.452126275
Short name T932
Test name
Test status
Simulation time 28225300 ps
CPU time 13.5 seconds
Started Jul 22 05:31:39 PM PDT 24
Finished Jul 22 05:31:52 PM PDT 24
Peak memory 264896 kb
Host smart-858a28fe-36f4-4b3e-9b52-c9f9146666d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452126275 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.452126275
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.1592604822
Short name T153
Test name
Test status
Simulation time 18759608000 ps
CPU time 363.96 seconds
Started Jul 22 05:31:30 PM PDT 24
Finished Jul 22 05:37:34 PM PDT 24
Peak memory 274788 kb
Host smart-af8c2c5e-739b-4180-81bd-f8353e7df3d9
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592604822 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.1592604822
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.637107872
Short name T427
Test name
Test status
Simulation time 426398700 ps
CPU time 238.64 seconds
Started Jul 22 05:31:23 PM PDT 24
Finished Jul 22 05:35:22 PM PDT 24
Peak memory 263160 kb
Host smart-0d3ce742-a448-4329-896a-854ea9b07966
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=637107872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.637107872
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.2334067072
Short name T692
Test name
Test status
Simulation time 11195608400 ps
CPU time 179.42 seconds
Started Jul 22 05:31:30 PM PDT 24
Finished Jul 22 05:34:30 PM PDT 24
Peak memory 261652 kb
Host smart-9a7f2ec6-de72-4c50-a8e9-dd0462e52454
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334067072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.flash_ctrl_prog_reset.2334067072
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.1435151563
Short name T703
Test name
Test status
Simulation time 230125900 ps
CPU time 242.42 seconds
Started Jul 22 05:32:56 PM PDT 24
Finished Jul 22 05:36:59 PM PDT 24
Peak memory 281404 kb
Host smart-819524e2-084d-4da2-903f-4c3bba73b6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435151563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.1435151563
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.2870785755
Short name T286
Test name
Test status
Simulation time 172629600 ps
CPU time 30.74 seconds
Started Jul 22 05:31:30 PM PDT 24
Finished Jul 22 05:32:01 PM PDT 24
Peak memory 275676 kb
Host smart-eea0691b-1870-4484-86a8-b569ecfdeb54
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870785755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.2870785755
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.3541066104
Short name T514
Test name
Test status
Simulation time 2165040600 ps
CPU time 132.17 seconds
Started Jul 22 05:31:31 PM PDT 24
Finished Jul 22 05:33:44 PM PDT 24
Peak memory 280948 kb
Host smart-deb24f6b-1abe-4c55-bd16-40c4aad89a9f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541066104 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_ro.3541066104
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.2209684646
Short name T355
Test name
Test status
Simulation time 29529500 ps
CPU time 30.73 seconds
Started Jul 22 05:31:30 PM PDT 24
Finished Jul 22 05:32:01 PM PDT 24
Peak memory 268500 kb
Host smart-32fdb176-4c04-48a6-bbc7-8f384e3f5605
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209684646 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.2209684646
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.1890681497
Short name T411
Test name
Test status
Simulation time 3447047200 ps
CPU time 67.76 seconds
Started Jul 22 05:31:36 PM PDT 24
Finished Jul 22 05:32:44 PM PDT 24
Peak memory 263156 kb
Host smart-5ef25ea9-d968-407f-a415-652f83fef1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890681497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.1890681497
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.4082624959
Short name T617
Test name
Test status
Simulation time 87110200 ps
CPU time 148.32 seconds
Started Jul 22 05:31:23 PM PDT 24
Finished Jul 22 05:33:52 PM PDT 24
Peak memory 276916 kb
Host smart-ee700487-1070-4eda-bfea-7c5090525dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082624959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.4082624959
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.1281216942
Short name T222
Test name
Test status
Simulation time 3167672900 ps
CPU time 194.8 seconds
Started Jul 22 05:31:30 PM PDT 24
Finished Jul 22 05:34:45 PM PDT 24
Peak memory 265336 kb
Host smart-8ec24531-2e06-436a-8335-772d8cbf522d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281216942 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.flash_ctrl_wo.1281216942
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.1811827097
Short name T691
Test name
Test status
Simulation time 49040600 ps
CPU time 13.49 seconds
Started Jul 22 05:32:10 PM PDT 24
Finished Jul 22 05:32:24 PM PDT 24
Peak memory 258256 kb
Host smart-82c1cf66-8be7-4a5e-bedf-56577e194014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811827097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.
1811827097
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.754919046
Short name T162
Test name
Test status
Simulation time 24285800 ps
CPU time 15.6 seconds
Started Jul 22 05:34:48 PM PDT 24
Finished Jul 22 05:35:04 PM PDT 24
Peak memory 274836 kb
Host smart-b7d4a3d5-b78b-47c0-abc0-7c1771116e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754919046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.754919046
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.1276669316
Short name T76
Test name
Test status
Simulation time 16194100 ps
CPU time 22.79 seconds
Started Jul 22 05:31:47 PM PDT 24
Finished Jul 22 05:32:10 PM PDT 24
Peak memory 274904 kb
Host smart-9fa6adb8-b4b0-476e-b19d-1d88e83a928a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276669316 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.1276669316
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.507464292
Short name T81
Test name
Test status
Simulation time 10048811900 ps
CPU time 82.56 seconds
Started Jul 22 05:31:55 PM PDT 24
Finished Jul 22 05:33:18 PM PDT 24
Peak memory 267836 kb
Host smart-4cba0a7c-510e-423c-8236-cf784d706dbb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507464292 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.507464292
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.1914489646
Short name T292
Test name
Test status
Simulation time 15355600 ps
CPU time 13.77 seconds
Started Jul 22 05:31:57 PM PDT 24
Finished Jul 22 05:32:11 PM PDT 24
Peak memory 265148 kb
Host smart-f8212a8d-dd67-4d3a-8efc-2efc09078717
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914489646 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.1914489646
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.370183704
Short name T882
Test name
Test status
Simulation time 160168343400 ps
CPU time 982.83 seconds
Started Jul 22 05:31:38 PM PDT 24
Finished Jul 22 05:48:01 PM PDT 24
Peak memory 261016 kb
Host smart-5ffd9f75-026a-4f55-84ae-4944df8e3987
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370183704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.flash_ctrl_hw_rma_reset.370183704
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.1573478809
Short name T953
Test name
Test status
Simulation time 8596812700 ps
CPU time 149.9 seconds
Started Jul 22 05:34:30 PM PDT 24
Finished Jul 22 05:37:01 PM PDT 24
Peak memory 263252 kb
Host smart-d9473685-f9fa-4037-b241-3dbc03b108f5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573478809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.1573478809
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.4054665530
Short name T485
Test name
Test status
Simulation time 1634756000 ps
CPU time 204.89 seconds
Started Jul 22 05:31:58 PM PDT 24
Finished Jul 22 05:35:23 PM PDT 24
Peak memory 284968 kb
Host smart-f415964b-602b-484a-a358-7aadb086f156
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054665530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.4054665530
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.3920540774
Short name T949
Test name
Test status
Simulation time 15934300 ps
CPU time 13.26 seconds
Started Jul 22 05:31:48 PM PDT 24
Finished Jul 22 05:32:02 PM PDT 24
Peak memory 264988 kb
Host smart-5d475a36-3ed1-49be-a62a-218127b39d52
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920540774 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.3920540774
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.2280593128
Short name T155
Test name
Test status
Simulation time 6143850400 ps
CPU time 515.94 seconds
Started Jul 22 05:31:48 PM PDT 24
Finished Jul 22 05:40:25 PM PDT 24
Peak memory 274516 kb
Host smart-8049e9e5-f730-4ae1-a31c-d66501aa98e7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280593128 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.2280593128
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.784041573
Short name T199
Test name
Test status
Simulation time 36900600 ps
CPU time 130.71 seconds
Started Jul 22 05:31:40 PM PDT 24
Finished Jul 22 05:33:51 PM PDT 24
Peak memory 265184 kb
Host smart-39f00371-1561-4164-90ef-61f8025a209e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784041573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ot
p_reset.784041573
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.69876710
Short name T959
Test name
Test status
Simulation time 107592400 ps
CPU time 275.24 seconds
Started Jul 22 05:32:15 PM PDT 24
Finished Jul 22 05:36:51 PM PDT 24
Peak memory 262988 kb
Host smart-a5829a96-7762-418f-8859-1c62ed7016fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=69876710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.69876710
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.2529130760
Short name T995
Test name
Test status
Simulation time 2146073800 ps
CPU time 150.81 seconds
Started Jul 22 05:31:47 PM PDT 24
Finished Jul 22 05:34:19 PM PDT 24
Peak memory 265376 kb
Host smart-de57e259-1263-4d0d-bb92-85cff9ef562f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529130760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.flash_ctrl_prog_reset.2529130760
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.2778613833
Short name T543
Test name
Test status
Simulation time 210292800 ps
CPU time 390.66 seconds
Started Jul 22 05:31:42 PM PDT 24
Finished Jul 22 05:38:14 PM PDT 24
Peak memory 281636 kb
Host smart-db21449e-ae48-4abd-b633-39f5831bd2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778613833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.2778613833
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.146703891
Short name T345
Test name
Test status
Simulation time 241748900 ps
CPU time 35.08 seconds
Started Jul 22 05:31:47 PM PDT 24
Finished Jul 22 05:32:22 PM PDT 24
Peak memory 275616 kb
Host smart-e6c3e46e-fc3b-427c-9621-513b8bd7d126
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146703891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_re_evict.146703891
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.601631455
Short name T801
Test name
Test status
Simulation time 2509889200 ps
CPU time 154.43 seconds
Started Jul 22 05:31:46 PM PDT 24
Finished Jul 22 05:34:20 PM PDT 24
Peak memory 289924 kb
Host smart-f0ef797a-7151-4414-8fd0-4662351b8a18
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601631455 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.flash_ctrl_ro.601631455
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.3598430644
Short name T650
Test name
Test status
Simulation time 3892605800 ps
CPU time 652.12 seconds
Started Jul 22 05:31:49 PM PDT 24
Finished Jul 22 05:42:42 PM PDT 24
Peak memory 314148 kb
Host smart-d54b92e6-77c3-455c-8632-b3cd6a605f08
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598430644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.flash_ctrl_rw.3598430644
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.1138565634
Short name T726
Test name
Test status
Simulation time 29742500 ps
CPU time 31.33 seconds
Started Jul 22 05:31:46 PM PDT 24
Finished Jul 22 05:32:18 PM PDT 24
Peak memory 275708 kb
Host smart-a0b76962-44da-488d-9c16-5ce022134b08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138565634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_rw_evict.1138565634
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.888004633
Short name T356
Test name
Test status
Simulation time 127775200 ps
CPU time 28.99 seconds
Started Jul 22 05:31:48 PM PDT 24
Finished Jul 22 05:32:18 PM PDT 24
Peak memory 268380 kb
Host smart-8a53d3ea-c4ea-45bf-bee0-e9d5bcee3489
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888004633 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.888004633
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.90205705
Short name T567
Test name
Test status
Simulation time 368195200 ps
CPU time 125.66 seconds
Started Jul 22 05:31:39 PM PDT 24
Finished Jul 22 05:33:45 PM PDT 24
Peak memory 276612 kb
Host smart-b8028112-cba6-4e85-acd9-a6ebb9c676f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90205705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.90205705
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.2150943372
Short name T1061
Test name
Test status
Simulation time 2612942900 ps
CPU time 210.62 seconds
Started Jul 22 05:31:47 PM PDT 24
Finished Jul 22 05:35:18 PM PDT 24
Peak memory 265268 kb
Host smart-efb52079-bcd5-4222-8001-03d50b0ce51e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150943372 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.flash_ctrl_wo.2150943372
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.904107520
Short name T672
Test name
Test status
Simulation time 19813000 ps
CPU time 13.43 seconds
Started Jul 22 05:32:05 PM PDT 24
Finished Jul 22 05:32:19 PM PDT 24
Peak memory 258528 kb
Host smart-b45dda89-7edf-4a6c-88cc-88460ac73ec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904107520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.904107520
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.366169402
Short name T1017
Test name
Test status
Simulation time 23564100 ps
CPU time 15.99 seconds
Started Jul 22 05:32:08 PM PDT 24
Finished Jul 22 05:32:24 PM PDT 24
Peak memory 284420 kb
Host smart-51af709d-4927-4e51-a76a-b2ecfbd106ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366169402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.366169402
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.4053236074
Short name T382
Test name
Test status
Simulation time 27357800 ps
CPU time 22.37 seconds
Started Jul 22 05:32:07 PM PDT 24
Finished Jul 22 05:32:30 PM PDT 24
Peak memory 265548 kb
Host smart-98dc77cf-599b-486f-aabf-bb19f198a392
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053236074 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.4053236074
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.2640931228
Short name T804
Test name
Test status
Simulation time 10019058000 ps
CPU time 89.56 seconds
Started Jul 22 05:32:06 PM PDT 24
Finished Jul 22 05:33:37 PM PDT 24
Peak memory 331472 kb
Host smart-be50b965-7845-45ec-a205-8949956ed9f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640931228 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.2640931228
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.1369523928
Short name T604
Test name
Test status
Simulation time 18917300 ps
CPU time 13.55 seconds
Started Jul 22 05:32:07 PM PDT 24
Finished Jul 22 05:32:21 PM PDT 24
Peak memory 265012 kb
Host smart-bff23500-16d5-4a5a-b5c5-44734a513966
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369523928 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.1369523928
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.2711146802
Short name T1045
Test name
Test status
Simulation time 2656262700 ps
CPU time 238.24 seconds
Started Jul 22 05:31:57 PM PDT 24
Finished Jul 22 05:35:56 PM PDT 24
Peak memory 261248 kb
Host smart-abccab54-4c5d-492a-b8b8-4e7fc8ebe89b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711146802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.2711146802
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.733369865
Short name T904
Test name
Test status
Simulation time 32208881800 ps
CPU time 322.41 seconds
Started Jul 22 05:32:05 PM PDT 24
Finished Jul 22 05:37:28 PM PDT 24
Peak memory 290996 kb
Host smart-58a78fac-b239-4944-9942-a98783657d4b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733369865 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.733369865
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.1201347052
Short name T968
Test name
Test status
Simulation time 4360031300 ps
CPU time 72.34 seconds
Started Jul 22 05:31:56 PM PDT 24
Finished Jul 22 05:33:09 PM PDT 24
Peak memory 262800 kb
Host smart-28331b3b-7f93-4142-bebf-328e8f8084d1
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201347052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.1
201347052
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.2062038629
Short name T777
Test name
Test status
Simulation time 48647300 ps
CPU time 13.5 seconds
Started Jul 22 05:32:08 PM PDT 24
Finished Jul 22 05:32:22 PM PDT 24
Peak memory 259916 kb
Host smart-14b12938-4297-44d9-bf99-42e4bf171353
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062038629 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.2062038629
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.2367864148
Short name T135
Test name
Test status
Simulation time 18800952500 ps
CPU time 628.66 seconds
Started Jul 22 05:31:55 PM PDT 24
Finished Jul 22 05:42:24 PM PDT 24
Peak memory 274868 kb
Host smart-f12ce5b1-6e95-42eb-be0a-b4a6788acd87
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367864148 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_mp_regions.2367864148
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.4189790236
Short name T740
Test name
Test status
Simulation time 50567700 ps
CPU time 132.05 seconds
Started Jul 22 05:31:57 PM PDT 24
Finished Jul 22 05:34:09 PM PDT 24
Peak memory 264432 kb
Host smart-e989c5bf-c49e-4a58-ae36-341e65386e60
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189790236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.4189790236
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.1895721761
Short name T70
Test name
Test status
Simulation time 2683780300 ps
CPU time 421.1 seconds
Started Jul 22 05:31:57 PM PDT 24
Finished Jul 22 05:38:58 PM PDT 24
Peak memory 263232 kb
Host smart-2d83bc76-e346-4fc8-83a0-c4ccb42bddcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1895721761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1895721761
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.1917289316
Short name T176
Test name
Test status
Simulation time 22238800 ps
CPU time 13.63 seconds
Started Jul 22 05:32:07 PM PDT 24
Finished Jul 22 05:32:21 PM PDT 24
Peak memory 265412 kb
Host smart-27e29ae1-0a34-475d-8f25-923e4ae3c9e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917289316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.flash_ctrl_prog_reset.1917289316
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.274963207
Short name T109
Test name
Test status
Simulation time 125915200 ps
CPU time 199.69 seconds
Started Jul 22 05:31:56 PM PDT 24
Finished Jul 22 05:35:17 PM PDT 24
Peak memory 274544 kb
Host smart-1d320c47-ff78-47ae-80b1-1d717fb76d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274963207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.274963207
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.3096991957
Short name T977
Test name
Test status
Simulation time 621989100 ps
CPU time 118.68 seconds
Started Jul 22 05:31:58 PM PDT 24
Finished Jul 22 05:33:57 PM PDT 24
Peak memory 281728 kb
Host smart-9bec3f85-dede-4a87-b490-07cf36c2d59f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096991957 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_ro.3096991957
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.440709430
Short name T1081
Test name
Test status
Simulation time 23662236100 ps
CPU time 631.45 seconds
Started Jul 22 05:32:59 PM PDT 24
Finished Jul 22 05:43:31 PM PDT 24
Peak memory 314556 kb
Host smart-e0973181-22b4-4349-a087-0f64d3d4ab8b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440709430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.flash_ctrl_rw.440709430
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.1777333331
Short name T329
Test name
Test status
Simulation time 42551400 ps
CPU time 28.7 seconds
Started Jul 22 05:32:07 PM PDT 24
Finished Jul 22 05:32:36 PM PDT 24
Peak memory 275624 kb
Host smart-91d06ecb-5189-45d9-b0d0-350112111501
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777333331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_rw_evict.1777333331
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.4091684765
Short name T147
Test name
Test status
Simulation time 154041700 ps
CPU time 32.11 seconds
Started Jul 22 05:32:06 PM PDT 24
Finished Jul 22 05:32:39 PM PDT 24
Peak memory 275532 kb
Host smart-505052c0-e7a2-40e1-a33a-60957317cee2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091684765 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.4091684765
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.2153023922
Short name T842
Test name
Test status
Simulation time 2806819900 ps
CPU time 84.05 seconds
Started Jul 22 05:32:06 PM PDT 24
Finished Jul 22 05:33:31 PM PDT 24
Peak memory 263808 kb
Host smart-11b30af2-c885-4326-85fd-9cbfbc8899a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153023922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.2153023922
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.3540257551
Short name T495
Test name
Test status
Simulation time 44396200 ps
CPU time 99.63 seconds
Started Jul 22 05:31:57 PM PDT 24
Finished Jul 22 05:33:37 PM PDT 24
Peak memory 268644 kb
Host smart-5fced1cd-cda6-4637-8688-d25bf2a25661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540257551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.3540257551
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.295741622
Short name T1055
Test name
Test status
Simulation time 8399237700 ps
CPU time 177.59 seconds
Started Jul 22 05:31:57 PM PDT 24
Finished Jul 22 05:34:55 PM PDT 24
Peak memory 261036 kb
Host smart-ba3eda6c-7fa0-48b2-922c-d172e67bc3c6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295741622 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.flash_ctrl_wo.295741622
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.1593590722
Short name T980
Test name
Test status
Simulation time 59881200 ps
CPU time 13.99 seconds
Started Jul 22 05:32:27 PM PDT 24
Finished Jul 22 05:32:42 PM PDT 24
Peak memory 265300 kb
Host smart-807e19c3-dcc2-4641-abae-24fe39302863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593590722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
1593590722
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.1716856434
Short name T940
Test name
Test status
Simulation time 51792400 ps
CPU time 16.28 seconds
Started Jul 22 05:32:29 PM PDT 24
Finished Jul 22 05:32:45 PM PDT 24
Peak memory 274916 kb
Host smart-d43b04ec-f85d-4399-9ffa-546b485cab46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716856434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.1716856434
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.847569254
Short name T938
Test name
Test status
Simulation time 55270400 ps
CPU time 21.93 seconds
Started Jul 22 05:32:18 PM PDT 24
Finished Jul 22 05:32:40 PM PDT 24
Peak memory 273572 kb
Host smart-7827457f-1324-4541-98a3-147e437e6701
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847569254 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.847569254
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1378501730
Short name T844
Test name
Test status
Simulation time 10019235100 ps
CPU time 78.22 seconds
Started Jul 22 05:32:27 PM PDT 24
Finished Jul 22 05:33:46 PM PDT 24
Peak memory 290068 kb
Host smart-d1db74cd-4687-46b3-9753-db2a19ed1635
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378501730 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.1378501730
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.4199967332
Short name T179
Test name
Test status
Simulation time 15509100 ps
CPU time 13.5 seconds
Started Jul 22 05:32:26 PM PDT 24
Finished Jul 22 05:32:40 PM PDT 24
Peak memory 258532 kb
Host smart-1c1107c9-e5d3-4a7d-ac5a-9e0069891b5b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199967332 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.4199967332
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.479407604
Short name T536
Test name
Test status
Simulation time 40129012000 ps
CPU time 863.79 seconds
Started Jul 22 05:32:59 PM PDT 24
Finished Jul 22 05:47:23 PM PDT 24
Peak memory 261056 kb
Host smart-28be56c9-2da2-4dc9-9a8e-30efe07a5d87
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479407604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.flash_ctrl_hw_rma_reset.479407604
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.3525820063
Short name T35
Test name
Test status
Simulation time 2471853800 ps
CPU time 133.37 seconds
Started Jul 22 05:32:16 PM PDT 24
Finished Jul 22 05:34:29 PM PDT 24
Peak memory 298212 kb
Host smart-573f5e66-61b4-44b5-b035-405b3c585574
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525820063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_intr_rd.3525820063
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.3340973267
Short name T426
Test name
Test status
Simulation time 11213867800 ps
CPU time 133.63 seconds
Started Jul 22 05:32:16 PM PDT 24
Finished Jul 22 05:34:30 PM PDT 24
Peak memory 293044 kb
Host smart-1c4dc4b0-046d-4f78-8e12-c2dbcea8c6ba
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340973267 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.3340973267
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.181709616
Short name T900
Test name
Test status
Simulation time 4721837500 ps
CPU time 64.07 seconds
Started Jul 22 05:32:14 PM PDT 24
Finished Jul 22 05:33:19 PM PDT 24
Peak memory 263544 kb
Host smart-cc30cebc-f19f-40b5-8f80-cddc2dbb6817
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181709616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.181709616
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.1451813119
Short name T1000
Test name
Test status
Simulation time 36157800 ps
CPU time 13.5 seconds
Started Jul 22 05:32:28 PM PDT 24
Finished Jul 22 05:32:42 PM PDT 24
Peak memory 264976 kb
Host smart-0d388be6-4bd0-4480-8ed7-7c9e6c9d931b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451813119 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.1451813119
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.3394783706
Short name T154
Test name
Test status
Simulation time 25179102800 ps
CPU time 358.14 seconds
Started Jul 22 05:32:16 PM PDT 24
Finished Jul 22 05:38:15 PM PDT 24
Peak memory 274436 kb
Host smart-2e207720-5983-40cd-b40a-33381a66b72f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394783706 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_mp_regions.3394783706
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.4095247099
Short name T192
Test name
Test status
Simulation time 181171300 ps
CPU time 130.74 seconds
Started Jul 22 05:32:16 PM PDT 24
Finished Jul 22 05:34:28 PM PDT 24
Peak memory 260272 kb
Host smart-fa041ecc-56b7-4f7f-8667-fce732a67faf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095247099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o
tp_reset.4095247099
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.1074658567
Short name T735
Test name
Test status
Simulation time 1427317500 ps
CPU time 455.69 seconds
Started Jul 22 05:32:03 PM PDT 24
Finished Jul 22 05:39:40 PM PDT 24
Peak memory 263224 kb
Host smart-3d58daef-747d-475b-9873-8e35deed093f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074658567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.1074658567
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.1566070239
Short name T998
Test name
Test status
Simulation time 26090200 ps
CPU time 14.25 seconds
Started Jul 22 05:32:16 PM PDT 24
Finished Jul 22 05:32:31 PM PDT 24
Peak memory 259752 kb
Host smart-e2833911-11ee-4bc9-8d61-b0ab4c3f2530
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566070239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.flash_ctrl_prog_reset.1566070239
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.1558568580
Short name T146
Test name
Test status
Simulation time 160428900 ps
CPU time 154.5 seconds
Started Jul 22 05:32:06 PM PDT 24
Finished Jul 22 05:34:41 PM PDT 24
Peak memory 269888 kb
Host smart-a00f026b-d7af-4346-8098-2e97e80b59c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558568580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1558568580
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.3407321285
Short name T349
Test name
Test status
Simulation time 113107100 ps
CPU time 35.24 seconds
Started Jul 22 05:32:14 PM PDT 24
Finished Jul 22 05:32:50 PM PDT 24
Peak memory 273560 kb
Host smart-5e8a6795-aad6-4a91-b9a0-33420a44ab86
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407321285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.3407321285
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.3927275019
Short name T908
Test name
Test status
Simulation time 560098100 ps
CPU time 113.86 seconds
Started Jul 22 05:32:16 PM PDT 24
Finished Jul 22 05:34:11 PM PDT 24
Peak memory 281728 kb
Host smart-d9b86fcf-cd28-440f-893d-b4169c4e422f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927275019 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.flash_ctrl_ro.3927275019
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.2378841238
Short name T609
Test name
Test status
Simulation time 126464300 ps
CPU time 30.9 seconds
Started Jul 22 05:32:14 PM PDT 24
Finished Jul 22 05:32:45 PM PDT 24
Peak memory 268448 kb
Host smart-e333cbad-e121-4605-a215-6ca315bed112
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378841238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_rw_evict.2378841238
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.2898886210
Short name T948
Test name
Test status
Simulation time 34501400 ps
CPU time 99.63 seconds
Started Jul 22 05:32:06 PM PDT 24
Finished Jul 22 05:33:47 PM PDT 24
Peak memory 277232 kb
Host smart-d7c2a405-66e9-4a6c-9517-268123c5ceb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898886210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.2898886210
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.2458319369
Short name T878
Test name
Test status
Simulation time 27806287600 ps
CPU time 235.2 seconds
Started Jul 22 05:32:14 PM PDT 24
Finished Jul 22 05:36:10 PM PDT 24
Peak memory 259976 kb
Host smart-f81d97b6-dd53-47a7-98f1-65fca136e923
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458319369 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.flash_ctrl_wo.2458319369
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.52258906
Short name T47
Test name
Test status
Simulation time 25868600 ps
CPU time 13.59 seconds
Started Jul 22 05:26:48 PM PDT 24
Finished Jul 22 05:27:02 PM PDT 24
Peak memory 261436 kb
Host smart-3100ba3e-f1a9-4457-ac51-8451ab6fca0e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52258906 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.52258906
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.2275469338
Short name T317
Test name
Test status
Simulation time 160884400 ps
CPU time 13.63 seconds
Started Jul 22 05:26:48 PM PDT 24
Finished Jul 22 05:27:02 PM PDT 24
Peak memory 258464 kb
Host smart-6751ef19-603b-47af-8d26-d1323309a4ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275469338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.2
275469338
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.3345472833
Short name T376
Test name
Test status
Simulation time 26223200 ps
CPU time 13.99 seconds
Started Jul 22 05:28:00 PM PDT 24
Finished Jul 22 05:28:14 PM PDT 24
Peak memory 261652 kb
Host smart-46bb6fad-6c92-4773-8ef2-8e43d6c95331
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345472833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.3345472833
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.384828592
Short name T561
Test name
Test status
Simulation time 25414000 ps
CPU time 13.33 seconds
Started Jul 22 05:26:49 PM PDT 24
Finished Jul 22 05:27:03 PM PDT 24
Peak memory 284376 kb
Host smart-0ebacc37-98c4-4361-8327-cc3ddc9d2eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384828592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.384828592
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.96782402
Short name T98
Test name
Test status
Simulation time 23665000 ps
CPU time 21.59 seconds
Started Jul 22 05:26:48 PM PDT 24
Finished Jul 22 05:27:10 PM PDT 24
Peak memory 273516 kb
Host smart-557bb041-122f-4c88-b46c-f8ae5b2dee83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96782402 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.flash_ctrl_disable.96782402
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.1737104545
Short name T870
Test name
Test status
Simulation time 7120793700 ps
CPU time 2675.1 seconds
Started Jul 22 05:26:37 PM PDT 24
Finished Jul 22 06:11:13 PM PDT 24
Peak memory 264676 kb
Host smart-69102f81-faf2-4383-8d56-50f95b3cd112
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1737104545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.1737104545
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.3374051250
Short name T85
Test name
Test status
Simulation time 2236418300 ps
CPU time 2301.81 seconds
Started Jul 22 05:26:36 PM PDT 24
Finished Jul 22 06:04:59 PM PDT 24
Peak memory 262244 kb
Host smart-68747b46-d6b6-4998-be44-fa5e45f82b64
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374051250 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.3374051250
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.4059978811
Short name T51
Test name
Test status
Simulation time 3059930000 ps
CPU time 32.51 seconds
Started Jul 22 05:26:34 PM PDT 24
Finished Jul 22 05:27:07 PM PDT 24
Peak memory 262564 kb
Host smart-63691c22-f0be-4995-93e7-6aaeeeb4c87d
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059978811 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_fetch_code.4059978811
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.419224324
Short name T845
Test name
Test status
Simulation time 99777743000 ps
CPU time 3548.24 seconds
Started Jul 22 05:27:05 PM PDT 24
Finished Jul 22 06:26:13 PM PDT 24
Peak memory 265212 kb
Host smart-f14589e3-ab9a-4253-8a71-4a7cf8655eb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419224324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_full_mem_access.419224324
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_addr_infection.820607147
Short name T1077
Test name
Test status
Simulation time 27573100 ps
CPU time 29.73 seconds
Started Jul 22 05:28:24 PM PDT 24
Finished Jul 22 05:28:55 PM PDT 24
Peak memory 268388 kb
Host smart-cb495623-3346-4b75-bf79-4920833d7b3a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820607147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_host_addr_infection.820607147
Directory /workspace/2.flash_ctrl_host_addr_infection/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.1967195369
Short name T278
Test name
Test status
Simulation time 52332400 ps
CPU time 88.34 seconds
Started Jul 22 05:26:31 PM PDT 24
Finished Jul 22 05:28:01 PM PDT 24
Peak memory 265272 kb
Host smart-690ab1de-b105-4ad4-a47d-280e882bd09c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1967195369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.1967195369
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3896883962
Short name T603
Test name
Test status
Simulation time 10019004300 ps
CPU time 90.64 seconds
Started Jul 22 05:26:53 PM PDT 24
Finished Jul 22 05:28:24 PM PDT 24
Peak memory 330352 kb
Host smart-77e1ed90-60a2-4df5-8807-0e92cca896e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896883962 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.3896883962
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.348297982
Short name T340
Test name
Test status
Simulation time 25095600 ps
CPU time 13.58 seconds
Started Jul 22 05:26:50 PM PDT 24
Finished Jul 22 05:27:04 PM PDT 24
Peak memory 260256 kb
Host smart-ab14e269-12cb-48d2-9bec-31085f223393
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348297982 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.348297982
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.986178303
Short name T716
Test name
Test status
Simulation time 334656537200 ps
CPU time 1781.85 seconds
Started Jul 22 05:26:45 PM PDT 24
Finished Jul 22 05:56:28 PM PDT 24
Peak memory 260752 kb
Host smart-9d35f97a-3e24-4f64-baf9-ce3810e9b717
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986178303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_hw_rma.986178303
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.2419206665
Short name T852
Test name
Test status
Simulation time 80143715000 ps
CPU time 871.79 seconds
Started Jul 22 05:26:39 PM PDT 24
Finished Jul 22 05:41:11 PM PDT 24
Peak memory 264204 kb
Host smart-6daef5ca-2e7b-49bc-bc78-ceadcb503763
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419206665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.2419206665
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.3630648233
Short name T988
Test name
Test status
Simulation time 4254772300 ps
CPU time 621.77 seconds
Started Jul 22 05:26:36 PM PDT 24
Finished Jul 22 05:36:58 PM PDT 24
Peak memory 336780 kb
Host smart-1fd77dd8-9cf8-46e4-866b-22a80743eefb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630648233 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_integrity.3630648233
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.1335283853
Short name T548
Test name
Test status
Simulation time 667755900 ps
CPU time 131.91 seconds
Started Jul 22 05:27:04 PM PDT 24
Finished Jul 22 05:29:16 PM PDT 24
Peak memory 284912 kb
Host smart-37422682-177a-4320-8bee-1cb949778e55
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335283853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.1335283853
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.2859283071
Short name T87
Test name
Test status
Simulation time 64757009800 ps
CPU time 279.05 seconds
Started Jul 22 05:28:30 PM PDT 24
Finished Jul 22 05:33:10 PM PDT 24
Peak memory 294420 kb
Host smart-993a72bb-1263-42cc-a68e-0751476302e4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859283071 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.2859283071
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.509933135
Short name T28
Test name
Test status
Simulation time 1879334300 ps
CPU time 63.87 seconds
Started Jul 22 05:26:59 PM PDT 24
Finished Jul 22 05:28:03 PM PDT 24
Peak memory 260360 kb
Host smart-1e9bf8eb-218f-4fa8-8d55-cae92b00e4a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509933135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_intr_wr.509933135
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1953511293
Short name T478
Test name
Test status
Simulation time 49549260200 ps
CPU time 167.74 seconds
Started Jul 22 05:26:38 PM PDT 24
Finished Jul 22 05:29:26 PM PDT 24
Peak memory 265352 kb
Host smart-ab911b48-04a0-493b-be3c-517ccd4a6d65
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195
3511293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.1953511293
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.1219365648
Short name T629
Test name
Test status
Simulation time 16253454300 ps
CPU time 72.34 seconds
Started Jul 22 05:26:45 PM PDT 24
Finished Jul 22 05:27:57 PM PDT 24
Peak memory 262848 kb
Host smart-324ce0ca-67c2-4d2a-b61f-734817143220
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219365648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.1219365648
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.248870389
Short name T185
Test name
Test status
Simulation time 63287600 ps
CPU time 13.15 seconds
Started Jul 22 05:28:25 PM PDT 24
Finished Jul 22 05:28:38 PM PDT 24
Peak memory 260824 kb
Host smart-b6ba52be-392c-44ea-8a86-4c4ac2d0732e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248870389 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.248870389
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.5824609
Short name T172
Test name
Test status
Simulation time 2580500900 ps
CPU time 71.74 seconds
Started Jul 22 05:26:37 PM PDT 24
Finished Jul 22 05:27:49 PM PDT 24
Peak memory 260664 kb
Host smart-fb39a8b0-e9cb-41a7-b249-9687df8072fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5824609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.5824609
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.2103268775
Short name T156
Test name
Test status
Simulation time 42110275500 ps
CPU time 252.55 seconds
Started Jul 22 05:26:59 PM PDT 24
Finished Jul 22 05:31:12 PM PDT 24
Peak memory 275136 kb
Host smart-f3840964-9ffa-4a1a-8194-888ccb620891
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103268775 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.2103268775
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.1745272400
Short name T765
Test name
Test status
Simulation time 40736600 ps
CPU time 130.24 seconds
Started Jul 22 05:28:02 PM PDT 24
Finished Jul 22 05:30:12 PM PDT 24
Peak memory 261160 kb
Host smart-bbec987a-4e4d-4397-8f01-d5c35fa296b9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745272400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.1745272400
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.4122533604
Short name T45
Test name
Test status
Simulation time 1368538700 ps
CPU time 221.01 seconds
Started Jul 22 05:26:38 PM PDT 24
Finished Jul 22 05:30:19 PM PDT 24
Peak memory 293104 kb
Host smart-7de07dc9-395f-42b9-b930-a44de69ad686
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122533604 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.4122533604
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.3685416573
Short name T644
Test name
Test status
Simulation time 3047493900 ps
CPU time 470.29 seconds
Started Jul 22 05:26:33 PM PDT 24
Finished Jul 22 05:34:25 PM PDT 24
Peak memory 263064 kb
Host smart-a64afd32-5aeb-4a16-88ac-b42bf37a254b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3685416573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.3685416573
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.4277645849
Short name T428
Test name
Test status
Simulation time 24490100 ps
CPU time 14.07 seconds
Started Jul 22 05:26:53 PM PDT 24
Finished Jul 22 05:27:07 PM PDT 24
Peak memory 262832 kb
Host smart-6197a003-c1c4-4f41-a3dc-ff66a51be4b3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277645849 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.4277645849
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.3782879118
Short name T282
Test name
Test status
Simulation time 4795290600 ps
CPU time 198.64 seconds
Started Jul 22 05:26:43 PM PDT 24
Finished Jul 22 05:30:02 PM PDT 24
Peak memory 260680 kb
Host smart-83f549b2-fac6-4b76-90bb-ea08c29d9728
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782879118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.flash_ctrl_prog_reset.3782879118
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.3189328105
Short name T897
Test name
Test status
Simulation time 40258900 ps
CPU time 125.96 seconds
Started Jul 22 05:26:35 PM PDT 24
Finished Jul 22 05:28:41 PM PDT 24
Peak memory 270772 kb
Host smart-3d172521-2290-44cc-842a-05f5eb061eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189328105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.3189328105
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.4115529961
Short name T1084
Test name
Test status
Simulation time 102876900 ps
CPU time 100.59 seconds
Started Jul 22 05:26:33 PM PDT 24
Finished Jul 22 05:28:14 PM PDT 24
Peak memory 262880 kb
Host smart-12016f59-994c-4cd2-a554-81fbb269726d
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4115529961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.4115529961
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.568852572
Short name T1006
Test name
Test status
Simulation time 63117300 ps
CPU time 32.22 seconds
Started Jul 22 05:26:48 PM PDT 24
Finished Jul 22 05:27:20 PM PDT 24
Peak memory 275760 kb
Host smart-593edca7-4f1f-44e3-9828-b07e6360cdd5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568852572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_rd_intg.568852572
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.4096667536
Short name T288
Test name
Test status
Simulation time 57199200 ps
CPU time 33.43 seconds
Started Jul 22 05:26:44 PM PDT 24
Finished Jul 22 05:27:18 PM PDT 24
Peak memory 275676 kb
Host smart-5b40dc5e-987d-4525-8fd0-a3553983e82f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096667536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.4096667536
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.231238800
Short name T519
Test name
Test status
Simulation time 122936100 ps
CPU time 21.27 seconds
Started Jul 22 05:26:36 PM PDT 24
Finished Jul 22 05:26:58 PM PDT 24
Peak memory 265424 kb
Host smart-14b2ee6c-028e-452d-8468-35a166ec863d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231238800 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.231238800
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.2541173018
Short name T579
Test name
Test status
Simulation time 78292400 ps
CPU time 21.3 seconds
Started Jul 22 05:26:37 PM PDT 24
Finished Jul 22 05:26:58 PM PDT 24
Peak memory 265388 kb
Host smart-ff4b8535-6c9f-4d1f-aa51-0bd0abffd827
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541173018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.2541173018
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.3759846407
Short name T198
Test name
Test status
Simulation time 211589658100 ps
CPU time 1034.63 seconds
Started Jul 22 05:28:25 PM PDT 24
Finished Jul 22 05:45:40 PM PDT 24
Peak memory 261236 kb
Host smart-07791193-945a-4c6c-8626-f0cc066a3b01
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759846407 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.3759846407
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.3243436277
Short name T697
Test name
Test status
Simulation time 1764915200 ps
CPU time 120.39 seconds
Started Jul 22 05:26:35 PM PDT 24
Finished Jul 22 05:28:36 PM PDT 24
Peak memory 281736 kb
Host smart-4239d402-e778-457c-904a-11dd678f3a93
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243436277 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_ro.3243436277
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.3539873498
Short name T693
Test name
Test status
Simulation time 3920122000 ps
CPU time 111.65 seconds
Started Jul 22 05:28:30 PM PDT 24
Finished Jul 22 05:30:22 PM PDT 24
Peak memory 290576 kb
Host smart-9563afb2-4eb1-4b8c-ba20-d6a462fc15c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539873498 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.3539873498
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.2358781504
Short name T905
Test name
Test status
Simulation time 61193661600 ps
CPU time 658.1 seconds
Started Jul 22 05:26:36 PM PDT 24
Finished Jul 22 05:37:34 PM PDT 24
Peak memory 314300 kb
Host smart-30f580d8-900f-4184-999d-fe721983354f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358781504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.flash_ctrl_rw.2358781504
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.1421783204
Short name T254
Test name
Test status
Simulation time 6376405100 ps
CPU time 796.7 seconds
Started Jul 22 05:26:38 PM PDT 24
Finished Jul 22 05:39:55 PM PDT 24
Peak memory 339160 kb
Host smart-e2cff024-7792-44fd-8f33-666732a5bb4d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421783204 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_rw_derr.1421783204
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.3177683951
Short name T746
Test name
Test status
Simulation time 63833600 ps
CPU time 32.23 seconds
Started Jul 22 05:28:03 PM PDT 24
Finished Jul 22 05:28:35 PM PDT 24
Peak memory 268464 kb
Host smart-5c952050-6602-460a-90d8-b09e4414957c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177683951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_rw_evict.3177683951
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.4194900808
Short name T210
Test name
Test status
Simulation time 39416500 ps
CPU time 30.69 seconds
Started Jul 22 05:26:48 PM PDT 24
Finished Jul 22 05:27:19 PM PDT 24
Peak memory 275564 kb
Host smart-5d34b9d4-bd30-44fc-857a-9cd8472c7a72
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194900808 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.4194900808
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.2107823754
Short name T682
Test name
Test status
Simulation time 12003559300 ps
CPU time 671.82 seconds
Started Jul 22 05:26:39 PM PDT 24
Finished Jul 22 05:37:51 PM PDT 24
Peak memory 312544 kb
Host smart-942e0315-addf-4d52-9714-161bdd0ef3db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107823754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_s
err.2107823754
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.1397330053
Short name T750
Test name
Test status
Simulation time 3894791700 ps
CPU time 75.33 seconds
Started Jul 22 05:26:47 PM PDT 24
Finished Jul 22 05:28:03 PM PDT 24
Peak memory 263548 kb
Host smart-88d2a056-bff0-4ad8-ac69-b0d7c8748b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397330053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.1397330053
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.463668181
Short name T572
Test name
Test status
Simulation time 3490276500 ps
CPU time 92.06 seconds
Started Jul 22 05:26:45 PM PDT 24
Finished Jul 22 05:28:17 PM PDT 24
Peak memory 265344 kb
Host smart-a6370586-d42f-4494-8b8f-5905259b9c1f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463668181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_serr_address.463668181
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.4119746698
Short name T145
Test name
Test status
Simulation time 4536830600 ps
CPU time 87 seconds
Started Jul 22 05:26:37 PM PDT 24
Finished Jul 22 05:28:05 PM PDT 24
Peak memory 273632 kb
Host smart-5da86f9f-6c09-4ca3-9768-a318a42aeaa9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119746698 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.4119746698
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.1478450928
Short name T389
Test name
Test status
Simulation time 22702300 ps
CPU time 97.69 seconds
Started Jul 22 05:26:33 PM PDT 24
Finished Jul 22 05:28:11 PM PDT 24
Peak memory 277396 kb
Host smart-8a15f53b-232c-4000-8187-955eebed3b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478450928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.1478450928
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.3313219507
Short name T434
Test name
Test status
Simulation time 52209600 ps
CPU time 26.03 seconds
Started Jul 22 05:26:25 PM PDT 24
Finished Jul 22 05:26:51 PM PDT 24
Peak memory 259596 kb
Host smart-255e050d-6059-443a-a5c4-4b0ab405dbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313219507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.3313219507
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.367483922
Short name T1012
Test name
Test status
Simulation time 1704280500 ps
CPU time 1672.72 seconds
Started Jul 22 05:26:46 PM PDT 24
Finished Jul 22 05:54:39 PM PDT 24
Peak memory 292176 kb
Host smart-ca9055f8-09ef-436b-87b5-6ca87e36e814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367483922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress
_all.367483922
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.4034357504
Short name T446
Test name
Test status
Simulation time 89959600 ps
CPU time 26.18 seconds
Started Jul 22 05:28:02 PM PDT 24
Finished Jul 22 05:28:28 PM PDT 24
Peak memory 262320 kb
Host smart-b8c89626-2ec2-43f3-a787-6d410225dbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034357504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.4034357504
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.1828232162
Short name T891
Test name
Test status
Simulation time 2171051500 ps
CPU time 155.62 seconds
Started Jul 22 05:26:39 PM PDT 24
Finished Jul 22 05:29:15 PM PDT 24
Peak memory 259912 kb
Host smart-9456f75b-5df3-4540-ae21-a8dadd9b95d0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828232162 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_wo.1828232162
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.719565519
Short name T22
Test name
Test status
Simulation time 44592700 ps
CPU time 15.24 seconds
Started Jul 22 05:26:48 PM PDT 24
Finished Jul 22 05:27:04 PM PDT 24
Peak memory 264856 kb
Host smart-e8930805-f2de-4ce0-ba3a-8e3ef196d818
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719565519 -assert nopostproc +UVM
_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.719565519
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.3243388518
Short name T612
Test name
Test status
Simulation time 314637900 ps
CPU time 14.23 seconds
Started Jul 22 05:33:13 PM PDT 24
Finished Jul 22 05:33:27 PM PDT 24
Peak memory 258372 kb
Host smart-dc192c8e-5553-45c6-afe0-4afc07c724e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243388518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
3243388518
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.740674172
Short name T749
Test name
Test status
Simulation time 40059000 ps
CPU time 16.12 seconds
Started Jul 22 05:32:26 PM PDT 24
Finished Jul 22 05:32:43 PM PDT 24
Peak memory 284428 kb
Host smart-874a201b-8cc6-4f73-a2ac-29388f0aef04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740674172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.740674172
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.2665696187
Short name T377
Test name
Test status
Simulation time 63588500 ps
CPU time 20.57 seconds
Started Jul 22 05:34:26 PM PDT 24
Finished Jul 22 05:34:48 PM PDT 24
Peak memory 274432 kb
Host smart-f6f7174b-e3ed-4740-86ba-21cdb69bf6e0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665696187 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.2665696187
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.293899356
Short name T1047
Test name
Test status
Simulation time 1412708000 ps
CPU time 65.64 seconds
Started Jul 22 05:32:27 PM PDT 24
Finished Jul 22 05:33:33 PM PDT 24
Peak memory 262844 kb
Host smart-06171773-1694-4c7c-be01-a0c56ef954be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293899356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_h
w_sec_otp.293899356
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.3311090191
Short name T116
Test name
Test status
Simulation time 2885580600 ps
CPU time 184.82 seconds
Started Jul 22 05:32:26 PM PDT 24
Finished Jul 22 05:35:31 PM PDT 24
Peak memory 294116 kb
Host smart-eac839eb-4d81-40a1-b023-8833287ab188
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311090191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.3311090191
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.3712977537
Short name T1052
Test name
Test status
Simulation time 24278258700 ps
CPU time 169.22 seconds
Started Jul 22 05:32:24 PM PDT 24
Finished Jul 22 05:35:14 PM PDT 24
Peak memory 292996 kb
Host smart-71f77403-13dd-4b9f-a86f-9f486d0163fe
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712977537 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.3712977537
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.2135146847
Short name T711
Test name
Test status
Simulation time 39414000 ps
CPU time 129.08 seconds
Started Jul 22 05:34:26 PM PDT 24
Finished Jul 22 05:36:36 PM PDT 24
Peak memory 260948 kb
Host smart-69a721b5-f9af-4916-a503-8a102c2da3f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135146847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.2135146847
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.3325711187
Short name T877
Test name
Test status
Simulation time 8846293100 ps
CPU time 164.77 seconds
Started Jul 22 05:32:28 PM PDT 24
Finished Jul 22 05:35:13 PM PDT 24
Peak memory 260740 kb
Host smart-a7f91a22-1391-48d7-8402-399bc3583667
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325711187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.flash_ctrl_prog_reset.3325711187
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.956907856
Short name T820
Test name
Test status
Simulation time 58261900 ps
CPU time 29.29 seconds
Started Jul 22 05:32:25 PM PDT 24
Finished Jul 22 05:32:55 PM PDT 24
Peak memory 275960 kb
Host smart-97571991-b5d5-42e6-bd56-6c2c3759142e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956907856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_rw_evict.956907856
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.1940285572
Short name T1050
Test name
Test status
Simulation time 72616300 ps
CPU time 30.26 seconds
Started Jul 22 05:33:12 PM PDT 24
Finished Jul 22 05:33:43 PM PDT 24
Peak memory 268524 kb
Host smart-e4a1e7f4-0bfb-49eb-bf0c-dbb3b4461e2a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940285572 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.1940285572
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.3173821685
Short name T723
Test name
Test status
Simulation time 1906676900 ps
CPU time 65.54 seconds
Started Jul 22 05:32:51 PM PDT 24
Finished Jul 22 05:33:57 PM PDT 24
Peak memory 264648 kb
Host smart-848b12ee-548e-4cce-b9e4-dc6b4364a5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173821685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.3173821685
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.2153481825
Short name T732
Test name
Test status
Simulation time 53870700 ps
CPU time 123.31 seconds
Started Jul 22 05:32:26 PM PDT 24
Finished Jul 22 05:34:30 PM PDT 24
Peak memory 277476 kb
Host smart-6757e114-d2e5-4080-bf78-d45440e21730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153481825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.2153481825
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.4049730682
Short name T972
Test name
Test status
Simulation time 25278400 ps
CPU time 13.75 seconds
Started Jul 22 05:32:36 PM PDT 24
Finished Jul 22 05:32:50 PM PDT 24
Peak memory 258300 kb
Host smart-665373fe-854a-45a8-932e-8c625cd1d679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049730682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
4049730682
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.2542451932
Short name T1036
Test name
Test status
Simulation time 48437100 ps
CPU time 15.71 seconds
Started Jul 22 05:34:26 PM PDT 24
Finished Jul 22 05:34:43 PM PDT 24
Peak memory 284264 kb
Host smart-3249a902-b004-450c-8e62-965230baf2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542451932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.2542451932
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.3138301115
Short name T728
Test name
Test status
Simulation time 24005000 ps
CPU time 22.22 seconds
Started Jul 22 05:32:34 PM PDT 24
Finished Jul 22 05:32:56 PM PDT 24
Peak memory 273536 kb
Host smart-90cf6cfe-d9be-4fcf-ac9e-ef5121f6582c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138301115 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.3138301115
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.2742336277
Short name T100
Test name
Test status
Simulation time 1727689000 ps
CPU time 63.4 seconds
Started Jul 22 05:32:25 PM PDT 24
Finished Jul 22 05:33:29 PM PDT 24
Peak memory 262712 kb
Host smart-2101bb76-6dab-430e-a599-31ed75ee3bb5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742336277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.2742336277
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.22921730
Short name T975
Test name
Test status
Simulation time 612776400 ps
CPU time 152.71 seconds
Started Jul 22 05:32:29 PM PDT 24
Finished Jul 22 05:35:02 PM PDT 24
Peak memory 285460 kb
Host smart-99b44140-dc3c-492b-9835-a26f54f47d70
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22921730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash
_ctrl_intr_rd.22921730
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.2159039388
Short name T702
Test name
Test status
Simulation time 12901612700 ps
CPU time 303.96 seconds
Started Jul 22 05:32:36 PM PDT 24
Finished Jul 22 05:37:40 PM PDT 24
Peak memory 291040 kb
Host smart-70ecf247-6c31-445f-b98b-fceba255d284
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159039388 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.2159039388
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.2062677572
Short name T501
Test name
Test status
Simulation time 146584500 ps
CPU time 131.98 seconds
Started Jul 22 05:32:28 PM PDT 24
Finished Jul 22 05:34:41 PM PDT 24
Peak memory 265104 kb
Host smart-b8a212e6-0eb1-472c-87c5-e96869d38b39
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062677572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.2062677572
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.1613303716
Short name T537
Test name
Test status
Simulation time 32637400 ps
CPU time 13.7 seconds
Started Jul 22 05:32:40 PM PDT 24
Finished Jul 22 05:32:54 PM PDT 24
Peak memory 259124 kb
Host smart-66944a74-31a6-4390-87a2-1dd2424e6976
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613303716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.flash_ctrl_prog_reset.1613303716
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.2122639662
Short name T467
Test name
Test status
Simulation time 35236800 ps
CPU time 31.14 seconds
Started Jul 22 05:32:35 PM PDT 24
Finished Jul 22 05:33:06 PM PDT 24
Peak memory 275592 kb
Host smart-ca14f9d9-efc2-444e-b065-6a10d514a22a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122639662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl
ash_ctrl_rw_evict.2122639662
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.3129881617
Short name T1106
Test name
Test status
Simulation time 29271800 ps
CPU time 31.81 seconds
Started Jul 22 05:32:35 PM PDT 24
Finished Jul 22 05:33:07 PM PDT 24
Peak memory 275620 kb
Host smart-ed269e4e-4320-449c-aaf5-6510f573ef84
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129881617 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.3129881617
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.3790195655
Short name T416
Test name
Test status
Simulation time 5743855900 ps
CPU time 66.03 seconds
Started Jul 22 05:34:50 PM PDT 24
Finished Jul 22 05:35:57 PM PDT 24
Peak memory 263496 kb
Host smart-acc0511e-baca-4a5a-9080-377fffa7cde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790195655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.3790195655
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.3653988105
Short name T880
Test name
Test status
Simulation time 24911900 ps
CPU time 171.04 seconds
Started Jul 22 05:32:29 PM PDT 24
Finished Jul 22 05:35:20 PM PDT 24
Peak memory 278572 kb
Host smart-3b6a6016-5c17-4582-aab5-69777d5a3a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653988105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.3653988105
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.2234422229
Short name T1046
Test name
Test status
Simulation time 28462100 ps
CPU time 13.46 seconds
Started Jul 22 05:32:36 PM PDT 24
Finished Jul 22 05:32:50 PM PDT 24
Peak memory 258536 kb
Host smart-329fe3a1-4923-445c-9e68-798dbbe2d12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234422229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
2234422229
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.704240938
Short name T895
Test name
Test status
Simulation time 16768100 ps
CPU time 15.96 seconds
Started Jul 22 05:34:26 PM PDT 24
Finished Jul 22 05:34:43 PM PDT 24
Peak memory 284328 kb
Host smart-99a49cdb-54b1-4200-bcc8-4d78c2054664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704240938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.704240938
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.114036631
Short name T743
Test name
Test status
Simulation time 15888600 ps
CPU time 22.04 seconds
Started Jul 22 05:32:37 PM PDT 24
Finished Jul 22 05:32:59 PM PDT 24
Peak memory 273612 kb
Host smart-66f9f8dc-d6f7-4849-85cb-5ab78bbe62fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114036631 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.114036631
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.2118712341
Short name T575
Test name
Test status
Simulation time 2434754800 ps
CPU time 181.21 seconds
Started Jul 22 05:32:37 PM PDT 24
Finished Jul 22 05:35:38 PM PDT 24
Peak memory 262912 kb
Host smart-20a20eed-f37b-49d9-9086-09e90193c51a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118712341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.2118712341
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.1222198069
Short name T803
Test name
Test status
Simulation time 3114813700 ps
CPU time 214.23 seconds
Started Jul 22 05:32:35 PM PDT 24
Finished Jul 22 05:36:10 PM PDT 24
Peak memory 284848 kb
Host smart-1845bb44-2e3e-434e-bfb6-643c4e05041c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222198069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_intr_rd.1222198069
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.227302004
Short name T1044
Test name
Test status
Simulation time 9577454800 ps
CPU time 139.36 seconds
Started Jul 22 05:32:35 PM PDT 24
Finished Jul 22 05:34:55 PM PDT 24
Peak memory 293184 kb
Host smart-bd65da49-0558-47f5-912a-b837d2cd7635
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227302004 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.227302004
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.2962301860
Short name T293
Test name
Test status
Simulation time 147944300 ps
CPU time 109.76 seconds
Started Jul 22 05:32:34 PM PDT 24
Finished Jul 22 05:34:24 PM PDT 24
Peak memory 261028 kb
Host smart-4db423eb-eb11-448e-a1de-129c07e2ca82
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962301860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.2962301860
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.722880540
Short name T1059
Test name
Test status
Simulation time 37400200 ps
CPU time 13.65 seconds
Started Jul 22 05:32:34 PM PDT 24
Finished Jul 22 05:32:48 PM PDT 24
Peak memory 259188 kb
Host smart-92e962e0-f5dc-48ce-bbff-aa3733597b42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722880540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.flash_ctrl_prog_reset.722880540
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.2854938408
Short name T351
Test name
Test status
Simulation time 28910400 ps
CPU time 28.16 seconds
Started Jul 22 05:32:36 PM PDT 24
Finished Jul 22 05:33:04 PM PDT 24
Peak memory 267612 kb
Host smart-912d252b-dad0-42ab-8994-cb1d2a5766af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854938408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl
ash_ctrl_rw_evict.2854938408
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.2090081775
Short name T361
Test name
Test status
Simulation time 47445900 ps
CPU time 30.47 seconds
Started Jul 22 05:32:35 PM PDT 24
Finished Jul 22 05:33:06 PM PDT 24
Peak memory 273592 kb
Host smart-07098663-5fb4-4741-90e6-48d4115a921c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090081775 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.2090081775
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.2570347179
Short name T639
Test name
Test status
Simulation time 30009200 ps
CPU time 98.54 seconds
Started Jul 22 05:32:35 PM PDT 24
Finished Jul 22 05:34:14 PM PDT 24
Peak memory 276304 kb
Host smart-114abfea-61b2-454c-a2e6-43df63b13de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570347179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.2570347179
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.4270897387
Short name T849
Test name
Test status
Simulation time 57678700 ps
CPU time 13.82 seconds
Started Jul 22 05:34:48 PM PDT 24
Finished Jul 22 05:35:02 PM PDT 24
Peak memory 265272 kb
Host smart-35edd738-79ea-4b4e-814b-a28430040706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270897387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
4270897387
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.2096161865
Short name T833
Test name
Test status
Simulation time 17417700 ps
CPU time 16 seconds
Started Jul 22 05:34:48 PM PDT 24
Finished Jul 22 05:35:04 PM PDT 24
Peak memory 274976 kb
Host smart-1c8f1fda-288a-4bc7-8c9f-a392dffb72e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096161865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.2096161865
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.2093736952
Short name T381
Test name
Test status
Simulation time 16898800 ps
CPU time 20.44 seconds
Started Jul 22 05:32:45 PM PDT 24
Finished Jul 22 05:33:06 PM PDT 24
Peak memory 274776 kb
Host smart-61655d35-4e18-4324-814e-2f395416d86c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093736952 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.2093736952
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.635071183
Short name T526
Test name
Test status
Simulation time 12073551600 ps
CPU time 255.24 seconds
Started Jul 22 05:32:46 PM PDT 24
Finished Jul 22 05:37:01 PM PDT 24
Peak memory 261180 kb
Host smart-2d0226a7-d5ce-4737-9dfa-aa8297273818
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635071183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_h
w_sec_otp.635071183
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.537872897
Short name T715
Test name
Test status
Simulation time 1585549400 ps
CPU time 217.57 seconds
Started Jul 22 05:32:44 PM PDT 24
Finished Jul 22 05:36:22 PM PDT 24
Peak memory 284956 kb
Host smart-eb460f78-5873-4186-a1e6-1ac2d842fd66
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537872897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flas
h_ctrl_intr_rd.537872897
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.1266000868
Short name T3
Test name
Test status
Simulation time 11409295800 ps
CPU time 166.54 seconds
Started Jul 22 05:32:46 PM PDT 24
Finished Jul 22 05:35:33 PM PDT 24
Peak memory 293124 kb
Host smart-fa08cfd4-2452-4596-9832-b608e9142173
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266000868 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.1266000868
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.3723963752
Short name T944
Test name
Test status
Simulation time 128723200 ps
CPU time 128.68 seconds
Started Jul 22 05:32:43 PM PDT 24
Finished Jul 22 05:34:52 PM PDT 24
Peak memory 260040 kb
Host smart-54e954ab-1f17-4829-8c05-3b6d2900d07d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723963752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.3723963752
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.3948591869
Short name T989
Test name
Test status
Simulation time 112920800 ps
CPU time 13.68 seconds
Started Jul 22 05:32:46 PM PDT 24
Finished Jul 22 05:33:00 PM PDT 24
Peak memory 259200 kb
Host smart-7ccbbec3-7787-47a5-8604-5f2dfa03b27a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948591869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.flash_ctrl_prog_reset.3948591869
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.3728702823
Short name T763
Test name
Test status
Simulation time 48243700 ps
CPU time 28.89 seconds
Started Jul 22 05:32:45 PM PDT 24
Finished Jul 22 05:33:14 PM PDT 24
Peak memory 275660 kb
Host smart-7ae93c81-e7fa-47f7-a8f7-6fa44e466f5c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728702823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl
ash_ctrl_rw_evict.3728702823
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.1484036421
Short name T1060
Test name
Test status
Simulation time 40271300 ps
CPU time 30.56 seconds
Started Jul 22 05:32:46 PM PDT 24
Finished Jul 22 05:33:17 PM PDT 24
Peak memory 273624 kb
Host smart-b43e7ed9-5444-47aa-bde7-2f94195ea9d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484036421 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.1484036421
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.3759056128
Short name T481
Test name
Test status
Simulation time 1213966500 ps
CPU time 64.09 seconds
Started Jul 22 05:32:45 PM PDT 24
Finished Jul 22 05:33:50 PM PDT 24
Peak memory 264964 kb
Host smart-d069303c-e0b1-4e70-bb4a-fa70a87b2219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759056128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.3759056128
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.4146337958
Short name T724
Test name
Test status
Simulation time 41118800 ps
CPU time 126.25 seconds
Started Jul 22 05:32:44 PM PDT 24
Finished Jul 22 05:34:51 PM PDT 24
Peak memory 276436 kb
Host smart-3f4e3d83-cd02-42a4-abb6-850e5e33fdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146337958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.4146337958
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.774464696
Short name T386
Test name
Test status
Simulation time 60062600 ps
CPU time 13.53 seconds
Started Jul 22 05:34:50 PM PDT 24
Finished Jul 22 05:35:05 PM PDT 24
Peak memory 265212 kb
Host smart-a684e64e-9568-4dd8-ba70-3739a14550b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774464696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.774464696
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.3353680511
Short name T438
Test name
Test status
Simulation time 14940300 ps
CPU time 15.8 seconds
Started Jul 22 05:34:22 PM PDT 24
Finished Jul 22 05:34:38 PM PDT 24
Peak memory 284436 kb
Host smart-d31e122b-1dcd-49b3-a8f0-eb48429560f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353680511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.3353680511
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.2632592726
Short name T380
Test name
Test status
Simulation time 12694100 ps
CPU time 22.7 seconds
Started Jul 22 05:32:53 PM PDT 24
Finished Jul 22 05:33:16 PM PDT 24
Peak memory 273432 kb
Host smart-8064820c-adae-423c-9a1e-9cd796e9086d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632592726 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.2632592726
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.1321311328
Short name T695
Test name
Test status
Simulation time 28744926100 ps
CPU time 112.07 seconds
Started Jul 22 05:32:45 PM PDT 24
Finished Jul 22 05:34:38 PM PDT 24
Peak memory 263368 kb
Host smart-08c659a9-78fa-45f2-8dc2-fbbad3ff12a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321311328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.1321311328
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.3077427221
Short name T1090
Test name
Test status
Simulation time 1990853600 ps
CPU time 141.36 seconds
Started Jul 22 05:32:59 PM PDT 24
Finished Jul 22 05:35:20 PM PDT 24
Peak memory 285340 kb
Host smart-2ad4eb6b-bb02-4529-8ea0-b86833ca2716
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077427221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_intr_rd.3077427221
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.3390460807
Short name T823
Test name
Test status
Simulation time 13116641600 ps
CPU time 326.92 seconds
Started Jul 22 05:32:54 PM PDT 24
Finished Jul 22 05:38:21 PM PDT 24
Peak memory 292344 kb
Host smart-844e92ea-6272-4c3e-bfaf-f5845549a276
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390460807 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.3390460807
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.58028710
Short name T642
Test name
Test status
Simulation time 140407800 ps
CPU time 110.22 seconds
Started Jul 22 05:32:43 PM PDT 24
Finished Jul 22 05:34:34 PM PDT 24
Peak memory 260076 kb
Host smart-a2c09f0f-fdf3-421b-8ad1-196cbe33f606
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58028710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_otp
_reset.58028710
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.437312162
Short name T509
Test name
Test status
Simulation time 38234100 ps
CPU time 13.4 seconds
Started Jul 22 05:32:52 PM PDT 24
Finished Jul 22 05:33:06 PM PDT 24
Peak memory 259208 kb
Host smart-6572142b-4d22-4b4c-ad33-fe9649ce9e9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437312162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.flash_ctrl_prog_reset.437312162
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.4196346796
Short name T786
Test name
Test status
Simulation time 31954700 ps
CPU time 31.34 seconds
Started Jul 22 05:32:59 PM PDT 24
Finished Jul 22 05:33:31 PM PDT 24
Peak memory 275612 kb
Host smart-eb134338-dfd9-4f19-ae7d-13cab526e09a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196346796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl
ash_ctrl_rw_evict.4196346796
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.1948167173
Short name T757
Test name
Test status
Simulation time 36198000 ps
CPU time 194.24 seconds
Started Jul 22 05:32:44 PM PDT 24
Finished Jul 22 05:35:59 PM PDT 24
Peak memory 278048 kb
Host smart-b0216801-cbd1-476d-9d1a-78de20ba68e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948167173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.1948167173
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.515880753
Short name T447
Test name
Test status
Simulation time 109072600 ps
CPU time 13.84 seconds
Started Jul 22 05:33:03 PM PDT 24
Finished Jul 22 05:33:17 PM PDT 24
Peak memory 258244 kb
Host smart-dc486f33-9a60-44f1-ad01-3fe08b302a36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515880753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.515880753
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.1837502786
Short name T896
Test name
Test status
Simulation time 28891500 ps
CPU time 13.54 seconds
Started Jul 22 05:33:06 PM PDT 24
Finished Jul 22 05:33:20 PM PDT 24
Peak memory 284272 kb
Host smart-def7054d-64c0-4360-a8a3-6a8092f1121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837502786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.1837502786
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.1605281515
Short name T859
Test name
Test status
Simulation time 4504551700 ps
CPU time 160.1 seconds
Started Jul 22 05:33:06 PM PDT 24
Finished Jul 22 05:35:47 PM PDT 24
Peak memory 262028 kb
Host smart-3df5c8c2-9324-4062-992f-5d23870eecbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605281515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.1605281515
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.3481895533
Short name T621
Test name
Test status
Simulation time 7935685600 ps
CPU time 193.56 seconds
Started Jul 22 05:33:04 PM PDT 24
Finished Jul 22 05:36:18 PM PDT 24
Peak memory 294004 kb
Host smart-6d3c0f94-73eb-4eca-a98b-18d022bcd87f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481895533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla
sh_ctrl_intr_rd.3481895533
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.3445403830
Short name T910
Test name
Test status
Simulation time 174517772800 ps
CPU time 379.7 seconds
Started Jul 22 05:33:03 PM PDT 24
Finished Jul 22 05:39:24 PM PDT 24
Peak memory 292128 kb
Host smart-fa0955bc-d400-4e0b-b2c9-af08bba80a4c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445403830 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.3445403830
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.1514732432
Short name T1065
Test name
Test status
Simulation time 37658700 ps
CPU time 130.58 seconds
Started Jul 22 05:34:50 PM PDT 24
Finished Jul 22 05:37:02 PM PDT 24
Peak memory 261196 kb
Host smart-70afaa86-b752-4f02-a53e-014a3ea95a19
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514732432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.1514732432
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.3730510687
Short name T613
Test name
Test status
Simulation time 601174400 ps
CPU time 24.41 seconds
Started Jul 22 05:33:04 PM PDT 24
Finished Jul 22 05:33:29 PM PDT 24
Peak memory 259484 kb
Host smart-a4b4e904-fa8d-40b5-a44e-b0ae81457ff5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730510687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.flash_ctrl_prog_reset.3730510687
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.2149188198
Short name T352
Test name
Test status
Simulation time 52302000 ps
CPU time 31.07 seconds
Started Jul 22 05:33:04 PM PDT 24
Finished Jul 22 05:33:36 PM PDT 24
Peak memory 273212 kb
Host smart-9f6c7b73-18bc-4989-b214-d77f38051062
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149188198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl
ash_ctrl_rw_evict.2149188198
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.483801420
Short name T441
Test name
Test status
Simulation time 52329400 ps
CPU time 30.86 seconds
Started Jul 22 05:33:05 PM PDT 24
Finished Jul 22 05:33:36 PM PDT 24
Peak memory 275720 kb
Host smart-fb2f0546-bc03-44ac-a656-79aa9450f21a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483801420 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.483801420
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.4165662591
Short name T1108
Test name
Test status
Simulation time 1755393000 ps
CPU time 62.43 seconds
Started Jul 22 05:33:03 PM PDT 24
Finished Jul 22 05:34:06 PM PDT 24
Peak memory 264620 kb
Host smart-7a90e65d-cc96-40e4-b0ad-4b39949e100d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165662591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.4165662591
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.2367496968
Short name T1099
Test name
Test status
Simulation time 89514000 ps
CPU time 99.83 seconds
Started Jul 22 05:32:56 PM PDT 24
Finished Jul 22 05:34:36 PM PDT 24
Peak memory 276336 kb
Host smart-9452c1db-c513-4c84-8bcd-0ec08b171db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367496968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.2367496968
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.3485309537
Short name T424
Test name
Test status
Simulation time 38830800 ps
CPU time 13.36 seconds
Started Jul 22 05:33:14 PM PDT 24
Finished Jul 22 05:33:28 PM PDT 24
Peak memory 258308 kb
Host smart-f57c360f-8b6b-4164-81ac-2d1694c362b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485309537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
3485309537
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.351132956
Short name T494
Test name
Test status
Simulation time 15314200 ps
CPU time 13.55 seconds
Started Jul 22 05:33:12 PM PDT 24
Finished Jul 22 05:33:26 PM PDT 24
Peak memory 284460 kb
Host smart-37cd3a79-ed17-49e7-8337-dd2cff685ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351132956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.351132956
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.3797540454
Short name T698
Test name
Test status
Simulation time 27309000 ps
CPU time 22.01 seconds
Started Jul 22 05:33:15 PM PDT 24
Finished Jul 22 05:33:37 PM PDT 24
Peak memory 273568 kb
Host smart-756fb482-9473-4f59-a7fd-5abd0d50c174
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797540454 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.3797540454
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.3695101390
Short name T507
Test name
Test status
Simulation time 2931027000 ps
CPU time 91.2 seconds
Started Jul 22 05:34:51 PM PDT 24
Finished Jul 22 05:36:22 PM PDT 24
Peak memory 260944 kb
Host smart-fda1e48a-e772-46bc-b4ba-03c935791538
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695101390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.3695101390
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.869373930
Short name T984
Test name
Test status
Simulation time 6719520600 ps
CPU time 294.26 seconds
Started Jul 22 05:33:04 PM PDT 24
Finished Jul 22 05:37:59 PM PDT 24
Peak memory 284704 kb
Host smart-5a784e52-f073-419a-b085-dbfe460f4404
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869373930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flas
h_ctrl_intr_rd.869373930
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.2080586364
Short name T607
Test name
Test status
Simulation time 57327692000 ps
CPU time 254.14 seconds
Started Jul 22 05:33:13 PM PDT 24
Finished Jul 22 05:37:28 PM PDT 24
Peak memory 284996 kb
Host smart-7bcf0a55-c2cf-4d6e-8483-1b49b5d2d04c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080586364 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.2080586364
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.236527048
Short name T624
Test name
Test status
Simulation time 141132400 ps
CPU time 131.26 seconds
Started Jul 22 05:33:03 PM PDT 24
Finished Jul 22 05:35:15 PM PDT 24
Peak memory 261208 kb
Host smart-86228459-d64c-46b7-ba0c-da9266c11dcb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236527048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ot
p_reset.236527048
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.2321065159
Short name T391
Test name
Test status
Simulation time 70060200 ps
CPU time 13.76 seconds
Started Jul 22 05:33:04 PM PDT 24
Finished Jul 22 05:33:18 PM PDT 24
Peak memory 265216 kb
Host smart-28b5d37b-3a76-43b0-913e-cb5de3b29a55
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321065159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.flash_ctrl_prog_reset.2321065159
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.3606165118
Short name T218
Test name
Test status
Simulation time 66869900 ps
CPU time 31.15 seconds
Started Jul 22 05:33:17 PM PDT 24
Finished Jul 22 05:33:49 PM PDT 24
Peak memory 275576 kb
Host smart-0e60f6ff-e6f2-4ab8-a0b8-18b829871e60
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606165118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl
ash_ctrl_rw_evict.3606165118
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.2564679279
Short name T283
Test name
Test status
Simulation time 27358500 ps
CPU time 31.28 seconds
Started Jul 22 05:33:15 PM PDT 24
Finished Jul 22 05:33:47 PM PDT 24
Peak memory 268428 kb
Host smart-039bf1d9-0627-48fb-93ab-2bbec9af4ed0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564679279 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.2564679279
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.857491690
Short name T459
Test name
Test status
Simulation time 815020000 ps
CPU time 217.61 seconds
Started Jul 22 05:34:51 PM PDT 24
Finished Jul 22 05:38:29 PM PDT 24
Peak memory 278208 kb
Host smart-79b2da58-c85b-4799-87d5-38413a3206e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857491690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.857491690
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.3525657419
Short name T250
Test name
Test status
Simulation time 28025500 ps
CPU time 13.49 seconds
Started Jul 22 05:33:28 PM PDT 24
Finished Jul 22 05:33:42 PM PDT 24
Peak memory 258300 kb
Host smart-7d22750e-c58f-46c4-9989-ec088941d57f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525657419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
3525657419
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.315937680
Short name T503
Test name
Test status
Simulation time 50490800 ps
CPU time 15.48 seconds
Started Jul 22 05:33:25 PM PDT 24
Finished Jul 22 05:33:41 PM PDT 24
Peak memory 274952 kb
Host smart-1386de5c-617e-46c1-aed9-7c523cd159e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315937680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.315937680
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.2713304694
Short name T144
Test name
Test status
Simulation time 70854300 ps
CPU time 21.92 seconds
Started Jul 22 05:33:30 PM PDT 24
Finished Jul 22 05:33:52 PM PDT 24
Peak memory 265484 kb
Host smart-d676e325-8074-4ba5-b149-12b924a057c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713304694 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.2713304694
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.1742817122
Short name T834
Test name
Test status
Simulation time 1275194900 ps
CPU time 53.86 seconds
Started Jul 22 05:33:14 PM PDT 24
Finished Jul 22 05:34:08 PM PDT 24
Peak memory 263412 kb
Host smart-24a71e24-66cc-4315-bb2f-b2907315d6e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742817122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.1742817122
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.3609524637
Short name T1037
Test name
Test status
Simulation time 2973219200 ps
CPU time 138.46 seconds
Started Jul 22 05:33:14 PM PDT 24
Finished Jul 22 05:35:33 PM PDT 24
Peak memory 295156 kb
Host smart-8afbd5f9-7c18-4ee4-b7a9-067265c0ae10
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609524637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.3609524637
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1000002633
Short name T742
Test name
Test status
Simulation time 241501079400 ps
CPU time 368.87 seconds
Started Jul 22 05:33:13 PM PDT 24
Finished Jul 22 05:39:22 PM PDT 24
Peak memory 292104 kb
Host smart-71950d22-2c7e-439a-8198-90690f7b8cac
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000002633 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1000002633
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.1377685822
Short name T396
Test name
Test status
Simulation time 210332600 ps
CPU time 130.16 seconds
Started Jul 22 05:34:50 PM PDT 24
Finished Jul 22 05:37:01 PM PDT 24
Peak memory 260196 kb
Host smart-9fb91e24-9188-49ba-8156-7ae4fa94cd15
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377685822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.1377685822
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.1102373358
Short name T811
Test name
Test status
Simulation time 25841900 ps
CPU time 14.72 seconds
Started Jul 22 05:33:15 PM PDT 24
Finished Jul 22 05:33:30 PM PDT 24
Peak memory 265316 kb
Host smart-0d7e6132-7a47-4b31-af3c-baa301bff869
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102373358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.flash_ctrl_prog_reset.1102373358
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.1371689892
Short name T358
Test name
Test status
Simulation time 28704100 ps
CPU time 31.54 seconds
Started Jul 22 05:33:15 PM PDT 24
Finished Jul 22 05:33:47 PM PDT 24
Peak memory 274620 kb
Host smart-6a550df2-28ec-49e0-8eb4-d0975a73d417
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371689892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl
ash_ctrl_rw_evict.1371689892
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.3730583349
Short name T401
Test name
Test status
Simulation time 375641900 ps
CPU time 54.59 seconds
Started Jul 22 05:33:29 PM PDT 24
Finished Jul 22 05:34:24 PM PDT 24
Peak memory 263172 kb
Host smart-7a97d625-1a2e-4ced-abc1-54b2619985a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730583349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.3730583349
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.628418477
Short name T1002
Test name
Test status
Simulation time 61039000 ps
CPU time 52.54 seconds
Started Jul 22 05:33:14 PM PDT 24
Finished Jul 22 05:34:07 PM PDT 24
Peak memory 271260 kb
Host smart-9873f02c-c809-4117-a49a-631cd867b274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628418477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.628418477
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.3143686333
Short name T662
Test name
Test status
Simulation time 107086500 ps
CPU time 13.83 seconds
Started Jul 22 05:33:24 PM PDT 24
Finished Jul 22 05:33:39 PM PDT 24
Peak memory 258408 kb
Host smart-f1f4beca-8aaa-404c-a8f2-4dc11e6d6eba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143686333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
3143686333
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.2223408668
Short name T753
Test name
Test status
Simulation time 38066800 ps
CPU time 15.91 seconds
Started Jul 22 05:33:24 PM PDT 24
Finished Jul 22 05:33:41 PM PDT 24
Peak memory 284412 kb
Host smart-db0dbc06-a707-4905-9ee5-b56f48197ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223408668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.2223408668
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.619381146
Short name T378
Test name
Test status
Simulation time 10914400 ps
CPU time 21.76 seconds
Started Jul 22 05:33:24 PM PDT 24
Finished Jul 22 05:33:46 PM PDT 24
Peak memory 273612 kb
Host smart-2eed02af-ed94-4658-a2bb-4f742307d175
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619381146 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.619381146
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.2067324461
Short name T472
Test name
Test status
Simulation time 2210208400 ps
CPU time 181.74 seconds
Started Jul 22 05:33:28 PM PDT 24
Finished Jul 22 05:36:31 PM PDT 24
Peak memory 261956 kb
Host smart-be72ab04-1473-448f-b574-5722e2b78711
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067324461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.2067324461
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.3634259242
Short name T902
Test name
Test status
Simulation time 2283571900 ps
CPU time 196.92 seconds
Started Jul 22 05:33:29 PM PDT 24
Finished Jul 22 05:36:46 PM PDT 24
Peak memory 293140 kb
Host smart-2e0d9a9e-4902-4097-a802-0c33914a4892
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634259242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_intr_rd.3634259242
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.2896328461
Short name T795
Test name
Test status
Simulation time 12398768000 ps
CPU time 271.71 seconds
Started Jul 22 05:33:24 PM PDT 24
Finished Jul 22 05:37:56 PM PDT 24
Peak memory 291108 kb
Host smart-2e043a04-0eee-499a-8d8a-49709707893e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896328461 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.2896328461
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.2565185587
Short name T200
Test name
Test status
Simulation time 47584700 ps
CPU time 132.5 seconds
Started Jul 22 05:33:24 PM PDT 24
Finished Jul 22 05:35:37 PM PDT 24
Peak memory 260152 kb
Host smart-82b7eaa9-530c-4571-90ac-e8ef335d7a8a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565185587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.2565185587
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.3244437178
Short name T563
Test name
Test status
Simulation time 32992100 ps
CPU time 13.91 seconds
Started Jul 22 05:33:25 PM PDT 24
Finished Jul 22 05:33:39 PM PDT 24
Peak memory 265364 kb
Host smart-45187eb6-7c27-4059-8750-8a5c55ccb428
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244437178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.flash_ctrl_prog_reset.3244437178
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.4056440087
Short name T27
Test name
Test status
Simulation time 43038300 ps
CPU time 31.02 seconds
Started Jul 22 05:33:26 PM PDT 24
Finished Jul 22 05:33:57 PM PDT 24
Peak memory 275580 kb
Host smart-3060ea71-f825-4a08-a65a-a908932c1fc9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056440087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl
ash_ctrl_rw_evict.4056440087
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1625363120
Short name T866
Test name
Test status
Simulation time 25942800 ps
CPU time 30.73 seconds
Started Jul 22 05:33:23 PM PDT 24
Finished Jul 22 05:33:54 PM PDT 24
Peak memory 268472 kb
Host smart-de6b8226-b425-4554-8b39-3dc4bc316668
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625363120 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.1625363120
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.585648353
Short name T423
Test name
Test status
Simulation time 14513021700 ps
CPU time 76.27 seconds
Started Jul 22 05:33:24 PM PDT 24
Finished Jul 22 05:34:41 PM PDT 24
Peak memory 263560 kb
Host smart-01848517-2136-40b6-8598-169f41c6d7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585648353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.585648353
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.1697518864
Short name T576
Test name
Test status
Simulation time 26368000 ps
CPU time 100.76 seconds
Started Jul 22 05:33:25 PM PDT 24
Finished Jul 22 05:35:07 PM PDT 24
Peak memory 275976 kb
Host smart-8ccea876-b862-4ecd-bc84-e5ca4f2b6f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697518864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.1697518864
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.1475442715
Short name T620
Test name
Test status
Simulation time 36935900 ps
CPU time 13.83 seconds
Started Jul 22 05:33:35 PM PDT 24
Finished Jul 22 05:33:49 PM PDT 24
Peak memory 258296 kb
Host smart-64d9b6ae-8304-4f13-9a0f-af8af4daefbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475442715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
1475442715
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.2350763947
Short name T790
Test name
Test status
Simulation time 12743100 ps
CPU time 21.75 seconds
Started Jul 22 05:33:36 PM PDT 24
Finished Jul 22 05:33:58 PM PDT 24
Peak memory 273460 kb
Host smart-079ca66d-0392-480f-acc3-9c0200db75ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350763947 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.2350763947
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.1446818259
Short name T831
Test name
Test status
Simulation time 3382198800 ps
CPU time 120.83 seconds
Started Jul 22 05:33:25 PM PDT 24
Finished Jul 22 05:35:26 PM PDT 24
Peak memory 262488 kb
Host smart-0e803657-f540-424c-b424-f1ed5511df52
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446818259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.1446818259
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.395375205
Short name T931
Test name
Test status
Simulation time 742627100 ps
CPU time 147.21 seconds
Started Jul 22 05:33:33 PM PDT 24
Finished Jul 22 05:36:00 PM PDT 24
Peak memory 294016 kb
Host smart-06fc1118-6a54-47f6-ac2f-944dba2c7ae7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395375205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flas
h_ctrl_intr_rd.395375205
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.628640276
Short name T663
Test name
Test status
Simulation time 24098676800 ps
CPU time 178.46 seconds
Started Jul 22 05:33:32 PM PDT 24
Finished Jul 22 05:36:31 PM PDT 24
Peak memory 293200 kb
Host smart-baff40e8-a1c8-40e6-8b5f-cc4407277eb4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628640276 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.628640276
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.934200654
Short name T913
Test name
Test status
Simulation time 74079900 ps
CPU time 133.29 seconds
Started Jul 22 05:33:24 PM PDT 24
Finished Jul 22 05:35:38 PM PDT 24
Peak memory 260308 kb
Host smart-6e1510f8-af26-4557-b051-d2f3d47df84e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934200654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_ot
p_reset.934200654
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.2520650432
Short name T879
Test name
Test status
Simulation time 5000725700 ps
CPU time 207.18 seconds
Started Jul 22 05:33:33 PM PDT 24
Finished Jul 22 05:37:01 PM PDT 24
Peak memory 265272 kb
Host smart-0cb01029-a04f-43fb-aab4-303d52da329c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520650432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.flash_ctrl_prog_reset.2520650432
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.1493698306
Short name T362
Test name
Test status
Simulation time 27912500 ps
CPU time 30.97 seconds
Started Jul 22 05:33:33 PM PDT 24
Finished Jul 22 05:34:05 PM PDT 24
Peak memory 273900 kb
Host smart-a27cd7a8-8379-479c-95c7-bd5ff8abb151
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493698306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.1493698306
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.2920594101
Short name T359
Test name
Test status
Simulation time 30113000 ps
CPU time 28.48 seconds
Started Jul 22 05:33:34 PM PDT 24
Finished Jul 22 05:34:03 PM PDT 24
Peak memory 275688 kb
Host smart-4c3856a6-03cf-4b1c-993e-808d93fde442
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920594101 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.2920594101
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.3764984068
Short name T1024
Test name
Test status
Simulation time 1597710200 ps
CPU time 66.38 seconds
Started Jul 22 05:33:33 PM PDT 24
Finished Jul 22 05:34:40 PM PDT 24
Peak memory 263616 kb
Host smart-2fe0a129-3852-4bb3-93bb-789a8a0b2cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764984068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.3764984068
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.3034003409
Short name T1105
Test name
Test status
Simulation time 92086200 ps
CPU time 76.18 seconds
Started Jul 22 05:33:25 PM PDT 24
Finished Jul 22 05:34:42 PM PDT 24
Peak memory 275548 kb
Host smart-d2af32ce-de36-4226-ba39-99f661fc0484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034003409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.3034003409
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.3531490152
Short name T539
Test name
Test status
Simulation time 156280400 ps
CPU time 13.41 seconds
Started Jul 22 05:27:25 PM PDT 24
Finished Jul 22 05:27:39 PM PDT 24
Peak memory 265272 kb
Host smart-9b379add-0a1c-40ea-9db7-940c02131af8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531490152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.3
531490152
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.201430255
Short name T978
Test name
Test status
Simulation time 37310600 ps
CPU time 13.87 seconds
Started Jul 22 05:27:26 PM PDT 24
Finished Jul 22 05:27:40 PM PDT 24
Peak memory 264900 kb
Host smart-c22420ab-b0c2-4087-a57c-30b48105e99f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201430255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
flash_ctrl_config_regwen.201430255
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.2410533410
Short name T383
Test name
Test status
Simulation time 44943700 ps
CPU time 15.47 seconds
Started Jul 22 05:27:18 PM PDT 24
Finished Jul 22 05:27:34 PM PDT 24
Peak memory 284472 kb
Host smart-d021a708-49eb-4e56-99c2-885f4a1a428d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410533410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.2410533410
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.2904350599
Short name T379
Test name
Test status
Simulation time 24821400 ps
CPU time 22.06 seconds
Started Jul 22 05:27:17 PM PDT 24
Finished Jul 22 05:27:40 PM PDT 24
Peak memory 273536 kb
Host smart-669e3e5b-4303-4f63-a43d-3c9aedf7be74
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904350599 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.2904350599
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.2391983213
Short name T181
Test name
Test status
Simulation time 5849663100 ps
CPU time 433.2 seconds
Started Jul 22 05:27:00 PM PDT 24
Finished Jul 22 05:34:13 PM PDT 24
Peak memory 263444 kb
Host smart-1d99427a-e351-4b83-8898-8e21985e6597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391983213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.2391983213
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.2979363507
Short name T1042
Test name
Test status
Simulation time 7521201400 ps
CPU time 2359.94 seconds
Started Jul 22 05:26:59 PM PDT 24
Finished Jul 22 06:06:19 PM PDT 24
Peak memory 262876 kb
Host smart-abcf501c-f70e-496e-8b62-ae5bce11be2d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2979363507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.2979363507
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.3103971072
Short name T84
Test name
Test status
Simulation time 1149600000 ps
CPU time 2240.07 seconds
Started Jul 22 05:27:03 PM PDT 24
Finished Jul 22 06:04:24 PM PDT 24
Peak memory 262428 kb
Host smart-eeaf030d-9f27-4031-9c0e-bdd63bb2766c
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103971072 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.3103971072
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.1740027988
Short name T214
Test name
Test status
Simulation time 10412527300 ps
CPU time 1141.95 seconds
Started Jul 22 05:27:00 PM PDT 24
Finished Jul 22 05:46:03 PM PDT 24
Peak memory 273376 kb
Host smart-cbe26c8d-6e22-40e7-a9fe-a4efc0423483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740027988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.1740027988
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.3573592309
Short name T605
Test name
Test status
Simulation time 600964300 ps
CPU time 29.41 seconds
Started Jul 22 05:27:03 PM PDT 24
Finished Jul 22 05:27:33 PM PDT 24
Peak memory 262564 kb
Host smart-8a61a989-deae-4f33-8548-c4f4499bbcbc
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573592309 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_fetch_code.3573592309
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.1434772615
Short name T986
Test name
Test status
Simulation time 351024900 ps
CPU time 39.12 seconds
Started Jul 22 05:27:17 PM PDT 24
Finished Jul 22 05:27:56 PM PDT 24
Peak memory 262840 kb
Host smart-80937bbe-7531-4b05-b5bb-ddbb1d4f85f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434772615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.1434772615
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.920868881
Short name T151
Test name
Test status
Simulation time 95237235800 ps
CPU time 2730.6 seconds
Started Jul 22 05:26:58 PM PDT 24
Finished Jul 22 06:12:29 PM PDT 24
Peak memory 262312 kb
Host smart-4d4b5e3a-781d-4930-b93a-25fbf64bb0be
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920868881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_full_mem_access.920868881
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.2476180433
Short name T78
Test name
Test status
Simulation time 311905428800 ps
CPU time 1831.79 seconds
Started Jul 22 05:29:18 PM PDT 24
Finished Jul 22 05:59:50 PM PDT 24
Peak memory 264068 kb
Host smart-994542c8-94c9-4186-a2b2-37d62a6400a0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476180433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.2476180433
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2433630383
Short name T544
Test name
Test status
Simulation time 10011932500 ps
CPU time 157.43 seconds
Started Jul 22 05:27:36 PM PDT 24
Finished Jul 22 05:30:14 PM PDT 24
Peak memory 396796 kb
Host smart-1d845f55-287a-440f-a593-53dc32e6b56c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433630383 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.2433630383
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.2075916181
Short name T341
Test name
Test status
Simulation time 15353900 ps
CPU time 13.46 seconds
Started Jul 22 05:27:30 PM PDT 24
Finished Jul 22 05:27:44 PM PDT 24
Peak memory 260204 kb
Host smart-2c2614c0-965b-4556-9ba1-f756f8b87eb9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075916181 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.2075916181
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.578412359
Short name T1025
Test name
Test status
Simulation time 160193046500 ps
CPU time 925.95 seconds
Started Jul 22 05:28:25 PM PDT 24
Finished Jul 22 05:43:52 PM PDT 24
Peak memory 262092 kb
Host smart-7384c3fb-3589-43d0-bf0b-2442f76f6e4c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578412359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_hw_rma_reset.578412359
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.465276809
Short name T832
Test name
Test status
Simulation time 4107606800 ps
CPU time 123.35 seconds
Started Jul 22 05:29:18 PM PDT 24
Finished Jul 22 05:31:21 PM PDT 24
Peak memory 263352 kb
Host smart-17fa2f7e-aa72-4bca-a8fa-999a7a89bb60
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465276809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw
_sec_otp.465276809
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.2568790362
Short name T736
Test name
Test status
Simulation time 8414242700 ps
CPU time 153.4 seconds
Started Jul 22 05:27:08 PM PDT 24
Finished Jul 22 05:29:41 PM PDT 24
Peak memory 292964 kb
Host smart-d20e8385-89c2-4b4e-b8d6-3ea1edfd5791
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568790362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_intr_rd.2568790362
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.955979956
Short name T794
Test name
Test status
Simulation time 9089051900 ps
CPU time 267.98 seconds
Started Jul 22 05:27:14 PM PDT 24
Finished Jul 22 05:31:42 PM PDT 24
Peak memory 293944 kb
Host smart-f949517a-5fbd-4e26-8c96-b5dd243a3da4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955979956 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.955979956
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.1723903379
Short name T518
Test name
Test status
Simulation time 9710721900 ps
CPU time 61.28 seconds
Started Jul 22 05:27:09 PM PDT 24
Finished Jul 22 05:28:11 PM PDT 24
Peak memory 260612 kb
Host smart-bb92c124-62d0-4f2c-ba59-b58d8b242726
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723903379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.1723903379
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3552198618
Short name T30
Test name
Test status
Simulation time 20027910700 ps
CPU time 167.81 seconds
Started Jul 22 05:27:13 PM PDT 24
Finished Jul 22 05:30:02 PM PDT 24
Peak memory 260352 kb
Host smart-22c423b1-6e73-4aa6-886d-035c270ce14e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355
2198618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.3552198618
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.185609561
Short name T299
Test name
Test status
Simulation time 5700172100 ps
CPU time 87.82 seconds
Started Jul 22 05:26:59 PM PDT 24
Finished Jul 22 05:28:27 PM PDT 24
Peak memory 263520 kb
Host smart-05527f54-007e-49b5-b931-635c199f8fbd
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185609561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.185609561
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.4067762815
Short name T184
Test name
Test status
Simulation time 26660200 ps
CPU time 13.5 seconds
Started Jul 22 05:27:29 PM PDT 24
Finished Jul 22 05:27:43 PM PDT 24
Peak memory 264892 kb
Host smart-19a63e72-4bd0-4789-951c-bb4883139154
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067762815 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.4067762815
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.1909633175
Short name T131
Test name
Test status
Simulation time 21317610600 ps
CPU time 271.28 seconds
Started Jul 22 05:27:00 PM PDT 24
Finished Jul 22 05:31:32 PM PDT 24
Peak memory 274836 kb
Host smart-3c29a4d4-d0b0-4909-9f69-3f90ddd740f0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909633175 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.1909633175
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.4139621782
Short name T1080
Test name
Test status
Simulation time 73049100 ps
CPU time 131.51 seconds
Started Jul 22 05:27:00 PM PDT 24
Finished Jul 22 05:29:12 PM PDT 24
Peak memory 261224 kb
Host smart-d3e5037e-9848-46ec-9c4b-cfba8a58c1c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139621782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.4139621782
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.1939899462
Short name T721
Test name
Test status
Simulation time 5354172600 ps
CPU time 230.45 seconds
Started Jul 22 05:27:13 PM PDT 24
Finished Jul 22 05:31:04 PM PDT 24
Peak memory 281708 kb
Host smart-4bfdc30a-d9d9-47be-89d4-609ac2b05a69
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939899462 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.1939899462
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.3421918125
Short name T64
Test name
Test status
Simulation time 25440000 ps
CPU time 14.61 seconds
Started Jul 22 05:27:26 PM PDT 24
Finished Jul 22 05:27:41 PM PDT 24
Peak memory 276916 kb
Host smart-8011e14b-56b9-4426-9803-5c0b9d0d2930
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3421918125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.3421918125
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.1079700351
Short name T230
Test name
Test status
Simulation time 163574800 ps
CPU time 147.98 seconds
Started Jul 22 05:28:24 PM PDT 24
Finished Jul 22 05:30:53 PM PDT 24
Peak memory 263152 kb
Host smart-8f9d333c-4654-4a39-9e39-993b622b59c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1079700351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.1079700351
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.1266642273
Short name T126
Test name
Test status
Simulation time 741550500 ps
CPU time 16.13 seconds
Started Jul 22 05:27:17 PM PDT 24
Finished Jul 22 05:27:33 PM PDT 24
Peak memory 265332 kb
Host smart-847b995e-ff4b-4b6e-83c1-45d3484c74fc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266642273 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.1266642273
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.3245604805
Short name T228
Test name
Test status
Simulation time 68226500 ps
CPU time 14.25 seconds
Started Jul 22 05:27:15 PM PDT 24
Finished Jul 22 05:27:30 PM PDT 24
Peak memory 263052 kb
Host smart-2674dc69-816b-4288-adc5-37b527d89a00
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245604805 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.3245604805
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.1053322414
Short name T809
Test name
Test status
Simulation time 34177000 ps
CPU time 13.52 seconds
Started Jul 22 05:27:07 PM PDT 24
Finished Jul 22 05:27:20 PM PDT 24
Peak memory 265328 kb
Host smart-a5b5c788-657d-4c74-8b4c-02176e5edd7d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053322414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.flash_ctrl_prog_reset.1053322414
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.3148549416
Short name T148
Test name
Test status
Simulation time 289886100 ps
CPU time 305.27 seconds
Started Jul 22 05:26:52 PM PDT 24
Finished Jul 22 05:31:58 PM PDT 24
Peak memory 276536 kb
Host smart-80d60d04-51c3-4b72-bf5b-c3ffe8f14ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148549416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.3148549416
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.1605980781
Short name T62
Test name
Test status
Simulation time 202363800 ps
CPU time 100.92 seconds
Started Jul 22 05:26:53 PM PDT 24
Finished Jul 22 05:28:34 PM PDT 24
Peak memory 262568 kb
Host smart-5c30fd0e-9e03-43bf-9298-4418369ace94
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1605980781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.1605980781
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.3890394232
Short name T560
Test name
Test status
Simulation time 66701400 ps
CPU time 34.32 seconds
Started Jul 22 05:27:16 PM PDT 24
Finished Jul 22 05:27:51 PM PDT 24
Peak memory 275716 kb
Host smart-c4228359-8b6c-4047-9a2e-73599327bbd3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890394232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_re_evict.3890394232
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.2071579169
Short name T119
Test name
Test status
Simulation time 63198400 ps
CPU time 22.37 seconds
Started Jul 22 05:29:18 PM PDT 24
Finished Jul 22 05:29:40 PM PDT 24
Peak memory 264932 kb
Host smart-86b5690b-6a04-4ec1-b5e7-12c686a665dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071579169 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.2071579169
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.2799664220
Short name T515
Test name
Test status
Simulation time 22338800 ps
CPU time 23.18 seconds
Started Jul 22 05:27:08 PM PDT 24
Finished Jul 22 05:27:31 PM PDT 24
Peak memory 265360 kb
Host smart-c04e3b93-39ac-4d70-abfb-dfb77e3aae77
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799664220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.2799664220
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.2439814788
Short name T754
Test name
Test status
Simulation time 547577100 ps
CPU time 117.92 seconds
Started Jul 22 05:28:52 PM PDT 24
Finished Jul 22 05:30:50 PM PDT 24
Peak memory 291512 kb
Host smart-0b780c12-ab5b-49b9-a155-5070998c116e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439814788 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_ro.2439814788
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.3053152454
Short name T817
Test name
Test status
Simulation time 3980235100 ps
CPU time 521.72 seconds
Started Jul 22 05:27:08 PM PDT 24
Finished Jul 22 05:35:50 PM PDT 24
Peak memory 309540 kb
Host smart-9d48b8e4-153c-4896-b552-130dfdc42706
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053152454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_rw.3053152454
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.549136282
Short name T473
Test name
Test status
Simulation time 26438500 ps
CPU time 31.25 seconds
Started Jul 22 05:27:16 PM PDT 24
Finished Jul 22 05:27:48 PM PDT 24
Peak memory 275616 kb
Host smart-b0a47836-5384-4bdc-8a52-c330c7503a87
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549136282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_rw_evict.549136282
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.4273503958
Short name T659
Test name
Test status
Simulation time 72147800 ps
CPU time 31.8 seconds
Started Jul 22 05:27:16 PM PDT 24
Finished Jul 22 05:27:48 PM PDT 24
Peak memory 268464 kb
Host smart-e74b342e-9cfd-4743-bb9f-4845bb6231fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273503958 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.4273503958
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_serr.3981606111
Short name T785
Test name
Test status
Simulation time 16957713200 ps
CPU time 513.54 seconds
Started Jul 22 05:29:18 PM PDT 24
Finished Jul 22 05:37:52 PM PDT 24
Peak memory 320944 kb
Host smart-fc22060f-3b45-45e2-8d15-87a65247941f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981606111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_s
err.3981606111
Directory /workspace/3.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.3539719349
Short name T15
Test name
Test status
Simulation time 1327949000 ps
CPU time 4721.03 seconds
Started Jul 22 05:27:18 PM PDT 24
Finished Jul 22 06:46:00 PM PDT 24
Peak memory 287824 kb
Host smart-0bb18255-3b4b-47ca-8698-c3cec03fe967
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539719349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.3539719349
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.1647049646
Short name T415
Test name
Test status
Simulation time 1367248400 ps
CPU time 63.73 seconds
Started Jul 22 05:27:16 PM PDT 24
Finished Jul 22 05:28:20 PM PDT 24
Peak memory 263788 kb
Host smart-a7ce366f-5a15-44c3-969b-dcab2d8ccfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647049646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1647049646
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.117687700
Short name T208
Test name
Test status
Simulation time 551026900 ps
CPU time 69.68 seconds
Started Jul 22 05:27:07 PM PDT 24
Finished Jul 22 05:28:17 PM PDT 24
Peak memory 264960 kb
Host smart-8a269a72-6cf9-444c-acd3-b3e93b0daf01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117687700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_serr_address.117687700
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.3541884338
Short name T1063
Test name
Test status
Simulation time 34516800 ps
CPU time 165.41 seconds
Started Jul 22 05:28:24 PM PDT 24
Finished Jul 22 05:31:09 PM PDT 24
Peak memory 277152 kb
Host smart-00793369-b16e-4b9a-87b1-12472047ddcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541884338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.3541884338
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.2013928439
Short name T826
Test name
Test status
Simulation time 46473900 ps
CPU time 25.53 seconds
Started Jul 22 05:26:47 PM PDT 24
Finished Jul 22 05:27:13 PM PDT 24
Peak memory 259640 kb
Host smart-e11620fa-3800-48e5-bd49-df2d94b03c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013928439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.2013928439
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.865581621
Short name T1088
Test name
Test status
Simulation time 275409600 ps
CPU time 1186.42 seconds
Started Jul 22 05:27:17 PM PDT 24
Finished Jul 22 05:47:04 PM PDT 24
Peak memory 289428 kb
Host smart-37e35852-8163-4504-ac16-4c1aa237cdd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865581621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress
_all.865581621
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.2080715654
Short name T118
Test name
Test status
Simulation time 20560600 ps
CPU time 24.09 seconds
Started Jul 22 05:26:49 PM PDT 24
Finished Jul 22 05:27:13 PM PDT 24
Peak memory 259720 kb
Host smart-1647074a-35ad-4389-a014-01366846dcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080715654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.2080715654
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.2339396358
Short name T839
Test name
Test status
Simulation time 13448665500 ps
CPU time 213.97 seconds
Started Jul 22 05:27:32 PM PDT 24
Finished Jul 22 05:31:06 PM PDT 24
Peak memory 260112 kb
Host smart-7ea05b84-f080-4929-ba4a-b1c664431298
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339396358 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_wo.2339396358
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.4244616613
Short name T582
Test name
Test status
Simulation time 26477200 ps
CPU time 15.88 seconds
Started Jul 22 05:33:42 PM PDT 24
Finished Jul 22 05:33:58 PM PDT 24
Peak memory 274820 kb
Host smart-97eed060-a744-4968-8e57-6d2c26680eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244616613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.4244616613
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.555884687
Short name T321
Test name
Test status
Simulation time 60896400 ps
CPU time 21.9 seconds
Started Jul 22 05:33:43 PM PDT 24
Finished Jul 22 05:34:06 PM PDT 24
Peak memory 273528 kb
Host smart-adfa1245-eef5-4d79-a3f6-fd357acc3e1c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555884687 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.555884687
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.4122965745
Short name T328
Test name
Test status
Simulation time 7681599100 ps
CPU time 152.31 seconds
Started Jul 22 05:33:32 PM PDT 24
Finished Jul 22 05:36:05 PM PDT 24
Peak memory 263388 kb
Host smart-c33f2ef4-d2b6-4566-91f8-ed6732d9efe7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122965745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.4122965745
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.2465417985
Short name T592
Test name
Test status
Simulation time 3752130500 ps
CPU time 201.67 seconds
Started Jul 22 05:33:32 PM PDT 24
Finished Jul 22 05:36:54 PM PDT 24
Peak memory 284852 kb
Host smart-275d1523-ccdd-4d31-b581-e72e089c70b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465417985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.2465417985
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3482689626
Short name T610
Test name
Test status
Simulation time 33795953200 ps
CPU time 267.46 seconds
Started Jul 22 05:33:36 PM PDT 24
Finished Jul 22 05:38:03 PM PDT 24
Peak memory 290920 kb
Host smart-fbf45a3e-09e6-4bd5-bf14-4adfe5263d0a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482689626 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.3482689626
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.3321045826
Short name T628
Test name
Test status
Simulation time 76809400 ps
CPU time 132.67 seconds
Started Jul 22 05:33:34 PM PDT 24
Finished Jul 22 05:35:47 PM PDT 24
Peak memory 260088 kb
Host smart-9c27edf5-8b57-49c6-8c6b-7e63287ce2de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321045826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.3321045826
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.2483043962
Short name T290
Test name
Test status
Simulation time 28450100 ps
CPU time 31.22 seconds
Started Jul 22 05:33:34 PM PDT 24
Finished Jul 22 05:34:06 PM PDT 24
Peak memory 275588 kb
Host smart-3d01c3c1-4cf3-4a19-9ccd-d7bed33c69e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483043962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.2483043962
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.4069288534
Short name T779
Test name
Test status
Simulation time 140840000 ps
CPU time 31.41 seconds
Started Jul 22 05:33:42 PM PDT 24
Finished Jul 22 05:34:14 PM PDT 24
Peak memory 267448 kb
Host smart-114e6f5e-7beb-4693-ad34-f588ca9bfb63
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069288534 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.4069288534
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.3066512333
Short name T530
Test name
Test status
Simulation time 369531500 ps
CPU time 58.24 seconds
Started Jul 22 05:34:43 PM PDT 24
Finished Jul 22 05:35:42 PM PDT 24
Peak memory 265116 kb
Host smart-65ab0733-7075-4faf-a971-2ec5cd0a9a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066512333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.3066512333
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.3188970120
Short name T857
Test name
Test status
Simulation time 39227500 ps
CPU time 194.02 seconds
Started Jul 22 05:33:33 PM PDT 24
Finished Jul 22 05:36:48 PM PDT 24
Peak memory 281236 kb
Host smart-f88baa55-06a7-406a-bea6-aaae5a4c409b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188970120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.3188970120
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.3172381299
Short name T475
Test name
Test status
Simulation time 35557500 ps
CPU time 13.74 seconds
Started Jul 22 05:33:42 PM PDT 24
Finished Jul 22 05:33:57 PM PDT 24
Peak memory 258248 kb
Host smart-365d117d-bb4b-441c-a627-810006c58927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172381299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
3172381299
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.3726774493
Short name T1035
Test name
Test status
Simulation time 77639800 ps
CPU time 13.46 seconds
Started Jul 22 05:33:42 PM PDT 24
Finished Jul 22 05:33:56 PM PDT 24
Peak memory 284252 kb
Host smart-17159481-7360-49d0-bc92-d9989ca966f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726774493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3726774493
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.2426282207
Short name T678
Test name
Test status
Simulation time 35894600 ps
CPU time 21.81 seconds
Started Jul 22 05:33:44 PM PDT 24
Finished Jul 22 05:34:06 PM PDT 24
Peak memory 265616 kb
Host smart-2bb9c408-124c-434f-8ed5-a0b113fca833
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426282207 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.2426282207
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.860470411
Short name T1038
Test name
Test status
Simulation time 3029073600 ps
CPU time 249.43 seconds
Started Jul 22 05:33:43 PM PDT 24
Finished Jul 22 05:37:53 PM PDT 24
Peak memory 263396 kb
Host smart-97a77979-7b3c-4ded-a995-574756316da3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860470411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_h
w_sec_otp.860470411
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.1495614110
Short name T338
Test name
Test status
Simulation time 983304400 ps
CPU time 153.75 seconds
Started Jul 22 05:33:43 PM PDT 24
Finished Jul 22 05:36:17 PM PDT 24
Peak memory 291032 kb
Host smart-6517abde-323c-4edb-9398-4e131296563e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495614110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.1495614110
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.3261891703
Short name T669
Test name
Test status
Simulation time 11184403300 ps
CPU time 142.15 seconds
Started Jul 22 05:33:43 PM PDT 24
Finished Jul 22 05:36:06 PM PDT 24
Peak memory 292776 kb
Host smart-7b7716e5-05ee-4348-a796-827f3d0b17d9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261891703 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.3261891703
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.2496959752
Short name T770
Test name
Test status
Simulation time 86533700 ps
CPU time 133.45 seconds
Started Jul 22 05:33:46 PM PDT 24
Finished Jul 22 05:36:00 PM PDT 24
Peak memory 261160 kb
Host smart-8aaf4af4-e978-4e36-bdc5-99ce911c88d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496959752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.2496959752
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.166928891
Short name T164
Test name
Test status
Simulation time 44092500 ps
CPU time 31.15 seconds
Started Jul 22 05:33:42 PM PDT 24
Finished Jul 22 05:34:14 PM PDT 24
Peak memory 275752 kb
Host smart-c1c50cc9-6da7-40b6-b734-b4a5696ada0e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166928891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_rw_evict.166928891
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.689346059
Short name T1005
Test name
Test status
Simulation time 1123346000 ps
CPU time 66.4 seconds
Started Jul 22 05:33:48 PM PDT 24
Finished Jul 22 05:34:55 PM PDT 24
Peak memory 264692 kb
Host smart-021461c7-2f6d-4102-bb33-ca10d90723b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689346059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.689346059
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.934191696
Short name T1067
Test name
Test status
Simulation time 26785600 ps
CPU time 76.98 seconds
Started Jul 22 05:33:41 PM PDT 24
Finished Jul 22 05:34:59 PM PDT 24
Peak memory 275628 kb
Host smart-f8f02552-69d5-43f9-950c-5dc2ab5063eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934191696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.934191696
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.1138967416
Short name T838
Test name
Test status
Simulation time 66172800 ps
CPU time 13.37 seconds
Started Jul 22 05:33:52 PM PDT 24
Finished Jul 22 05:34:06 PM PDT 24
Peak memory 258312 kb
Host smart-ab390be4-c747-4ec6-ad75-c05be3c5a29d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138967416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
1138967416
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.155772482
Short name T488
Test name
Test status
Simulation time 54836500 ps
CPU time 13.71 seconds
Started Jul 22 05:33:54 PM PDT 24
Finished Jul 22 05:34:08 PM PDT 24
Peak memory 284508 kb
Host smart-c7a0e6fa-49be-417a-87e7-a34576719110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155772482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.155772482
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.15042461
Short name T1085
Test name
Test status
Simulation time 13488600 ps
CPU time 21.09 seconds
Started Jul 22 05:33:55 PM PDT 24
Finished Jul 22 05:34:17 PM PDT 24
Peak memory 273544 kb
Host smart-999c6058-095c-46a3-865e-bf9952e91202
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15042461 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.flash_ctrl_disable.15042461
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.3198051151
Short name T453
Test name
Test status
Simulation time 4200466700 ps
CPU time 121.61 seconds
Started Jul 22 05:33:43 PM PDT 24
Finished Jul 22 05:35:45 PM PDT 24
Peak memory 262860 kb
Host smart-218c62ff-d044-4e58-b960-ba7c78691ba3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198051151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.3198051151
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.2170073253
Short name T337
Test name
Test status
Simulation time 2118327400 ps
CPU time 228.11 seconds
Started Jul 22 05:33:53 PM PDT 24
Finished Jul 22 05:37:41 PM PDT 24
Peak memory 291468 kb
Host smart-554b8394-763a-4d19-8848-f2d1ad72c05c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170073253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.2170073253
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.4188969835
Short name T797
Test name
Test status
Simulation time 23973309800 ps
CPU time 173.53 seconds
Started Jul 22 05:33:52 PM PDT 24
Finished Jul 22 05:36:46 PM PDT 24
Peak memory 294128 kb
Host smart-8fe5bbb6-0d89-4a8a-868d-205dc00c4fd4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188969835 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.4188969835
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.1973357617
Short name T528
Test name
Test status
Simulation time 141493700 ps
CPU time 131.03 seconds
Started Jul 22 05:33:43 PM PDT 24
Finished Jul 22 05:35:54 PM PDT 24
Peak memory 260308 kb
Host smart-80fde0cc-b32b-4c9f-abca-b61128aeab7b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973357617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o
tp_reset.1973357617
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.4276212336
Short name T289
Test name
Test status
Simulation time 41544900 ps
CPU time 31.18 seconds
Started Jul 22 05:33:55 PM PDT 24
Finished Jul 22 05:34:27 PM PDT 24
Peak memory 267408 kb
Host smart-b3752d98-7f2a-4975-af2e-b5e8f454da7c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276212336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl
ash_ctrl_rw_evict.4276212336
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.3309463069
Short name T1043
Test name
Test status
Simulation time 29008300 ps
CPU time 31.11 seconds
Started Jul 22 05:33:52 PM PDT 24
Finished Jul 22 05:34:24 PM PDT 24
Peak memory 275584 kb
Host smart-6ca00c38-9bc6-4af4-b789-ee3b52b7aaba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309463069 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.3309463069
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.3730548420
Short name T611
Test name
Test status
Simulation time 584827100 ps
CPU time 70.92 seconds
Started Jul 22 05:33:53 PM PDT 24
Finished Jul 22 05:35:05 PM PDT 24
Peak memory 264908 kb
Host smart-d6ebb9f0-2596-4728-9f83-06ff95419a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730548420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3730548420
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.840162119
Short name T232
Test name
Test status
Simulation time 54302600 ps
CPU time 52.32 seconds
Started Jul 22 05:33:44 PM PDT 24
Finished Jul 22 05:34:36 PM PDT 24
Peak memory 271256 kb
Host smart-8ee0b9ba-0657-41b3-bf04-e315e3e5b712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840162119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.840162119
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.1485939587
Short name T606
Test name
Test status
Simulation time 166186800 ps
CPU time 13.83 seconds
Started Jul 22 05:34:05 PM PDT 24
Finished Jul 22 05:34:19 PM PDT 24
Peak memory 258300 kb
Host smart-3524adac-a1b3-481c-8679-af7153456962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485939587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
1485939587
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.3717436189
Short name T111
Test name
Test status
Simulation time 23617800 ps
CPU time 13.64 seconds
Started Jul 22 05:34:03 PM PDT 24
Finished Jul 22 05:34:18 PM PDT 24
Peak memory 274860 kb
Host smart-214384df-1b25-4bc5-ac82-fc24b3ea0dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717436189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.3717436189
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.3475009714
Short name T466
Test name
Test status
Simulation time 16022500 ps
CPU time 20.7 seconds
Started Jul 22 05:33:52 PM PDT 24
Finished Jul 22 05:34:13 PM PDT 24
Peak memory 273612 kb
Host smart-719dc968-f307-46e4-b6e4-6511ee9397f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475009714 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.3475009714
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.3325284520
Short name T889
Test name
Test status
Simulation time 4843796600 ps
CPU time 95.75 seconds
Started Jul 22 05:33:52 PM PDT 24
Finished Jul 22 05:35:29 PM PDT 24
Peak memory 263388 kb
Host smart-8996d6d1-80c1-46f4-8380-370eb8e50560
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325284520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.3325284520
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.73466318
Short name T34
Test name
Test status
Simulation time 10378768100 ps
CPU time 144.65 seconds
Started Jul 22 05:34:43 PM PDT 24
Finished Jul 22 05:37:09 PM PDT 24
Peak memory 294192 kb
Host smart-480c41e2-f912-4197-8610-8e157d39f635
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73466318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash
_ctrl_intr_rd.73466318
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.2238199282
Short name T755
Test name
Test status
Simulation time 12325677500 ps
CPU time 165.02 seconds
Started Jul 22 05:33:53 PM PDT 24
Finished Jul 22 05:36:39 PM PDT 24
Peak memory 292648 kb
Host smart-09ff5a0a-7a56-437a-a4bc-5886529b17a1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238199282 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.2238199282
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.3068144740
Short name T578
Test name
Test status
Simulation time 43504100 ps
CPU time 134.91 seconds
Started Jul 22 05:33:53 PM PDT 24
Finished Jul 22 05:36:09 PM PDT 24
Peak memory 261272 kb
Host smart-ed306caf-2c20-4765-9c95-3baf73462f0e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068144740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.3068144740
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.2913510479
Short name T627
Test name
Test status
Simulation time 79667700 ps
CPU time 31.4 seconds
Started Jul 22 05:33:55 PM PDT 24
Finished Jul 22 05:34:27 PM PDT 24
Peak memory 275600 kb
Host smart-77c1690e-4600-4143-a856-12f2692673a1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913510479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.2913510479
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.707645763
Short name T448
Test name
Test status
Simulation time 37801100 ps
CPU time 31.27 seconds
Started Jul 22 05:33:53 PM PDT 24
Finished Jul 22 05:34:25 PM PDT 24
Peak memory 275688 kb
Host smart-1ab832e8-7ab1-4c99-b709-8a81a50f1e42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707645763 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.707645763
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.2637443431
Short name T400
Test name
Test status
Simulation time 2785119100 ps
CPU time 84.51 seconds
Started Jul 22 05:33:53 PM PDT 24
Finished Jul 22 05:35:18 PM PDT 24
Peak memory 262100 kb
Host smart-be68a0dd-45c4-4b1f-9b21-24b34469e011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637443431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.2637443431
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.2866972921
Short name T42
Test name
Test status
Simulation time 48234700 ps
CPU time 146.76 seconds
Started Jul 22 05:33:54 PM PDT 24
Finished Jul 22 05:36:21 PM PDT 24
Peak memory 279068 kb
Host smart-a4883cd8-8f7e-47d1-a00b-c4feffd8ac40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866972921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.2866972921
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.462074792
Short name T680
Test name
Test status
Simulation time 44057400 ps
CPU time 13.65 seconds
Started Jul 22 05:34:03 PM PDT 24
Finished Jul 22 05:34:18 PM PDT 24
Peak memory 265316 kb
Host smart-f25d9084-a828-43a4-9446-3bce9cac66db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462074792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.462074792
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.3019023478
Short name T322
Test name
Test status
Simulation time 53699100 ps
CPU time 15.68 seconds
Started Jul 22 05:34:06 PM PDT 24
Finished Jul 22 05:34:22 PM PDT 24
Peak memory 274892 kb
Host smart-9b2b2aea-23da-4150-9e33-1d52df5688c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019023478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.3019023478
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.3277408228
Short name T1013
Test name
Test status
Simulation time 27414600 ps
CPU time 21.69 seconds
Started Jul 22 05:34:04 PM PDT 24
Finished Jul 22 05:34:26 PM PDT 24
Peak memory 265460 kb
Host smart-13d50d0a-d2c1-4c68-bd3a-78152262795d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277408228 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.3277408228
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.3508675313
Short name T547
Test name
Test status
Simulation time 8574355900 ps
CPU time 153.95 seconds
Started Jul 22 05:34:03 PM PDT 24
Finished Jul 22 05:36:38 PM PDT 24
Peak memory 263224 kb
Host smart-3cba7ede-f293-4dde-b819-80f110a0736b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508675313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.3508675313
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.3352819251
Short name T276
Test name
Test status
Simulation time 1796266800 ps
CPU time 213.9 seconds
Started Jul 22 05:34:04 PM PDT 24
Finished Jul 22 05:37:39 PM PDT 24
Peak memory 291008 kb
Host smart-2b6065a6-4a11-44d8-907a-10a4af0e60bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352819251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_intr_rd.3352819251
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3493552998
Short name T676
Test name
Test status
Simulation time 23850703700 ps
CPU time 160.09 seconds
Started Jul 22 05:34:04 PM PDT 24
Finished Jul 22 05:36:44 PM PDT 24
Peak memory 293060 kb
Host smart-a6c2cfc0-6e82-4b57-ad23-f1fdab160789
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493552998 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.3493552998
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.2391833178
Short name T502
Test name
Test status
Simulation time 46514800 ps
CPU time 28.84 seconds
Started Jul 22 05:34:03 PM PDT 24
Finished Jul 22 05:34:32 PM PDT 24
Peak memory 275712 kb
Host smart-fe14f81c-a209-4307-806b-3d4291a92fa2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391833178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.2391833178
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.1532539238
Short name T589
Test name
Test status
Simulation time 42634500 ps
CPU time 31.48 seconds
Started Jul 22 05:34:02 PM PDT 24
Finished Jul 22 05:34:34 PM PDT 24
Peak memory 267420 kb
Host smart-977bdbcb-61b7-4dc3-a85e-2cc763dc578c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532539238 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.1532539238
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.2561405432
Short name T46
Test name
Test status
Simulation time 4608413200 ps
CPU time 76.82 seconds
Started Jul 22 05:34:03 PM PDT 24
Finished Jul 22 05:35:21 PM PDT 24
Peak memory 263172 kb
Host smart-f9e2b0c8-0692-4051-80d3-5653c36f8374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561405432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.2561405432
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.1258653908
Short name T385
Test name
Test status
Simulation time 34134000 ps
CPU time 98.46 seconds
Started Jul 22 05:34:03 PM PDT 24
Finished Jul 22 05:35:42 PM PDT 24
Peak memory 276392 kb
Host smart-a17869d5-1ca1-4626-a6b4-1499db2d3437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258653908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.1258653908
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.641790306
Short name T315
Test name
Test status
Simulation time 46203500 ps
CPU time 13.87 seconds
Started Jul 22 05:34:12 PM PDT 24
Finished Jul 22 05:34:27 PM PDT 24
Peak memory 258428 kb
Host smart-d306c102-6313-49dd-88dc-adce3a3cb388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641790306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.641790306
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.1547511714
Short name T117
Test name
Test status
Simulation time 25920700 ps
CPU time 15.56 seconds
Started Jul 22 05:34:03 PM PDT 24
Finished Jul 22 05:34:19 PM PDT 24
Peak memory 284436 kb
Host smart-7095a4e9-841d-42ba-8cd7-2c6b0316b991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547511714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.1547511714
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.3091893497
Short name T969
Test name
Test status
Simulation time 10335700 ps
CPU time 22.16 seconds
Started Jul 22 05:34:04 PM PDT 24
Finished Jul 22 05:34:27 PM PDT 24
Peak memory 273528 kb
Host smart-156d2044-d377-4229-a0b9-31bb9fbb0f1a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091893497 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.3091893497
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.3933319374
Short name T1004
Test name
Test status
Simulation time 5589771500 ps
CPU time 172.02 seconds
Started Jul 22 05:34:04 PM PDT 24
Finished Jul 22 05:36:56 PM PDT 24
Peak memory 263320 kb
Host smart-e4321e5c-8679-4a10-af53-1d133f25aa18
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933319374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.3933319374
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.2606730790
Short name T464
Test name
Test status
Simulation time 8047242900 ps
CPU time 140.3 seconds
Started Jul 22 05:34:06 PM PDT 24
Finished Jul 22 05:36:27 PM PDT 24
Peak memory 292620 kb
Host smart-03eb9e2a-0796-4007-93ed-3c5b053ef65a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606730790 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.2606730790
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.3034538847
Short name T105
Test name
Test status
Simulation time 40168500 ps
CPU time 134.45 seconds
Started Jul 22 05:34:03 PM PDT 24
Finished Jul 22 05:36:18 PM PDT 24
Peak memory 261168 kb
Host smart-96ae3459-5c3d-41d2-a811-aea34b35f50f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034538847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.3034538847
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.905450586
Short name T632
Test name
Test status
Simulation time 36316600 ps
CPU time 31.77 seconds
Started Jul 22 05:34:03 PM PDT 24
Finished Jul 22 05:34:36 PM PDT 24
Peak memory 270600 kb
Host smart-2b9f1bc9-5708-4af8-9050-0fc4044d56af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905450586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_rw_evict.905450586
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.1298601094
Short name T443
Test name
Test status
Simulation time 160033500 ps
CPU time 32.08 seconds
Started Jul 22 05:34:03 PM PDT 24
Finished Jul 22 05:34:35 PM PDT 24
Peak memory 275648 kb
Host smart-2f5de4e9-e2f5-401a-93e4-14aa07ee5dad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298601094 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.1298601094
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.3428413509
Short name T409
Test name
Test status
Simulation time 5605962800 ps
CPU time 73.32 seconds
Started Jul 22 05:34:03 PM PDT 24
Finished Jul 22 05:35:17 PM PDT 24
Peak memory 264152 kb
Host smart-84ebb7d6-4416-4f8b-8f42-a13e58d83d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428413509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.3428413509
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.2940112226
Short name T599
Test name
Test status
Simulation time 58580300 ps
CPU time 170.59 seconds
Started Jul 22 05:34:04 PM PDT 24
Finished Jul 22 05:36:55 PM PDT 24
Peak memory 273264 kb
Host smart-2164b21b-c70d-4f14-a7ad-a4af2367b1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940112226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.2940112226
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.2443763935
Short name T903
Test name
Test status
Simulation time 42622400 ps
CPU time 13.63 seconds
Started Jul 22 05:34:14 PM PDT 24
Finished Jul 22 05:34:27 PM PDT 24
Peak memory 258352 kb
Host smart-517859da-302b-4b87-ae1d-0d2439da16ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443763935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
2443763935
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.3627365111
Short name T679
Test name
Test status
Simulation time 64550800 ps
CPU time 15.75 seconds
Started Jul 22 05:34:14 PM PDT 24
Finished Jul 22 05:34:30 PM PDT 24
Peak memory 284248 kb
Host smart-60d7b247-e7de-48d6-877d-440227db9b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627365111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.3627365111
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.3605022951
Short name T398
Test name
Test status
Simulation time 18543000 ps
CPU time 20.48 seconds
Started Jul 22 05:34:13 PM PDT 24
Finished Jul 22 05:34:34 PM PDT 24
Peak memory 273672 kb
Host smart-cf52020f-094d-478c-9860-664936400eb3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605022951 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.3605022951
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.2035522991
Short name T710
Test name
Test status
Simulation time 2076856800 ps
CPU time 82.92 seconds
Started Jul 22 05:34:12 PM PDT 24
Finished Jul 22 05:35:35 PM PDT 24
Peak memory 261060 kb
Host smart-cd8d39ff-a498-4fc9-96b6-8b5af800f819
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035522991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.2035522991
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.2903520279
Short name T577
Test name
Test status
Simulation time 25653673700 ps
CPU time 251.86 seconds
Started Jul 22 05:34:13 PM PDT 24
Finished Jul 22 05:38:25 PM PDT 24
Peak memory 284816 kb
Host smart-93d2e114-1850-4624-ab9c-f915b907bf53
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903520279 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.2903520279
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.3363976632
Short name T748
Test name
Test status
Simulation time 372490400 ps
CPU time 129.14 seconds
Started Jul 22 05:35:11 PM PDT 24
Finished Jul 22 05:37:21 PM PDT 24
Peak memory 265260 kb
Host smart-506cd5a8-5728-4622-8824-c2b8d45c61fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363976632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.3363976632
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.1287338572
Short name T41
Test name
Test status
Simulation time 66139200 ps
CPU time 31.82 seconds
Started Jul 22 05:34:13 PM PDT 24
Finished Jul 22 05:34:45 PM PDT 24
Peak memory 268428 kb
Host smart-1f5824a3-c05f-4721-8bf8-6f6ca99ffdc1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287338572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.1287338572
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.3886000320
Short name T287
Test name
Test status
Simulation time 37864700 ps
CPU time 31.54 seconds
Started Jul 22 05:34:14 PM PDT 24
Finished Jul 22 05:34:46 PM PDT 24
Peak memory 268424 kb
Host smart-827baf61-f951-49fa-b6ae-9f5a1e53df71
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886000320 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.3886000320
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.3334421421
Short name T850
Test name
Test status
Simulation time 1150492300 ps
CPU time 67.86 seconds
Started Jul 22 05:34:16 PM PDT 24
Finished Jul 22 05:35:24 PM PDT 24
Peak memory 265140 kb
Host smart-851ef80a-fadd-451e-b347-7f0a462b10e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334421421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.3334421421
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.3762971293
Short name T555
Test name
Test status
Simulation time 7437135100 ps
CPU time 158.09 seconds
Started Jul 22 05:34:14 PM PDT 24
Finished Jul 22 05:36:52 PM PDT 24
Peak memory 281648 kb
Host smart-a29debce-211d-461a-8bad-dd54668a9419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762971293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.3762971293
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.3526563483
Short name T737
Test name
Test status
Simulation time 92242500 ps
CPU time 13.84 seconds
Started Jul 22 05:34:22 PM PDT 24
Finished Jul 22 05:34:36 PM PDT 24
Peak memory 258308 kb
Host smart-f5062ac1-34eb-4095-ba2d-aa1f03575d5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526563483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
3526563483
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.3655501890
Short name T449
Test name
Test status
Simulation time 16745000 ps
CPU time 16.06 seconds
Started Jul 22 05:34:21 PM PDT 24
Finished Jul 22 05:34:37 PM PDT 24
Peak memory 274872 kb
Host smart-665ba367-ccfd-46cd-86d1-88548c2dc55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655501890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.3655501890
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.3400355400
Short name T713
Test name
Test status
Simulation time 10577000 ps
CPU time 22.33 seconds
Started Jul 22 05:34:14 PM PDT 24
Finished Jul 22 05:34:37 PM PDT 24
Peak memory 273608 kb
Host smart-6fa32f25-ac28-4e71-929c-f978fe593052
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400355400 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.3400355400
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.988206851
Short name T316
Test name
Test status
Simulation time 1806184300 ps
CPU time 66.38 seconds
Started Jul 22 05:34:11 PM PDT 24
Finished Jul 22 05:35:18 PM PDT 24
Peak memory 263288 kb
Host smart-64a63982-9a52-404d-ae1c-b2e6c75d3b17
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988206851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_h
w_sec_otp.988206851
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.1889547236
Short name T856
Test name
Test status
Simulation time 7332492500 ps
CPU time 205.33 seconds
Started Jul 22 05:34:14 PM PDT 24
Finished Jul 22 05:37:40 PM PDT 24
Peak memory 284860 kb
Host smart-794ff10e-a78a-438a-80b5-a2fcf8c09daa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889547236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_intr_rd.1889547236
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.1474649345
Short name T37
Test name
Test status
Simulation time 50948880500 ps
CPU time 299.68 seconds
Started Jul 22 05:34:12 PM PDT 24
Finished Jul 22 05:39:13 PM PDT 24
Peak memory 291976 kb
Host smart-b8447f94-e058-44e6-abeb-d0dfc5341bc8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474649345 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.1474649345
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.2745653117
Short name T193
Test name
Test status
Simulation time 63303200 ps
CPU time 132.44 seconds
Started Jul 22 05:34:16 PM PDT 24
Finished Jul 22 05:36:29 PM PDT 24
Peak memory 261132 kb
Host smart-e55a46f0-2bdf-4ea9-91c5-e186ed33b7f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745653117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.2745653117
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.1412732782
Short name T649
Test name
Test status
Simulation time 29620300 ps
CPU time 31.14 seconds
Started Jul 22 05:34:14 PM PDT 24
Finished Jul 22 05:34:45 PM PDT 24
Peak memory 273676 kb
Host smart-4c40d043-28d4-4ecf-84ea-a42181b9f5ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412732782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.1412732782
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.2209368510
Short name T318
Test name
Test status
Simulation time 43479400 ps
CPU time 30.91 seconds
Started Jul 22 05:34:16 PM PDT 24
Finished Jul 22 05:34:47 PM PDT 24
Peak memory 274916 kb
Host smart-1555471a-0ebc-4bd4-b70a-b12586979e65
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209368510 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.2209368510
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.2963138495
Short name T312
Test name
Test status
Simulation time 5476133000 ps
CPU time 77.7 seconds
Started Jul 22 05:34:23 PM PDT 24
Finished Jul 22 05:35:41 PM PDT 24
Peak memory 263664 kb
Host smart-45ed5589-02af-4347-be0b-fe7cfbedfa64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963138495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.2963138495
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.3369051708
Short name T233
Test name
Test status
Simulation time 43945100 ps
CPU time 98.58 seconds
Started Jul 22 05:34:14 PM PDT 24
Finished Jul 22 05:35:53 PM PDT 24
Peak memory 277292 kb
Host smart-60da6cdb-56ad-4fc3-bbfb-353874ea0238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369051708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.3369051708
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.3898924417
Short name T762
Test name
Test status
Simulation time 51648200 ps
CPU time 14.2 seconds
Started Jul 22 05:34:21 PM PDT 24
Finished Jul 22 05:34:36 PM PDT 24
Peak memory 265288 kb
Host smart-0fe96965-2f6c-495c-a075-a986c5df8ccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898924417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
3898924417
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.3273956577
Short name T1054
Test name
Test status
Simulation time 28573200 ps
CPU time 15.71 seconds
Started Jul 22 05:34:20 PM PDT 24
Finished Jul 22 05:34:36 PM PDT 24
Peak memory 284652 kb
Host smart-58f0ec01-24c1-421c-ac35-09090dc35f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273956577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.3273956577
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.1799304731
Short name T640
Test name
Test status
Simulation time 11074200 ps
CPU time 21.79 seconds
Started Jul 22 05:34:22 PM PDT 24
Finished Jul 22 05:34:44 PM PDT 24
Peak memory 273532 kb
Host smart-618297ea-4c09-44b0-b296-84ab027b00f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799304731 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.1799304731
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.2481251807
Short name T99
Test name
Test status
Simulation time 6421254200 ps
CPU time 67.21 seconds
Started Jul 22 05:34:21 PM PDT 24
Finished Jul 22 05:35:29 PM PDT 24
Peak memory 261060 kb
Host smart-b287f0c4-086e-4622-9c73-52dc92792788
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481251807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.2481251807
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.92479312
Short name T36
Test name
Test status
Simulation time 4988827600 ps
CPU time 183.66 seconds
Started Jul 22 05:34:23 PM PDT 24
Finished Jul 22 05:37:27 PM PDT 24
Peak memory 284900 kb
Host smart-0e55fed7-b105-42ff-ba29-8ca4c495fb11
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92479312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash
_ctrl_intr_rd.92479312
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.286595641
Short name T479
Test name
Test status
Simulation time 11920757600 ps
CPU time 280.63 seconds
Started Jul 22 05:34:21 PM PDT 24
Finished Jul 22 05:39:02 PM PDT 24
Peak memory 289984 kb
Host smart-a08ab21f-dbdd-4837-ba89-b057da041613
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286595641 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.286595641
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.2912652417
Short name T921
Test name
Test status
Simulation time 69601800 ps
CPU time 133.15 seconds
Started Jul 22 05:34:23 PM PDT 24
Finished Jul 22 05:36:37 PM PDT 24
Peak memory 265324 kb
Host smart-4fb773d2-63ca-4b72-bfdd-87d6325d786b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912652417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.2912652417
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.1776393769
Short name T1049
Test name
Test status
Simulation time 49181800 ps
CPU time 31.01 seconds
Started Jul 22 05:34:22 PM PDT 24
Finished Jul 22 05:34:54 PM PDT 24
Peak memory 268532 kb
Host smart-87a30c1c-6419-4166-b655-c5abe9cc85cf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776393769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.1776393769
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.3389907022
Short name T819
Test name
Test status
Simulation time 28073400 ps
CPU time 30.95 seconds
Started Jul 22 05:34:23 PM PDT 24
Finished Jul 22 05:34:55 PM PDT 24
Peak memory 268564 kb
Host smart-51c43560-a713-40d5-b456-e7f54e9c21de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389907022 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.3389907022
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.547601182
Short name T404
Test name
Test status
Simulation time 8322585800 ps
CPU time 74.34 seconds
Started Jul 22 05:34:20 PM PDT 24
Finished Jul 22 05:35:35 PM PDT 24
Peak memory 263768 kb
Host smart-5fad75b1-bd2b-406d-92cc-ac356d8fa1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547601182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.547601182
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.3545278563
Short name T231
Test name
Test status
Simulation time 130988900 ps
CPU time 123.13 seconds
Started Jul 22 05:34:24 PM PDT 24
Finished Jul 22 05:36:28 PM PDT 24
Peak memory 276328 kb
Host smart-96198a10-407b-446d-b01f-1bef474f9480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545278563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3545278563
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.790477825
Short name T16
Test name
Test status
Simulation time 32997900 ps
CPU time 13.86 seconds
Started Jul 22 05:34:30 PM PDT 24
Finished Jul 22 05:34:44 PM PDT 24
Peak memory 265148 kb
Host smart-987da21e-f545-4f3d-8dfa-79d852481bde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790477825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.790477825
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.2053980184
Short name T769
Test name
Test status
Simulation time 21763400 ps
CPU time 13.4 seconds
Started Jul 22 05:34:32 PM PDT 24
Finished Jul 22 05:34:45 PM PDT 24
Peak memory 274928 kb
Host smart-902ca3a6-2cdb-45e0-b839-ef90d2e94e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053980184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.2053980184
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.560213562
Short name T13
Test name
Test status
Simulation time 11179400 ps
CPU time 21.79 seconds
Started Jul 22 05:34:28 PM PDT 24
Finished Jul 22 05:34:51 PM PDT 24
Peak memory 265568 kb
Host smart-568a5754-d2d0-4e64-bb79-c54f68779558
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560213562 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.560213562
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.1805094827
Short name T848
Test name
Test status
Simulation time 6949568200 ps
CPU time 127.51 seconds
Started Jul 22 05:34:24 PM PDT 24
Finished Jul 22 05:36:32 PM PDT 24
Peak memory 260916 kb
Host smart-c7fd0da0-a88f-4b7e-9048-89dd0db3422d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805094827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.1805094827
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.2803916168
Short name T890
Test name
Test status
Simulation time 1544285400 ps
CPU time 211.33 seconds
Started Jul 22 05:34:23 PM PDT 24
Finished Jul 22 05:37:55 PM PDT 24
Peak memory 290952 kb
Host smart-29fc198c-459c-4ec5-9c92-f7a99fdd55db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803916168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.2803916168
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.4257202723
Short name T165
Test name
Test status
Simulation time 14974605000 ps
CPU time 147.48 seconds
Started Jul 22 05:34:30 PM PDT 24
Finished Jul 22 05:36:58 PM PDT 24
Peak memory 293052 kb
Host smart-bc24ed24-3378-4130-9c04-204685a0edf3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257202723 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.4257202723
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.3534914551
Short name T191
Test name
Test status
Simulation time 193023300 ps
CPU time 130.85 seconds
Started Jul 22 05:34:24 PM PDT 24
Finished Jul 22 05:36:35 PM PDT 24
Peak memory 261268 kb
Host smart-38809224-911b-4653-8b8b-0965c96e7e7d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534914551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.3534914551
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.870430007
Short name T863
Test name
Test status
Simulation time 34032200 ps
CPU time 31.3 seconds
Started Jul 22 05:34:29 PM PDT 24
Finished Jul 22 05:35:01 PM PDT 24
Peak memory 275540 kb
Host smart-3585bcd4-107c-4b62-a318-228c93287b2b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870430007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_rw_evict.870430007
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.140220090
Short name T1039
Test name
Test status
Simulation time 27087200 ps
CPU time 28.85 seconds
Started Jul 22 05:34:28 PM PDT 24
Finished Jul 22 05:34:58 PM PDT 24
Peak memory 268480 kb
Host smart-10b40ff9-d147-4633-9afc-6e49dfba3f6d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140220090 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.140220090
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.230990618
Short name T414
Test name
Test status
Simulation time 2719019600 ps
CPU time 69.96 seconds
Started Jul 22 05:34:30 PM PDT 24
Finished Jul 22 05:35:40 PM PDT 24
Peak memory 264740 kb
Host smart-31766be0-1f04-4dda-912c-6b080b444b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230990618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.230990618
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.3154112029
Short name T542
Test name
Test status
Simulation time 80655800 ps
CPU time 124.04 seconds
Started Jul 22 05:35:09 PM PDT 24
Finished Jul 22 05:37:13 PM PDT 24
Peak memory 277516 kb
Host smart-84445d60-4ec9-4659-a992-3d39acf92a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154112029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.3154112029
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.837888131
Short name T720
Test name
Test status
Simulation time 65257500 ps
CPU time 13.82 seconds
Started Jul 22 05:27:59 PM PDT 24
Finished Jul 22 05:28:13 PM PDT 24
Peak memory 265232 kb
Host smart-7b8d2018-b73d-48c3-a8ef-6719b58213bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837888131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.837888131
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.2251256282
Short name T375
Test name
Test status
Simulation time 37954100 ps
CPU time 14.31 seconds
Started Jul 22 05:27:53 PM PDT 24
Finished Jul 22 05:28:08 PM PDT 24
Peak memory 261648 kb
Host smart-00e9193b-6dc1-40df-be85-b0ec7e2f0e27
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251256282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_config_regwen.2251256282
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.1662059320
Short name T956
Test name
Test status
Simulation time 24667200 ps
CPU time 15.78 seconds
Started Jul 22 05:27:55 PM PDT 24
Finished Jul 22 05:28:11 PM PDT 24
Peak memory 274992 kb
Host smart-47faf703-1169-4c48-95dc-197da0afcc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662059320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.1662059320
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.1862553782
Short name T1001
Test name
Test status
Simulation time 46443500 ps
CPU time 21.37 seconds
Started Jul 22 05:27:58 PM PDT 24
Finished Jul 22 05:28:20 PM PDT 24
Peak memory 273472 kb
Host smart-66f4b68f-1d02-4f4f-b51d-dd5c0ddd4009
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862553782 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.1862553782
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.3152089141
Short name T909
Test name
Test status
Simulation time 1450957600 ps
CPU time 378.13 seconds
Started Jul 22 05:27:30 PM PDT 24
Finished Jul 22 05:33:48 PM PDT 24
Peak memory 263464 kb
Host smart-55c1102f-6f34-4c29-ba1d-ea6de501c5bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3152089141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.3152089141
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.1595458835
Short name T898
Test name
Test status
Simulation time 6642439700 ps
CPU time 2465.65 seconds
Started Jul 22 05:27:36 PM PDT 24
Finished Jul 22 06:08:42 PM PDT 24
Peak memory 263016 kb
Host smart-3d7e4d2d-a757-479b-b44a-eb9294cf41b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1595458835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.1595458835
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.1808941841
Short name T1097
Test name
Test status
Simulation time 1016661300 ps
CPU time 3232.66 seconds
Started Jul 22 05:27:36 PM PDT 24
Finished Jul 22 06:21:29 PM PDT 24
Peak memory 264992 kb
Host smart-91571ecd-5453-4fec-9613-690e9efc1963
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808941841 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.1808941841
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.3158886179
Short name T588
Test name
Test status
Simulation time 502012200 ps
CPU time 867.23 seconds
Started Jul 22 05:27:38 PM PDT 24
Finished Jul 22 05:42:06 PM PDT 24
Peak memory 273352 kb
Host smart-57c02667-0239-426c-95ff-7cfc6c0a2431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158886179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.3158886179
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.2888410311
Short name T1015
Test name
Test status
Simulation time 468026700 ps
CPU time 25.46 seconds
Started Jul 22 05:27:37 PM PDT 24
Finished Jul 22 05:28:03 PM PDT 24
Peak memory 263744 kb
Host smart-e2649334-96b6-4863-b96b-fd10e5da2f44
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888410311 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_fetch_code.2888410311
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.366479915
Short name T821
Test name
Test status
Simulation time 81066197600 ps
CPU time 2597.36 seconds
Started Jul 22 05:27:36 PM PDT 24
Finished Jul 22 06:10:54 PM PDT 24
Peak memory 265188 kb
Host smart-ec78b10a-2afd-4b97-9b45-197d664cef2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366479915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct
rl_full_mem_access.366479915
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.2089154753
Short name T72
Test name
Test status
Simulation time 229799241200 ps
CPU time 2547.25 seconds
Started Jul 22 05:27:29 PM PDT 24
Finished Jul 22 06:09:57 PM PDT 24
Peak memory 265244 kb
Host smart-c70f45cf-0c5d-4ca0-9e7e-19daa7778f90
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089154753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.2089154753
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.2142081873
Short name T927
Test name
Test status
Simulation time 108563400 ps
CPU time 46.24 seconds
Started Jul 22 05:27:26 PM PDT 24
Finished Jul 22 05:28:13 PM PDT 24
Peak memory 262612 kb
Host smart-1c0ed068-8a23-49c8-9e2f-0726fbf6cc2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2142081873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.2142081873
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1856878268
Short name T294
Test name
Test status
Simulation time 10044238400 ps
CPU time 51.57 seconds
Started Jul 22 05:27:56 PM PDT 24
Finished Jul 22 05:28:48 PM PDT 24
Peak memory 265804 kb
Host smart-b3a7f5cd-20c2-45a2-932c-657922439722
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856878268 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.1856878268
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.3633340841
Short name T1102
Test name
Test status
Simulation time 15871800 ps
CPU time 13.43 seconds
Started Jul 22 05:27:57 PM PDT 24
Finished Jul 22 05:28:11 PM PDT 24
Peak memory 264956 kb
Host smart-e64c380a-d5dd-4693-bbfb-3a0cb9e20a13
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633340841 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.3633340841
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.418249630
Short name T574
Test name
Test status
Simulation time 80137600000 ps
CPU time 932.4 seconds
Started Jul 22 05:27:29 PM PDT 24
Finished Jul 22 05:43:02 PM PDT 24
Peak memory 265116 kb
Host smart-7b66f377-1d93-4f48-ad5d-5ee925addb2c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418249630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_hw_rma_reset.418249630
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.1978580895
Short name T440
Test name
Test status
Simulation time 3356704500 ps
CPU time 154.68 seconds
Started Jul 22 05:27:25 PM PDT 24
Finished Jul 22 05:30:00 PM PDT 24
Peak memory 263188 kb
Host smart-af8cdd83-271c-46f2-ab1c-c4a3839e6526
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978580895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.1978580895
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.3485724168
Short name T1010
Test name
Test status
Simulation time 7467394600 ps
CPU time 566.74 seconds
Started Jul 22 05:27:46 PM PDT 24
Finished Jul 22 05:37:13 PM PDT 24
Peak memory 334780 kb
Host smart-869d0cc9-32dc-4ec5-9b51-0d8b8cd6bf20
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485724168 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_integrity.3485724168
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.1901779342
Short name T512
Test name
Test status
Simulation time 6580438300 ps
CPU time 225.87 seconds
Started Jul 22 05:27:45 PM PDT 24
Finished Jul 22 05:31:31 PM PDT 24
Peak memory 284844 kb
Host smart-c0e546b5-6cc9-4f7d-afab-06046cc0f410
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901779342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.1901779342
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.2457410893
Short name T591
Test name
Test status
Simulation time 23771636000 ps
CPU time 149.07 seconds
Started Jul 22 05:27:47 PM PDT 24
Finished Jul 22 05:30:17 PM PDT 24
Peak memory 292884 kb
Host smart-5733df5d-afd3-402a-9af9-1b770f054dc3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457410893 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.2457410893
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.1190271418
Short name T523
Test name
Test status
Simulation time 1841689000 ps
CPU time 58.72 seconds
Started Jul 22 05:27:48 PM PDT 24
Finished Jul 22 05:28:47 PM PDT 24
Peak memory 261008 kb
Host smart-86abdceb-3aba-48b9-86c3-2fabec0f59d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190271418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.1190271418
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.210102672
Short name T298
Test name
Test status
Simulation time 999611700 ps
CPU time 86.8 seconds
Started Jul 22 05:27:37 PM PDT 24
Finished Jul 22 05:29:04 PM PDT 24
Peak memory 260536 kb
Host smart-21ed6eac-2e44-46b5-8600-909f35ac85ba
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210102672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.210102672
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.2589777870
Short name T1079
Test name
Test status
Simulation time 84297800 ps
CPU time 13.36 seconds
Started Jul 22 05:27:59 PM PDT 24
Finished Jul 22 05:28:12 PM PDT 24
Peak memory 259872 kb
Host smart-ce451d8b-06aa-42dc-908b-ab37715d3b92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589777870 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.2589777870
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.2119133835
Short name T134
Test name
Test status
Simulation time 7871981800 ps
CPU time 529.79 seconds
Started Jul 22 05:27:27 PM PDT 24
Finished Jul 22 05:36:17 PM PDT 24
Peak memory 274928 kb
Host smart-9b246370-2f93-40af-a85c-5b1fc470101f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119133835 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.2119133835
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.1532182059
Short name T712
Test name
Test status
Simulation time 75642900 ps
CPU time 110.41 seconds
Started Jul 22 05:27:26 PM PDT 24
Finished Jul 22 05:29:17 PM PDT 24
Peak memory 260120 kb
Host smart-d8b4b06a-4d6d-4c8a-8c5b-b9bb49f3700c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532182059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.1532182059
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.238952549
Short name T873
Test name
Test status
Simulation time 1368215500 ps
CPU time 213.48 seconds
Started Jul 22 05:27:46 PM PDT 24
Finished Jul 22 05:31:20 PM PDT 24
Peak memory 281832 kb
Host smart-74e99c1d-b365-4fdc-96a1-4d295045af42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238952549 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.238952549
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.1578149500
Short name T60
Test name
Test status
Simulation time 16644700 ps
CPU time 14.49 seconds
Started Jul 22 05:28:27 PM PDT 24
Finished Jul 22 05:28:43 PM PDT 24
Peak memory 276976 kb
Host smart-f1381dac-acab-49e6-a25c-5163d035f0f2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1578149500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.1578149500
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.1269388427
Short name T701
Test name
Test status
Simulation time 821477100 ps
CPU time 435.23 seconds
Started Jul 22 05:27:27 PM PDT 24
Finished Jul 22 05:34:43 PM PDT 24
Peak memory 263120 kb
Host smart-18c0437c-f8b3-4547-bd27-3a61c8469215
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1269388427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.1269388427
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.2542476108
Short name T656
Test name
Test status
Simulation time 40281800 ps
CPU time 13.65 seconds
Started Jul 22 05:28:18 PM PDT 24
Finished Jul 22 05:28:32 PM PDT 24
Peak memory 265324 kb
Host smart-bb3a5482-542c-4f90-9d30-793095ef0d43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542476108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.flash_ctrl_prog_reset.2542476108
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.332823128
Short name T549
Test name
Test status
Simulation time 386089300 ps
CPU time 926.74 seconds
Started Jul 22 05:27:26 PM PDT 24
Finished Jul 22 05:42:53 PM PDT 24
Peak memory 284644 kb
Host smart-fa525a90-74ff-4e46-b554-a788963f54cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332823128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.332823128
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.2807973752
Short name T1094
Test name
Test status
Simulation time 5726874800 ps
CPU time 144.16 seconds
Started Jul 22 05:27:30 PM PDT 24
Finished Jul 22 05:29:54 PM PDT 24
Peak memory 262588 kb
Host smart-d7fccaf9-ab4c-4fa9-b0ef-647445e71ef5
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2807973752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2807973752
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.3816052508
Short name T939
Test name
Test status
Simulation time 122549300 ps
CPU time 34.82 seconds
Started Jul 22 05:27:54 PM PDT 24
Finished Jul 22 05:28:29 PM PDT 24
Peak memory 267432 kb
Host smart-86decb28-64bc-4e36-9160-f2ac8c0ee7fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816052508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.3816052508
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.1035656
Short name T759
Test name
Test status
Simulation time 19714700 ps
CPU time 22.95 seconds
Started Jul 22 05:27:45 PM PDT 24
Finished Jul 22 05:28:09 PM PDT 24
Peak memory 265376 kb
Host smart-6b9311c3-d40d-4593-b3e2-de29717552d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035656 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.1035656
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.3485812119
Short name T120
Test name
Test status
Simulation time 90115900 ps
CPU time 22.13 seconds
Started Jul 22 05:27:45 PM PDT 24
Finished Jul 22 05:28:07 PM PDT 24
Peak memory 265336 kb
Host smart-e2b85ac0-15a5-474a-828a-b5e4cb7c0e94
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485812119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.3485812119
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.1363753990
Short name T983
Test name
Test status
Simulation time 1948224100 ps
CPU time 106.69 seconds
Started Jul 22 05:27:38 PM PDT 24
Finished Jul 22 05:29:25 PM PDT 24
Peak memory 289140 kb
Host smart-749d5b34-07cd-45f7-b5f7-1c6af4c13a49
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363753990 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_ro.1363753990
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.548974342
Short name T115
Test name
Test status
Simulation time 1575515600 ps
CPU time 180.57 seconds
Started Jul 22 05:27:47 PM PDT 24
Finished Jul 22 05:30:48 PM PDT 24
Peak memory 281680 kb
Host smart-f904a9f2-9024-4807-9104-0ff708393208
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
548974342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.548974342
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.1006605653
Short name T835
Test name
Test status
Simulation time 2320232500 ps
CPU time 133.59 seconds
Started Jul 22 05:27:46 PM PDT 24
Finished Jul 22 05:30:00 PM PDT 24
Peak memory 281836 kb
Host smart-e37a3711-f790-4b67-912e-25ae1dfe4f9c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006605653 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.1006605653
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.2864981649
Short name T465
Test name
Test status
Simulation time 14068967600 ps
CPU time 556.44 seconds
Started Jul 22 05:27:37 PM PDT 24
Finished Jul 22 05:36:54 PM PDT 24
Peak memory 310020 kb
Host smart-cfc9c663-69a7-4685-b28b-686165289674
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864981649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_rw.2864981649
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.4047448641
Short name T1064
Test name
Test status
Simulation time 159130600 ps
CPU time 33.11 seconds
Started Jul 22 05:27:46 PM PDT 24
Finished Jul 22 05:28:20 PM PDT 24
Peak memory 268520 kb
Host smart-8dcc0753-a3cc-4d14-822f-d61401c76cbb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047448641 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.4047448641
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.3498645364
Short name T161
Test name
Test status
Simulation time 2895854200 ps
CPU time 657.74 seconds
Started Jul 22 05:27:47 PM PDT 24
Finished Jul 22 05:38:45 PM PDT 24
Peak memory 320944 kb
Host smart-2f18ead2-7a4e-4d91-a274-7eafe4e99760
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498645364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_s
err.3498645364
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.3095509766
Short name T43
Test name
Test status
Simulation time 1548551200 ps
CPU time 4782.16 seconds
Started Jul 22 05:27:54 PM PDT 24
Finished Jul 22 06:47:37 PM PDT 24
Peak memory 286088 kb
Host smart-1a0cba29-7e2b-48d5-8618-c6b1c58a5189
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095509766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3095509766
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.3837552864
Short name T31
Test name
Test status
Simulation time 7743453900 ps
CPU time 59.99 seconds
Started Jul 22 05:27:56 PM PDT 24
Finished Jul 22 05:28:57 PM PDT 24
Peak memory 264684 kb
Host smart-fa65697f-e1d9-4208-be36-da1d4c46016f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837552864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.3837552864
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.287177737
Short name T615
Test name
Test status
Simulation time 1231572100 ps
CPU time 65.95 seconds
Started Jul 22 05:27:46 PM PDT 24
Finished Jul 22 05:28:53 PM PDT 24
Peak memory 273624 kb
Host smart-5d8b2043-ce09-45a7-a734-178f44e5dd8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287177737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_serr_address.287177737
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.3277786797
Short name T894
Test name
Test status
Simulation time 3068392300 ps
CPU time 79.47 seconds
Started Jul 22 05:27:46 PM PDT 24
Finished Jul 22 05:29:06 PM PDT 24
Peak memory 273516 kb
Host smart-c9e1e186-5711-4bfe-8cca-277b73cda3ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277786797 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_serr_counter.3277786797
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.3819362765
Short name T774
Test name
Test status
Simulation time 66716700 ps
CPU time 170.49 seconds
Started Jul 22 05:27:26 PM PDT 24
Finished Jul 22 05:30:17 PM PDT 24
Peak memory 269252 kb
Host smart-7b642f91-3cb6-4f3b-a1f5-6f0e7c0d425e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819362765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.3819362765
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.1330376092
Short name T875
Test name
Test status
Simulation time 18155400 ps
CPU time 25.81 seconds
Started Jul 22 05:29:18 PM PDT 24
Finished Jul 22 05:29:44 PM PDT 24
Peak memory 259652 kb
Host smart-5d587ae3-683e-4d03-b668-51354a1edf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330376092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.1330376092
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.1955318219
Short name T906
Test name
Test status
Simulation time 8454920300 ps
CPU time 1463.5 seconds
Started Jul 22 05:27:54 PM PDT 24
Finished Jul 22 05:52:18 PM PDT 24
Peak memory 288812 kb
Host smart-332a6cb3-8a00-4656-903e-6c099944fd5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955318219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.1955318219
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.2628744313
Short name T565
Test name
Test status
Simulation time 88511800 ps
CPU time 27.11 seconds
Started Jul 22 05:27:25 PM PDT 24
Finished Jul 22 05:27:53 PM PDT 24
Peak memory 262408 kb
Host smart-9689cb06-6b19-4b3f-9a7a-e48fc53df08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628744313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.2628744313
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.741438451
Short name T807
Test name
Test status
Simulation time 10401755600 ps
CPU time 189.83 seconds
Started Jul 22 05:28:12 PM PDT 24
Finished Jul 22 05:31:23 PM PDT 24
Peak memory 260104 kb
Host smart-f6b8562a-eace-4ec7-8c0c-2c9a1abd7d7d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741438451 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.flash_ctrl_wo.741438451
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.3746584253
Short name T840
Test name
Test status
Simulation time 85535300 ps
CPU time 13.57 seconds
Started Jul 22 05:34:30 PM PDT 24
Finished Jul 22 05:34:44 PM PDT 24
Peak memory 265240 kb
Host smart-371e1af7-71ef-42b9-90dc-26b0a248e567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746584253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
3746584253
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.1953929747
Short name T437
Test name
Test status
Simulation time 60766800 ps
CPU time 15.69 seconds
Started Jul 22 05:34:31 PM PDT 24
Finished Jul 22 05:34:47 PM PDT 24
Peak memory 274988 kb
Host smart-4856d017-6af7-4d39-97a3-c8128ad2ec92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953929747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.1953929747
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.1751519534
Short name T583
Test name
Test status
Simulation time 10555600 ps
CPU time 20.79 seconds
Started Jul 22 05:34:29 PM PDT 24
Finished Jul 22 05:34:50 PM PDT 24
Peak memory 265512 kb
Host smart-9da7420b-a145-4bc1-beb5-601c5b010678
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751519534 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.1751519534
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.4051248721
Short name T96
Test name
Test status
Simulation time 901314300 ps
CPU time 83.34 seconds
Started Jul 22 05:34:32 PM PDT 24
Finished Jul 22 05:35:56 PM PDT 24
Peak memory 260972 kb
Host smart-f005aa00-62a9-4121-8c14-44db96d06688
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051248721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.4051248721
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.2244671413
Short name T324
Test name
Test status
Simulation time 41273600 ps
CPU time 111 seconds
Started Jul 22 05:34:29 PM PDT 24
Finished Jul 22 05:36:21 PM PDT 24
Peak memory 260288 kb
Host smart-bc75069e-2c72-4e83-823c-7de333797629
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244671413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.2244671413
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.181015720
Short name T947
Test name
Test status
Simulation time 4710207800 ps
CPU time 81.01 seconds
Started Jul 22 05:34:33 PM PDT 24
Finished Jul 22 05:35:54 PM PDT 24
Peak memory 263708 kb
Host smart-a6eb604c-61f1-491e-a406-65a17ff86076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181015720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.181015720
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.1664553531
Short name T688
Test name
Test status
Simulation time 42609000 ps
CPU time 145.72 seconds
Started Jul 22 05:34:30 PM PDT 24
Finished Jul 22 05:36:56 PM PDT 24
Peak memory 277020 kb
Host smart-fef7b4e6-9910-4ca3-b0a8-65da9246e814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664553531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.1664553531
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.1716668922
Short name T982
Test name
Test status
Simulation time 76356300 ps
CPU time 14.17 seconds
Started Jul 22 05:34:40 PM PDT 24
Finished Jul 22 05:34:55 PM PDT 24
Peak memory 258328 kb
Host smart-a71447f0-3074-4af3-94cc-11dca923efb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716668922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
1716668922
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.1474881249
Short name T708
Test name
Test status
Simulation time 49139300 ps
CPU time 13.3 seconds
Started Jul 22 05:34:39 PM PDT 24
Finished Jul 22 05:34:53 PM PDT 24
Peak memory 274840 kb
Host smart-cabbaa35-ec90-45f0-96a1-c909c4ffa0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474881249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.1474881249
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.2202405040
Short name T1098
Test name
Test status
Simulation time 16930700 ps
CPU time 22.03 seconds
Started Jul 22 05:34:39 PM PDT 24
Finished Jul 22 05:35:02 PM PDT 24
Peak memory 273528 kb
Host smart-198562bb-e8ac-40a6-9cdf-66961bdc61ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202405040 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.2202405040
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.4177086868
Short name T1048
Test name
Test status
Simulation time 410081100 ps
CPU time 44.72 seconds
Started Jul 22 05:34:29 PM PDT 24
Finished Jul 22 05:35:15 PM PDT 24
Peak memory 263332 kb
Host smart-eda3590d-5835-4848-b4b4-83b8a7ad8402
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177086868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.4177086868
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.3579333587
Short name T195
Test name
Test status
Simulation time 77015000 ps
CPU time 112.41 seconds
Started Jul 22 05:34:31 PM PDT 24
Finished Jul 22 05:36:23 PM PDT 24
Peak memory 260092 kb
Host smart-0bdb5b9e-c4eb-44a5-bc94-6021a87cb0bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579333587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.3579333587
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.500024026
Short name T1093
Test name
Test status
Simulation time 1349590000 ps
CPU time 64.95 seconds
Started Jul 22 05:34:40 PM PDT 24
Finished Jul 22 05:35:45 PM PDT 24
Peak memory 263648 kb
Host smart-57a2b744-3232-4ff5-a60f-4e7b47c200c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500024026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.500024026
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.2176401131
Short name T1070
Test name
Test status
Simulation time 17892100 ps
CPU time 75.55 seconds
Started Jul 22 05:34:33 PM PDT 24
Finished Jul 22 05:35:48 PM PDT 24
Peak memory 276560 kb
Host smart-ae94220c-1b2a-467b-849d-b3f1abc8d52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176401131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.2176401131
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.867710391
Short name T504
Test name
Test status
Simulation time 44967400 ps
CPU time 13.29 seconds
Started Jul 22 05:39:38 PM PDT 24
Finished Jul 22 05:39:52 PM PDT 24
Peak memory 264964 kb
Host smart-4d26364a-456b-4b83-8f5a-11eb12fcadaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867710391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.867710391
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.2848878437
Short name T991
Test name
Test status
Simulation time 49388700 ps
CPU time 13.41 seconds
Started Jul 22 05:34:40 PM PDT 24
Finished Jul 22 05:34:54 PM PDT 24
Peak memory 274860 kb
Host smart-652ffeeb-0c84-4bfe-877d-96e4c33a4c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848878437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.2848878437
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.984908865
Short name T397
Test name
Test status
Simulation time 26663200 ps
CPU time 21.98 seconds
Started Jul 22 05:34:41 PM PDT 24
Finished Jul 22 05:35:04 PM PDT 24
Peak memory 273640 kb
Host smart-abb9ac38-3fc3-49fb-9b98-6d1a0327ba9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984908865 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.984908865
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.1885509712
Short name T1096
Test name
Test status
Simulation time 1701195900 ps
CPU time 38.49 seconds
Started Jul 22 05:34:41 PM PDT 24
Finished Jul 22 05:35:20 PM PDT 24
Peak memory 260132 kb
Host smart-6522a6d9-a243-40eb-bd4c-bf6780a230c6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885509712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.1885509712
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.2417828458
Short name T12
Test name
Test status
Simulation time 150801600 ps
CPU time 134.71 seconds
Started Jul 22 05:34:40 PM PDT 24
Finished Jul 22 05:36:55 PM PDT 24
Peak memory 261280 kb
Host smart-46b620b1-f503-4d61-a6d7-fd15edc78de4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417828458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.2417828458
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.939171515
Short name T420
Test name
Test status
Simulation time 6672792600 ps
CPU time 74.28 seconds
Started Jul 22 05:34:41 PM PDT 24
Finished Jul 22 05:35:56 PM PDT 24
Peak memory 263732 kb
Host smart-2e1562e4-5544-4e7c-a7a1-ec7becb66b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939171515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.939171515
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.1505402602
Short name T719
Test name
Test status
Simulation time 46608300 ps
CPU time 125.25 seconds
Started Jul 22 05:34:40 PM PDT 24
Finished Jul 22 05:36:45 PM PDT 24
Peak memory 277584 kb
Host smart-4c627cd2-9d79-4558-abe1-819ccbd6e710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505402602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.1505402602
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.2010801005
Short name T814
Test name
Test status
Simulation time 152494700 ps
CPU time 13.86 seconds
Started Jul 22 05:34:40 PM PDT 24
Finished Jul 22 05:34:55 PM PDT 24
Peak memory 258312 kb
Host smart-300681f9-e587-4f43-b2a5-ab1af50ee7fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010801005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
2010801005
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.3485364189
Short name T706
Test name
Test status
Simulation time 31790100 ps
CPU time 16.03 seconds
Started Jul 22 05:34:42 PM PDT 24
Finished Jul 22 05:34:58 PM PDT 24
Peak memory 274868 kb
Host smart-c64739be-1714-4ba3-a94a-6555d72bbaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485364189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.3485364189
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.2674398766
Short name T323
Test name
Test status
Simulation time 30074700 ps
CPU time 21.95 seconds
Started Jul 22 05:34:39 PM PDT 24
Finished Jul 22 05:35:02 PM PDT 24
Peak memory 273696 kb
Host smart-1bb442cc-b70a-4226-a95e-a0dd017950e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674398766 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.2674398766
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.733781016
Short name T670
Test name
Test status
Simulation time 6602280000 ps
CPU time 135.67 seconds
Started Jul 22 05:34:43 PM PDT 24
Finished Jul 22 05:37:00 PM PDT 24
Peak memory 260948 kb
Host smart-8f528fa0-b609-4f4f-80aa-0031fc1c170d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733781016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_h
w_sec_otp.733781016
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.2293364237
Short name T1007
Test name
Test status
Simulation time 40125500 ps
CPU time 131.59 seconds
Started Jul 22 05:34:40 PM PDT 24
Finished Jul 22 05:36:53 PM PDT 24
Peak memory 264880 kb
Host smart-94be8e3b-f3ee-46de-ba12-ec275c1527b5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293364237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.2293364237
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.1758883371
Short name T405
Test name
Test status
Simulation time 2029202600 ps
CPU time 76.3 seconds
Started Jul 22 05:34:43 PM PDT 24
Finished Jul 22 05:35:59 PM PDT 24
Peak memory 263668 kb
Host smart-5e75f579-993b-470d-ba5e-1f17f6ef8c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758883371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.1758883371
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.3346595476
Short name T384
Test name
Test status
Simulation time 52212000 ps
CPU time 49.01 seconds
Started Jul 22 05:39:36 PM PDT 24
Finished Jul 22 05:40:26 PM PDT 24
Peak memory 271244 kb
Host smart-e24aec8e-da9a-4e65-8cdd-ab1e68f3e9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346595476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.3346595476
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.1486695062
Short name T554
Test name
Test status
Simulation time 44172000 ps
CPU time 13.84 seconds
Started Jul 22 05:34:48 PM PDT 24
Finished Jul 22 05:35:03 PM PDT 24
Peak memory 265288 kb
Host smart-5466630d-c597-422b-8b68-f8476207b72a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486695062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
1486695062
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.969630928
Short name T925
Test name
Test status
Simulation time 220336100 ps
CPU time 16.16 seconds
Started Jul 22 05:34:51 PM PDT 24
Finished Jul 22 05:35:07 PM PDT 24
Peak memory 274916 kb
Host smart-10bf18b5-20fa-441d-a978-c322293a8932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969630928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.969630928
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.3817702092
Short name T1078
Test name
Test status
Simulation time 25528100 ps
CPU time 21.89 seconds
Started Jul 22 05:34:49 PM PDT 24
Finished Jul 22 05:35:12 PM PDT 24
Peak memory 273532 kb
Host smart-ef5f34ba-e5d4-4c00-a2a6-62aad89d6564
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817702092 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.3817702092
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.1011091674
Short name T686
Test name
Test status
Simulation time 2264529200 ps
CPU time 88.86 seconds
Started Jul 22 05:34:49 PM PDT 24
Finished Jul 22 05:36:19 PM PDT 24
Peak memory 262780 kb
Host smart-202aea00-45e7-432d-a9f0-232abb548bb6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011091674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.1011091674
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.2611553450
Short name T637
Test name
Test status
Simulation time 145025600 ps
CPU time 131.24 seconds
Started Jul 22 05:34:49 PM PDT 24
Finished Jul 22 05:37:01 PM PDT 24
Peak memory 260264 kb
Host smart-f6001110-75de-4993-bbb7-b337018bf7e9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611553450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o
tp_reset.2611553450
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.3776254735
Short name T419
Test name
Test status
Simulation time 2210764000 ps
CPU time 81.63 seconds
Started Jul 22 05:34:48 PM PDT 24
Finished Jul 22 05:36:10 PM PDT 24
Peak memory 259676 kb
Host smart-6df058f0-f2c8-4985-9396-7fcd0116ba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776254735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.3776254735
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.587454633
Short name T451
Test name
Test status
Simulation time 130560000 ps
CPU time 169.15 seconds
Started Jul 22 05:34:49 PM PDT 24
Finished Jul 22 05:37:39 PM PDT 24
Peak memory 277424 kb
Host smart-578d1a2d-cda5-41d4-8107-148837266811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587454633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.587454633
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.861229651
Short name T1034
Test name
Test status
Simulation time 376341200 ps
CPU time 14.33 seconds
Started Jul 22 05:34:49 PM PDT 24
Finished Jul 22 05:35:03 PM PDT 24
Peak memory 265584 kb
Host smart-6e7ecfff-183b-4fbe-bb3f-731645c46910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861229651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.861229651
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.274513123
Short name T439
Test name
Test status
Simulation time 17156200 ps
CPU time 16.06 seconds
Started Jul 22 05:34:50 PM PDT 24
Finished Jul 22 05:35:07 PM PDT 24
Peak memory 275052 kb
Host smart-200640c0-609c-412a-b586-af5a3e644a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274513123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.274513123
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.1747118291
Short name T203
Test name
Test status
Simulation time 24872500 ps
CPU time 21.9 seconds
Started Jul 22 05:34:50 PM PDT 24
Finished Jul 22 05:35:13 PM PDT 24
Peak memory 273596 kb
Host smart-7105526f-7860-4e39-b0eb-1b9b559f8a5a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747118291 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.1747118291
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.779961377
Short name T327
Test name
Test status
Simulation time 3236078100 ps
CPU time 68.86 seconds
Started Jul 22 05:34:48 PM PDT 24
Finished Jul 22 05:35:57 PM PDT 24
Peak memory 262748 kb
Host smart-8c0ebc30-1b35-4ff5-af29-45a2e36f2313
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779961377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_h
w_sec_otp.779961377
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.3203812877
Short name T661
Test name
Test status
Simulation time 102604400 ps
CPU time 129.29 seconds
Started Jul 22 05:34:51 PM PDT 24
Finished Jul 22 05:37:01 PM PDT 24
Peak memory 260284 kb
Host smart-6ef7e78c-0dc0-4ef2-9c42-1c48abddb4b7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203812877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.3203812877
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.3536003157
Short name T893
Test name
Test status
Simulation time 6649678700 ps
CPU time 81.89 seconds
Started Jul 22 05:34:49 PM PDT 24
Finished Jul 22 05:36:11 PM PDT 24
Peak memory 263572 kb
Host smart-343f5c30-0181-458c-9a0b-ab748c6963e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536003157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.3536003157
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.3488285247
Short name T665
Test name
Test status
Simulation time 94107700 ps
CPU time 144 seconds
Started Jul 22 05:34:49 PM PDT 24
Finished Jul 22 05:37:14 PM PDT 24
Peak memory 276960 kb
Host smart-3ed39bf5-296f-4c91-9e3d-33751779bb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488285247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.3488285247
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.2865200600
Short name T871
Test name
Test status
Simulation time 63751000 ps
CPU time 14.1 seconds
Started Jul 22 05:34:50 PM PDT 24
Finished Jul 22 05:35:04 PM PDT 24
Peak memory 265312 kb
Host smart-c1c84295-1862-4202-960d-87773c3d56ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865200600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
2865200600
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.1942074692
Short name T431
Test name
Test status
Simulation time 26968800 ps
CPU time 15.7 seconds
Started Jul 22 05:34:51 PM PDT 24
Finished Jul 22 05:35:07 PM PDT 24
Peak memory 284180 kb
Host smart-dfa2d3b3-d606-4e0e-940e-1d90a7a9f904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942074692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.1942074692
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.1087922889
Short name T745
Test name
Test status
Simulation time 11033900 ps
CPU time 21.98 seconds
Started Jul 22 05:34:50 PM PDT 24
Finished Jul 22 05:35:12 PM PDT 24
Peak memory 273544 kb
Host smart-c499f578-605b-4f07-95eb-f66ef7e277bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087922889 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.1087922889
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.1201105899
Short name T776
Test name
Test status
Simulation time 5518083900 ps
CPU time 62.31 seconds
Started Jul 22 05:34:50 PM PDT 24
Finished Jul 22 05:35:53 PM PDT 24
Peak memory 263260 kb
Host smart-b36ed1bd-8a2e-4bb4-83b3-0afb0f4a0535
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201105899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.1201105899
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.1499660981
Short name T194
Test name
Test status
Simulation time 99246200 ps
CPU time 112.46 seconds
Started Jul 22 05:34:49 PM PDT 24
Finished Jul 22 05:36:42 PM PDT 24
Peak memory 261308 kb
Host smart-619fbcf5-9af2-414f-abcf-42796c5af750
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499660981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.1499660981
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.2384187635
Short name T5
Test name
Test status
Simulation time 5053899000 ps
CPU time 84.57 seconds
Started Jul 22 05:34:48 PM PDT 24
Finished Jul 22 05:36:13 PM PDT 24
Peak memory 265040 kb
Host smart-e9eb8f61-80b1-4b7a-8776-8573f231d01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384187635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.2384187635
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.2037311178
Short name T598
Test name
Test status
Simulation time 32552400 ps
CPU time 121.67 seconds
Started Jul 22 05:39:38 PM PDT 24
Finished Jul 22 05:41:41 PM PDT 24
Peak memory 276628 kb
Host smart-f417f6a5-1fb0-42b4-a288-c41634c64cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037311178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.2037311178
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.1593731807
Short name T139
Test name
Test status
Simulation time 171254200 ps
CPU time 13.51 seconds
Started Jul 22 05:39:38 PM PDT 24
Finished Jul 22 05:39:52 PM PDT 24
Peak memory 265212 kb
Host smart-b4e48064-508e-4ddd-961f-8c2d1b9cb891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593731807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
1593731807
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.1304578261
Short name T143
Test name
Test status
Simulation time 35099100 ps
CPU time 15.64 seconds
Started Jul 22 05:35:00 PM PDT 24
Finished Jul 22 05:35:16 PM PDT 24
Peak memory 274868 kb
Host smart-a9bd639c-e9f1-4f84-91df-d6341a4fad45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304578261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.1304578261
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.2728561839
Short name T727
Test name
Test status
Simulation time 26998800 ps
CPU time 21.84 seconds
Started Jul 22 05:34:56 PM PDT 24
Finished Jul 22 05:35:18 PM PDT 24
Peak memory 273636 kb
Host smart-8ed720bd-cff0-4e59-a4a3-9662f73f0286
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728561839 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.2728561839
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.2830372751
Short name T320
Test name
Test status
Simulation time 2385320700 ps
CPU time 195.33 seconds
Started Jul 22 05:34:58 PM PDT 24
Finished Jul 22 05:38:14 PM PDT 24
Peak memory 262276 kb
Host smart-c42bcc2b-7902-4281-9822-12f4dddb05fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830372751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.2830372751
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.2971343104
Short name T766
Test name
Test status
Simulation time 36506100 ps
CPU time 111.2 seconds
Started Jul 22 05:34:57 PM PDT 24
Finished Jul 22 05:36:49 PM PDT 24
Peak memory 260020 kb
Host smart-fa3e6171-d6ee-498f-963b-21e12030cf43
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971343104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o
tp_reset.2971343104
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.839706812
Short name T406
Test name
Test status
Simulation time 937692900 ps
CPU time 87.36 seconds
Started Jul 22 05:34:59 PM PDT 24
Finished Jul 22 05:36:27 PM PDT 24
Peak memory 264968 kb
Host smart-c38984fa-daff-4a10-8552-2cf9ed1279a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839706812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.839706812
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.3475951577
Short name T1022
Test name
Test status
Simulation time 34843000 ps
CPU time 52.09 seconds
Started Jul 22 05:34:57 PM PDT 24
Finished Jul 22 05:35:50 PM PDT 24
Peak memory 271336 kb
Host smart-6eb39218-d038-41e2-b54c-8b139c6812ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475951577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3475951577
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.4214897420
Short name T1041
Test name
Test status
Simulation time 68576000 ps
CPU time 14.13 seconds
Started Jul 22 05:34:58 PM PDT 24
Finished Jul 22 05:35:12 PM PDT 24
Peak memory 258380 kb
Host smart-a5c9b204-b798-4cd9-b782-a851c9eb2c5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214897420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
4214897420
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.2463708897
Short name T917
Test name
Test status
Simulation time 61613700 ps
CPU time 13.81 seconds
Started Jul 22 05:34:57 PM PDT 24
Finished Jul 22 05:35:12 PM PDT 24
Peak memory 274884 kb
Host smart-279e8402-7dcf-4d15-826b-a67c3d07d259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463708897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.2463708897
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.1963776840
Short name T97
Test name
Test status
Simulation time 15321000 ps
CPU time 21.8 seconds
Started Jul 22 05:34:59 PM PDT 24
Finished Jul 22 05:35:21 PM PDT 24
Peak memory 265384 kb
Host smart-c7fdeffc-2730-45fb-8d04-228772f7c288
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963776840 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.1963776840
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.2267056140
Short name T957
Test name
Test status
Simulation time 5227556500 ps
CPU time 128.74 seconds
Started Jul 22 05:39:38 PM PDT 24
Finished Jul 22 05:41:48 PM PDT 24
Peak memory 263296 kb
Host smart-c3480972-58bc-44fc-87a1-2e7ae96058a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267056140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.2267056140
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.203552874
Short name T538
Test name
Test status
Simulation time 139667100 ps
CPU time 130.23 seconds
Started Jul 22 05:34:59 PM PDT 24
Finished Jul 22 05:37:10 PM PDT 24
Peak memory 260032 kb
Host smart-9cb7ee1a-dd02-4a06-b8fc-fdb11591e698
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203552874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_ot
p_reset.203552874
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.2970748410
Short name T516
Test name
Test status
Simulation time 3587564800 ps
CPU time 63.61 seconds
Started Jul 22 05:39:38 PM PDT 24
Finished Jul 22 05:40:43 PM PDT 24
Peak memory 262872 kb
Host smart-a6cad967-233a-4234-a6ad-2d0f63c9bdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970748410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.2970748410
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.2487479556
Short name T641
Test name
Test status
Simulation time 290880000 ps
CPU time 169.47 seconds
Started Jul 22 05:34:58 PM PDT 24
Finished Jul 22 05:37:48 PM PDT 24
Peak memory 281552 kb
Host smart-288c1807-b4e1-4920-8660-7eac59672bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487479556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.2487479556
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.1076269382
Short name T1072
Test name
Test status
Simulation time 60831600 ps
CPU time 13.41 seconds
Started Jul 22 05:35:06 PM PDT 24
Finished Jul 22 05:35:20 PM PDT 24
Peak memory 258404 kb
Host smart-06ad771b-bdb5-48dd-b89c-fe7f2662d6a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076269382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
1076269382
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.2462596216
Short name T141
Test name
Test status
Simulation time 15207100 ps
CPU time 16.54 seconds
Started Jul 22 05:35:05 PM PDT 24
Finished Jul 22 05:35:22 PM PDT 24
Peak memory 274920 kb
Host smart-528b96de-2e83-40e6-9e39-759caaad6a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462596216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.2462596216
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.1289304364
Short name T760
Test name
Test status
Simulation time 22066000 ps
CPU time 21.8 seconds
Started Jul 22 05:35:08 PM PDT 24
Finished Jul 22 05:35:30 PM PDT 24
Peak memory 273644 kb
Host smart-f1c60b05-b9b3-42ae-9638-f7ed8b5a95c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289304364 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.1289304364
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.2780229901
Short name T791
Test name
Test status
Simulation time 10922846900 ps
CPU time 216.96 seconds
Started Jul 22 05:39:38 PM PDT 24
Finished Jul 22 05:43:16 PM PDT 24
Peak memory 260912 kb
Host smart-66de9f32-e3d1-4bb6-a4c4-d4e82133508b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780229901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.2780229901
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.1753157428
Short name T847
Test name
Test status
Simulation time 317196200 ps
CPU time 129.57 seconds
Started Jul 22 05:34:57 PM PDT 24
Finished Jul 22 05:37:06 PM PDT 24
Peak memory 264544 kb
Host smart-d7a4f13a-8159-4d32-a2c6-99e31a937da6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753157428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o
tp_reset.1753157428
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.1760772945
Short name T408
Test name
Test status
Simulation time 7177222900 ps
CPU time 77.6 seconds
Started Jul 22 05:35:06 PM PDT 24
Finished Jul 22 05:36:24 PM PDT 24
Peak memory 263696 kb
Host smart-a782c1d2-b642-47c6-96f7-e9a4404a1c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760772945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.1760772945
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.1782057737
Short name T619
Test name
Test status
Simulation time 20205800 ps
CPU time 98.55 seconds
Started Jul 22 05:39:38 PM PDT 24
Finished Jul 22 05:41:18 PM PDT 24
Peak memory 277188 kb
Host smart-0cafd713-6ec0-4cce-9522-e0ae1a79c91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782057737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.1782057737
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.3658000948
Short name T918
Test name
Test status
Simulation time 22528500 ps
CPU time 13.32 seconds
Started Jul 22 05:28:24 PM PDT 24
Finished Jul 22 05:28:38 PM PDT 24
Peak memory 258444 kb
Host smart-613f1b53-8181-4412-8926-dd171452d7a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658000948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.3
658000948
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.4002550523
Short name T729
Test name
Test status
Simulation time 21166900 ps
CPU time 13.54 seconds
Started Jul 22 05:28:20 PM PDT 24
Finished Jul 22 05:28:34 PM PDT 24
Peak memory 274892 kb
Host smart-153bbf45-863c-4625-ab9a-1f6ae16a2bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002550523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.4002550523
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.3358685825
Short name T183
Test name
Test status
Simulation time 32207100 ps
CPU time 20.75 seconds
Started Jul 22 05:28:19 PM PDT 24
Finished Jul 22 05:28:41 PM PDT 24
Peak memory 273536 kb
Host smart-71e1443b-6cac-498b-a854-be013e93b489
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358685825 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.3358685825
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.263340885
Short name T965
Test name
Test status
Simulation time 4685191700 ps
CPU time 2193.98 seconds
Started Jul 22 05:28:05 PM PDT 24
Finished Jul 22 06:04:39 PM PDT 24
Peak memory 265220 kb
Host smart-e5e14bd2-a482-4b79-baeb-5165fa09779b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=263340885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.263340885
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.466349185
Short name T452
Test name
Test status
Simulation time 670831800 ps
CPU time 830.47 seconds
Started Jul 22 05:28:03 PM PDT 24
Finished Jul 22 05:41:54 PM PDT 24
Peak memory 273456 kb
Host smart-57fa3e31-3243-4905-8cc8-b5b930a88002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466349185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.466349185
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.3023434719
Short name T54
Test name
Test status
Simulation time 92047800 ps
CPU time 22.04 seconds
Started Jul 22 05:28:12 PM PDT 24
Finished Jul 22 05:28:34 PM PDT 24
Peak memory 263540 kb
Host smart-ea1cf11b-7ca7-4542-bb54-d606810e072f
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023434719 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.flash_ctrl_fetch_code.3023434719
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3517909595
Short name T912
Test name
Test status
Simulation time 10031379800 ps
CPU time 62.43 seconds
Started Jul 22 05:28:19 PM PDT 24
Finished Jul 22 05:29:22 PM PDT 24
Peak memory 293632 kb
Host smart-0c41d87a-7c4c-416f-a1ff-20fe9d2e1187
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517909595 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.3517909595
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.1229002712
Short name T121
Test name
Test status
Simulation time 98808300 ps
CPU time 13.59 seconds
Started Jul 22 05:28:17 PM PDT 24
Finished Jul 22 05:28:32 PM PDT 24
Peak memory 258732 kb
Host smart-ee5fdc4c-4a4b-4d1d-b2eb-cf626dcf0cb3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229002712 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.1229002712
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.1033615841
Short name T689
Test name
Test status
Simulation time 6945070700 ps
CPU time 216.47 seconds
Started Jul 22 05:28:12 PM PDT 24
Finished Jul 22 05:31:49 PM PDT 24
Peak memory 261028 kb
Host smart-f5f6ca9a-24bc-40cd-a3fe-c42736bf1ee0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033615841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.1033615841
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.2976473067
Short name T541
Test name
Test status
Simulation time 4098080600 ps
CPU time 180.04 seconds
Started Jul 22 05:28:10 PM PDT 24
Finished Jul 22 05:31:10 PM PDT 24
Peak memory 291044 kb
Host smart-ce80c8d8-5fb8-47e2-857d-a6d04fe6c1bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976473067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_intr_rd.2976473067
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.2942593222
Short name T390
Test name
Test status
Simulation time 22743848200 ps
CPU time 174.19 seconds
Started Jul 22 05:28:09 PM PDT 24
Finished Jul 22 05:31:04 PM PDT 24
Peak memory 292820 kb
Host smart-49af2332-718b-439e-9fae-ff4b80815a2a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942593222 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.2942593222
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.1453872377
Short name T497
Test name
Test status
Simulation time 8467954400 ps
CPU time 76.17 seconds
Started Jul 22 05:28:10 PM PDT 24
Finished Jul 22 05:29:26 PM PDT 24
Peak memory 265268 kb
Host smart-3669de56-3d12-43da-825e-02283b8aa0b4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453872377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.1453872377
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.2497795040
Short name T954
Test name
Test status
Simulation time 51748420900 ps
CPU time 208.68 seconds
Started Jul 22 05:28:11 PM PDT 24
Finished Jul 22 05:31:40 PM PDT 24
Peak memory 260416 kb
Host smart-f1107aa6-843a-4f67-ae58-5ec74cd588a4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249
7795040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.2497795040
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.4121530348
Short name T556
Test name
Test status
Simulation time 3341675400 ps
CPU time 69.17 seconds
Started Jul 22 05:28:11 PM PDT 24
Finished Jul 22 05:29:21 PM PDT 24
Peak memory 260756 kb
Host smart-acab7c87-9dcd-4179-bf57-72f61e5a83a9
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121530348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.4121530348
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.2567070731
Short name T492
Test name
Test status
Simulation time 15598800 ps
CPU time 13.32 seconds
Started Jul 22 05:28:19 PM PDT 24
Finished Jul 22 05:28:33 PM PDT 24
Peak memory 260688 kb
Host smart-7c1c400e-219a-4fc7-8c66-d7a5268e2354
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567070731 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.2567070731
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.961205415
Short name T344
Test name
Test status
Simulation time 4844598400 ps
CPU time 209.39 seconds
Started Jul 22 05:28:12 PM PDT 24
Finished Jul 22 05:31:42 PM PDT 24
Peak memory 263888 kb
Host smart-21104b9b-071a-4ce0-8de5-7d5016057ee2
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961205415 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.961205415
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.2285076134
Short name T394
Test name
Test status
Simulation time 73334800 ps
CPU time 134.7 seconds
Started Jul 22 05:28:01 PM PDT 24
Finished Jul 22 05:30:16 PM PDT 24
Peak memory 260012 kb
Host smart-dd36364e-7753-4537-a369-232cad0d92df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285076134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.2285076134
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.1489071262
Short name T433
Test name
Test status
Simulation time 211458400 ps
CPU time 323.69 seconds
Started Jul 22 05:27:56 PM PDT 24
Finished Jul 22 05:33:20 PM PDT 24
Peak memory 263232 kb
Host smart-77968a08-a274-412f-97dc-621884657356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1489071262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.1489071262
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.2230036193
Short name T962
Test name
Test status
Simulation time 21758300 ps
CPU time 13.7 seconds
Started Jul 22 05:28:16 PM PDT 24
Finished Jul 22 05:28:31 PM PDT 24
Peak memory 265240 kb
Host smart-8f25315e-4938-4223-86ab-63474028b110
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230036193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.flash_ctrl_prog_reset.2230036193
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.2000280820
Short name T432
Test name
Test status
Simulation time 60134900 ps
CPU time 189.51 seconds
Started Jul 22 05:27:56 PM PDT 24
Finished Jul 22 05:31:06 PM PDT 24
Peak memory 281584 kb
Host smart-66f698a4-a7fc-4a9b-919a-07b175ddcb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000280820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.2000280820
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.81487493
Short name T966
Test name
Test status
Simulation time 72748400 ps
CPU time 30.82 seconds
Started Jul 22 05:28:17 PM PDT 24
Finished Jul 22 05:28:49 PM PDT 24
Peak memory 275696 kb
Host smart-fde1ff91-cc66-44d7-b8f8-75df9baeb1a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81487493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash
_ctrl_re_evict.81487493
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.3413948321
Short name T806
Test name
Test status
Simulation time 576057900 ps
CPU time 108.39 seconds
Started Jul 22 05:28:01 PM PDT 24
Finished Jul 22 05:29:50 PM PDT 24
Peak memory 291320 kb
Host smart-f4a2db5d-07da-48e6-9736-4b21ceca9116
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413948321 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_ro.3413948321
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.3966713534
Short name T899
Test name
Test status
Simulation time 2685392500 ps
CPU time 160.94 seconds
Started Jul 22 05:28:01 PM PDT 24
Finished Jul 22 05:30:42 PM PDT 24
Peak memory 282892 kb
Host smart-44bd59a5-fc4b-4911-aafc-4f8778b03c48
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3966713534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.3966713534
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.104856384
Short name T764
Test name
Test status
Simulation time 475122700 ps
CPU time 108.31 seconds
Started Jul 22 05:28:12 PM PDT 24
Finished Jul 22 05:30:01 PM PDT 24
Peak memory 281760 kb
Host smart-6081cd9d-b3e5-48f4-abda-38d6d22c8e49
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104856384 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.104856384
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.3080502992
Short name T714
Test name
Test status
Simulation time 3206594600 ps
CPU time 611.63 seconds
Started Jul 22 05:28:12 PM PDT 24
Finished Jul 22 05:38:24 PM PDT 24
Peak memory 318984 kb
Host smart-b6e1fb2f-ba67-4a39-a19f-7b8ad957ce32
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080502992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.flash_ctrl_rw.3080502992
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.140608519
Short name T836
Test name
Test status
Simulation time 3636368000 ps
CPU time 668.7 seconds
Started Jul 22 05:28:12 PM PDT 24
Finished Jul 22 05:39:21 PM PDT 24
Peak memory 318940 kb
Host smart-e8a24d61-84be-4efa-9db7-32383873cfc4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140608519 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.flash_ctrl_rw_derr.140608519
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.1229110114
Short name T687
Test name
Test status
Simulation time 38770200 ps
CPU time 30.88 seconds
Started Jul 22 05:28:17 PM PDT 24
Finished Jul 22 05:28:49 PM PDT 24
Peak memory 273632 kb
Host smart-bf2ab4b1-1d1e-42ca-88aa-ac237893e6df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229110114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_rw_evict.1229110114
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.2643879881
Short name T508
Test name
Test status
Simulation time 30770500 ps
CPU time 32.08 seconds
Started Jul 22 05:28:17 PM PDT 24
Finished Jul 22 05:28:50 PM PDT 24
Peak memory 268500 kb
Host smart-dfe384cd-ff6f-4188-8ff0-c4f8dd531dd6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643879881 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.2643879881
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.429598304
Short name T403
Test name
Test status
Simulation time 4984311100 ps
CPU time 75.33 seconds
Started Jul 22 05:28:16 PM PDT 24
Finished Jul 22 05:29:32 PM PDT 24
Peak memory 263224 kb
Host smart-2f134c29-22e7-4c6f-91fd-18c490157732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429598304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.429598304
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.2922215777
Short name T1023
Test name
Test status
Simulation time 38338000 ps
CPU time 100.27 seconds
Started Jul 22 05:27:57 PM PDT 24
Finished Jul 22 05:29:38 PM PDT 24
Peak memory 277336 kb
Host smart-12fd9c46-614b-4159-ae06-97a133219126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922215777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2922215777
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.3894156294
Short name T520
Test name
Test status
Simulation time 4118786600 ps
CPU time 173.8 seconds
Started Jul 22 05:28:02 PM PDT 24
Finished Jul 22 05:30:56 PM PDT 24
Peak memory 265252 kb
Host smart-bfd086ba-0233-4e78-a40f-6b95cf929fde
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894156294 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.flash_ctrl_wo.3894156294
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.3292088239
Short name T568
Test name
Test status
Simulation time 62442100 ps
CPU time 15.38 seconds
Started Jul 22 05:35:07 PM PDT 24
Finished Jul 22 05:35:23 PM PDT 24
Peak memory 274772 kb
Host smart-8b49c151-55ea-4ea7-8813-c37c394b9b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292088239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.3292088239
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.414641017
Short name T841
Test name
Test status
Simulation time 37226800 ps
CPU time 133.38 seconds
Started Jul 22 05:35:07 PM PDT 24
Finished Jul 22 05:37:20 PM PDT 24
Peak memory 260132 kb
Host smart-66378ddd-acfb-4d77-8d88-cb7dc2488b80
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414641017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_ot
p_reset.414641017
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.572464460
Short name T699
Test name
Test status
Simulation time 62520100 ps
CPU time 15.41 seconds
Started Jul 22 05:39:38 PM PDT 24
Finished Jul 22 05:39:54 PM PDT 24
Peak memory 274760 kb
Host smart-b524dbeb-25ef-4fd1-94c9-114a7f30d2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572464460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.572464460
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.536348457
Short name T1056
Test name
Test status
Simulation time 133500100 ps
CPU time 134.8 seconds
Started Jul 22 05:35:08 PM PDT 24
Finished Jul 22 05:37:23 PM PDT 24
Peak memory 260200 kb
Host smart-f8632fb8-5c17-4b54-814c-2bfee10ca369
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536348457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_ot
p_reset.536348457
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.974860975
Short name T758
Test name
Test status
Simulation time 37196200 ps
CPU time 15.76 seconds
Started Jul 22 05:35:07 PM PDT 24
Finished Jul 22 05:35:23 PM PDT 24
Peak memory 284428 kb
Host smart-7bb0c208-9d21-425f-ae1b-c2424c8963b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974860975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.974860975
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.2124927743
Short name T74
Test name
Test status
Simulation time 551390200 ps
CPU time 132.88 seconds
Started Jul 22 05:35:07 PM PDT 24
Finished Jul 22 05:37:20 PM PDT 24
Peak memory 265124 kb
Host smart-6895ee8f-f344-4cae-ac41-e4d3a8f99c0f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124927743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.2124927743
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.1508660355
Short name T630
Test name
Test status
Simulation time 16600100 ps
CPU time 16.06 seconds
Started Jul 22 05:35:06 PM PDT 24
Finished Jul 22 05:35:22 PM PDT 24
Peak memory 284368 kb
Host smart-7eb11a62-58c5-4b53-b83f-92265bc47d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508660355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.1508660355
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.1921786159
Short name T490
Test name
Test status
Simulation time 41094800 ps
CPU time 132.07 seconds
Started Jul 22 05:35:07 PM PDT 24
Finished Jul 22 05:37:20 PM PDT 24
Peak memory 260516 kb
Host smart-9d382eb3-123b-4c9d-bb2e-f1ac7cf08778
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921786159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o
tp_reset.1921786159
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.2509835839
Short name T163
Test name
Test status
Simulation time 43681900 ps
CPU time 15.79 seconds
Started Jul 22 05:35:08 PM PDT 24
Finished Jul 22 05:35:24 PM PDT 24
Peak memory 274824 kb
Host smart-de6ee9a5-8814-4615-8f8b-a8def27afade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509835839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.2509835839
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.2088114636
Short name T1073
Test name
Test status
Simulation time 40418100 ps
CPU time 134.18 seconds
Started Jul 22 05:35:05 PM PDT 24
Finished Jul 22 05:37:19 PM PDT 24
Peak memory 261128 kb
Host smart-c3047ab4-26e4-48cf-afd4-a793fbaec2f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088114636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.2088114636
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.1191119292
Short name T471
Test name
Test status
Simulation time 31196600 ps
CPU time 16.64 seconds
Started Jul 22 05:36:56 PM PDT 24
Finished Jul 22 05:37:14 PM PDT 24
Peak memory 274896 kb
Host smart-38f25b1b-e0a1-4e3b-91a6-1fd2eacf0e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191119292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.1191119292
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.353107209
Short name T854
Test name
Test status
Simulation time 50121200 ps
CPU time 110.01 seconds
Started Jul 22 05:35:08 PM PDT 24
Finished Jul 22 05:36:58 PM PDT 24
Peak memory 264972 kb
Host smart-55211c82-3b53-4bed-8394-88294bb9d135
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353107209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_ot
p_reset.353107209
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.4185660877
Short name T717
Test name
Test status
Simulation time 15173300 ps
CPU time 15.71 seconds
Started Jul 22 05:35:07 PM PDT 24
Finished Jul 22 05:35:23 PM PDT 24
Peak memory 284244 kb
Host smart-a0275f69-7457-4aef-8371-f57871a9af91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185660877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.4185660877
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.2920637014
Short name T964
Test name
Test status
Simulation time 37319100 ps
CPU time 111.85 seconds
Started Jul 22 05:35:08 PM PDT 24
Finished Jul 22 05:37:00 PM PDT 24
Peak memory 261124 kb
Host smart-9c1b7d1c-8091-4337-9713-347362ed8c1f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920637014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.2920637014
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.3347581225
Short name T430
Test name
Test status
Simulation time 14799600 ps
CPU time 15.51 seconds
Started Jul 22 05:35:18 PM PDT 24
Finished Jul 22 05:35:35 PM PDT 24
Peak memory 284304 kb
Host smart-786d9487-94ae-49bf-bc56-0e482daace97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347581225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.3347581225
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.3960351248
Short name T584
Test name
Test status
Simulation time 39304400 ps
CPU time 131.32 seconds
Started Jul 22 05:35:14 PM PDT 24
Finished Jul 22 05:37:25 PM PDT 24
Peak memory 261444 kb
Host smart-09055908-1c9c-4177-acc6-4ea95e39a754
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960351248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.3960351248
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.2491229400
Short name T1092
Test name
Test status
Simulation time 16131900 ps
CPU time 16.53 seconds
Started Jul 22 05:35:17 PM PDT 24
Finished Jul 22 05:35:35 PM PDT 24
Peak memory 274888 kb
Host smart-4d5ee6d0-260d-4256-8b9e-1e9c4616f293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491229400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.2491229400
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.3342346004
Short name T580
Test name
Test status
Simulation time 144468100 ps
CPU time 130.72 seconds
Started Jul 22 05:35:16 PM PDT 24
Finished Jul 22 05:37:28 PM PDT 24
Peak memory 260272 kb
Host smart-33f38d2c-90e8-4650-99de-7c58a48dd833
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342346004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.3342346004
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.3314155044
Short name T796
Test name
Test status
Simulation time 201695300 ps
CPU time 15.57 seconds
Started Jul 22 05:38:08 PM PDT 24
Finished Jul 22 05:38:27 PM PDT 24
Peak memory 284168 kb
Host smart-29059834-b7e3-4595-900a-816795138d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314155044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.3314155044
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.3235700045
Short name T569
Test name
Test status
Simulation time 151441100 ps
CPU time 111.66 seconds
Started Jul 22 05:35:16 PM PDT 24
Finished Jul 22 05:37:08 PM PDT 24
Peak memory 260140 kb
Host smart-16adbfa1-8d41-4d77-a9bf-1101aa7d6fcb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235700045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.3235700045
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.4239826403
Short name T142
Test name
Test status
Simulation time 203227000 ps
CPU time 14.24 seconds
Started Jul 22 05:28:43 PM PDT 24
Finished Jul 22 05:28:58 PM PDT 24
Peak memory 265292 kb
Host smart-c398e0e5-1a1b-4a2a-86b2-bf063906c6e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239826403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.4
239826403
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.2996227707
Short name T456
Test name
Test status
Simulation time 17244300 ps
CPU time 15.57 seconds
Started Jul 22 05:28:37 PM PDT 24
Finished Jul 22 05:28:53 PM PDT 24
Peak memory 274904 kb
Host smart-3242983c-b270-4c92-8025-b297c36e0f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996227707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.2996227707
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.2581844477
Short name T237
Test name
Test status
Simulation time 5662714900 ps
CPU time 2207.91 seconds
Started Jul 22 05:28:27 PM PDT 24
Finished Jul 22 06:05:16 PM PDT 24
Peak memory 262956 kb
Host smart-b8ed4e18-c21d-44b6-8fd8-3d34a13e7c11
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2581844477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.2581844477
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.719853919
Short name T1062
Test name
Test status
Simulation time 2299382800 ps
CPU time 795.57 seconds
Started Jul 22 05:28:34 PM PDT 24
Finished Jul 22 05:41:50 PM PDT 24
Peak memory 270512 kb
Host smart-5a491cab-e219-4c66-9214-d737743a2f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719853919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.719853919
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.2162725181
Short name T50
Test name
Test status
Simulation time 1174638800 ps
CPU time 32.06 seconds
Started Jul 22 05:28:26 PM PDT 24
Finished Jul 22 05:28:58 PM PDT 24
Peak memory 262592 kb
Host smart-a8cb4c25-7042-46f7-bd26-bc92d98b9f15
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162725181 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_fetch_code.2162725181
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.1521455940
Short name T992
Test name
Test status
Simulation time 10019011100 ps
CPU time 88.05 seconds
Started Jul 22 05:28:44 PM PDT 24
Finished Jul 22 05:30:12 PM PDT 24
Peak memory 314600 kb
Host smart-3c8ee580-71d2-4398-8afa-37e073a305cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521455940 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.1521455940
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.2185986370
Short name T1009
Test name
Test status
Simulation time 47290500 ps
CPU time 13.73 seconds
Started Jul 22 05:28:45 PM PDT 24
Finished Jul 22 05:28:59 PM PDT 24
Peak memory 260248 kb
Host smart-f4b3c403-4a01-481e-8f86-38d401857784
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185986370 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.2185986370
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.434971659
Short name T205
Test name
Test status
Simulation time 40124599100 ps
CPU time 902.65 seconds
Started Jul 22 05:28:27 PM PDT 24
Finished Jul 22 05:43:30 PM PDT 24
Peak memory 260868 kb
Host smart-7aaeb152-07d9-4536-8d6c-927bc28ca9c9
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434971659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.flash_ctrl_hw_rma_reset.434971659
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.4118895260
Short name T595
Test name
Test status
Simulation time 4759094300 ps
CPU time 195.64 seconds
Started Jul 22 05:28:35 PM PDT 24
Finished Jul 22 05:31:51 PM PDT 24
Peak memory 261096 kb
Host smart-37476dad-1de6-4d5a-b7d0-cb65ad1ec4fa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118895260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.4118895260
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.856246361
Short name T89
Test name
Test status
Simulation time 6242039400 ps
CPU time 253.9 seconds
Started Jul 22 05:28:37 PM PDT 24
Finished Jul 22 05:32:52 PM PDT 24
Peak memory 292728 kb
Host smart-9dd25ced-23e0-45b3-9d1d-24e597bf84fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856246361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash
_ctrl_intr_rd.856246361
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.1397422908
Short name T696
Test name
Test status
Simulation time 5950150900 ps
CPU time 135.65 seconds
Started Jul 22 05:28:39 PM PDT 24
Finished Jul 22 05:30:55 PM PDT 24
Peak memory 293048 kb
Host smart-89faea42-5b83-4a72-a211-be50071bb333
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397422908 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.1397422908
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.2219123205
Short name T830
Test name
Test status
Simulation time 7626799200 ps
CPU time 89.83 seconds
Started Jul 22 05:28:36 PM PDT 24
Finished Jul 22 05:30:07 PM PDT 24
Peak memory 260792 kb
Host smart-07eec67e-52f6-47ab-97ef-445021b85ed4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219123205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.2219123205
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.3364430469
Short name T778
Test name
Test status
Simulation time 44349415600 ps
CPU time 191.72 seconds
Started Jul 22 05:28:37 PM PDT 24
Finished Jul 22 05:31:49 PM PDT 24
Peak memory 265236 kb
Host smart-82f5fc7f-e8e8-404d-be44-ee659b91eedd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336
4430469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.3364430469
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.2019768468
Short name T800
Test name
Test status
Simulation time 980363200 ps
CPU time 89.76 seconds
Started Jul 22 05:28:26 PM PDT 24
Finished Jul 22 05:29:56 PM PDT 24
Peak memory 263408 kb
Host smart-d2a0156c-8664-4843-9661-8fb363a552aa
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019768468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.2019768468
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.140230168
Short name T297
Test name
Test status
Simulation time 48830800 ps
CPU time 13.76 seconds
Started Jul 22 05:28:46 PM PDT 24
Finished Jul 22 05:29:01 PM PDT 24
Peak memory 264896 kb
Host smart-669848c1-c829-4b0a-82a9-60001fa90f55
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140230168 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.140230168
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.1767027359
Short name T137
Test name
Test status
Simulation time 49931861200 ps
CPU time 293.6 seconds
Started Jul 22 05:28:25 PM PDT 24
Finished Jul 22 05:33:20 PM PDT 24
Peak memory 275072 kb
Host smart-dc3e982e-65ed-4b87-9043-3a89292b72e0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767027359 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.1767027359
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.3050246453
Short name T867
Test name
Test status
Simulation time 40643500 ps
CPU time 130.7 seconds
Started Jul 22 05:28:27 PM PDT 24
Finished Jul 22 05:30:39 PM PDT 24
Peak memory 264124 kb
Host smart-759e5ad9-1b80-44c0-a3e3-f4700f229014
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050246453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.3050246453
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.2566446145
Short name T477
Test name
Test status
Simulation time 166625300 ps
CPU time 363.42 seconds
Started Jul 22 05:28:34 PM PDT 24
Finished Jul 22 05:34:38 PM PDT 24
Peak memory 263072 kb
Host smart-0ed1462e-0444-4e15-a854-349cfb2c5142
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2566446145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.2566446145
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.2982547459
Short name T393
Test name
Test status
Simulation time 25639600 ps
CPU time 14.09 seconds
Started Jul 22 05:28:37 PM PDT 24
Finished Jul 22 05:28:52 PM PDT 24
Peak memory 259396 kb
Host smart-427314cf-ea28-455b-92b8-598cdf57ea37
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982547459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.flash_ctrl_prog_reset.2982547459
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.375500847
Short name T169
Test name
Test status
Simulation time 302598400 ps
CPU time 723.29 seconds
Started Jul 22 05:28:23 PM PDT 24
Finished Jul 22 05:40:27 PM PDT 24
Peak memory 285180 kb
Host smart-dc11ba42-8761-4d7f-8037-816e0663d19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375500847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.375500847
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.2503971720
Short name T221
Test name
Test status
Simulation time 92841100 ps
CPU time 33.82 seconds
Started Jul 22 05:28:36 PM PDT 24
Finished Jul 22 05:29:10 PM PDT 24
Peak memory 277740 kb
Host smart-0ea1619c-722c-4d0c-9874-f618a35d99ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503971720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.2503971720
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.714552300
Short name T828
Test name
Test status
Simulation time 2086152700 ps
CPU time 140.62 seconds
Started Jul 22 05:28:27 PM PDT 24
Finished Jul 22 05:30:48 PM PDT 24
Peak memory 281744 kb
Host smart-ebaa8f37-96f1-4c19-9048-6657701b8109
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714552300 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.flash_ctrl_ro.714552300
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.3694138958
Short name T1027
Test name
Test status
Simulation time 1646928100 ps
CPU time 118.31 seconds
Started Jul 22 05:28:25 PM PDT 24
Finished Jul 22 05:30:24 PM PDT 24
Peak memory 291740 kb
Host smart-0e69c29e-7ea3-406e-b795-ba57ce79ff83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694138958 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.3694138958
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.2167164140
Short name T353
Test name
Test status
Simulation time 4400813800 ps
CPU time 634 seconds
Started Jul 22 05:28:34 PM PDT 24
Finished Jul 22 05:39:09 PM PDT 24
Peak memory 314324 kb
Host smart-b67ae124-42c5-4cff-8e51-cc7cde0c5dd1
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167164140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.flash_ctrl_rw.2167164140
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.876622138
Short name T325
Test name
Test status
Simulation time 29491400 ps
CPU time 30.86 seconds
Started Jul 22 05:28:40 PM PDT 24
Finished Jul 22 05:29:11 PM PDT 24
Peak memory 275580 kb
Host smart-d1b176f0-6d6b-4e84-85d2-b82c92ec4016
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876622138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_rw_evict.876622138
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.351714112
Short name T460
Test name
Test status
Simulation time 30254900 ps
CPU time 28.46 seconds
Started Jul 22 05:28:37 PM PDT 24
Finished Jul 22 05:29:06 PM PDT 24
Peak memory 275684 kb
Host smart-25fb71b3-63cb-4f87-94ab-5d79a599b099
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351714112 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.351714112
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.1447200689
Short name T789
Test name
Test status
Simulation time 14402221400 ps
CPU time 669.17 seconds
Started Jul 22 05:28:36 PM PDT 24
Finished Jul 22 05:39:46 PM PDT 24
Peak memory 320768 kb
Host smart-65b4f964-f27e-4329-86ec-9f1fd1c7b658
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447200689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s
err.1447200689
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.3944482169
Short name T602
Test name
Test status
Simulation time 2582477600 ps
CPU time 85.94 seconds
Started Jul 22 05:28:40 PM PDT 24
Finished Jul 22 05:30:06 PM PDT 24
Peak memory 263656 kb
Host smart-f5f6a39d-361a-490c-ba0d-8249b1749380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944482169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.3944482169
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.1729702788
Short name T623
Test name
Test status
Simulation time 71956500 ps
CPU time 99.51 seconds
Started Jul 22 05:28:18 PM PDT 24
Finished Jul 22 05:29:58 PM PDT 24
Peak memory 277228 kb
Host smart-10ee71fc-3023-4353-83fe-68a6edac6f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729702788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.1729702788
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.284940139
Short name T967
Test name
Test status
Simulation time 10064549800 ps
CPU time 210.78 seconds
Started Jul 22 05:28:25 PM PDT 24
Finished Jul 22 05:31:57 PM PDT 24
Peak memory 265268 kb
Host smart-b9625c50-a693-4e64-9fc1-0ec74c0c97ea
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284940139 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.flash_ctrl_wo.284940139
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.838362441
Short name T636
Test name
Test status
Simulation time 19845500 ps
CPU time 16.29 seconds
Started Jul 22 05:38:08 PM PDT 24
Finished Jul 22 05:38:28 PM PDT 24
Peak memory 274768 kb
Host smart-15f5b9a7-8eea-46ae-91f1-4045fcf4e759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838362441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.838362441
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.3912197331
Short name T395
Test name
Test status
Simulation time 138270300 ps
CPU time 110.68 seconds
Started Jul 22 05:35:15 PM PDT 24
Finished Jul 22 05:37:06 PM PDT 24
Peak memory 264096 kb
Host smart-eaa07525-56a6-4be9-8086-bd29e50a7cf7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912197331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.3912197331
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.3079188885
Short name T658
Test name
Test status
Simulation time 48514000 ps
CPU time 15.75 seconds
Started Jul 22 05:35:17 PM PDT 24
Finished Jul 22 05:35:34 PM PDT 24
Peak memory 274912 kb
Host smart-edf9c239-1707-4cf8-9221-837c739ace47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079188885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.3079188885
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.1098710624
Short name T455
Test name
Test status
Simulation time 38210300 ps
CPU time 111.66 seconds
Started Jul 22 05:35:17 PM PDT 24
Finished Jul 22 05:37:10 PM PDT 24
Peak memory 261024 kb
Host smart-130b5322-c8ce-48aa-aa2f-4dbe8503271e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098710624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.1098710624
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.862948734
Short name T1101
Test name
Test status
Simulation time 38258000 ps
CPU time 13.43 seconds
Started Jul 22 05:35:17 PM PDT 24
Finished Jul 22 05:35:32 PM PDT 24
Peak memory 275012 kb
Host smart-308d6950-6959-4188-ada6-1e716c51b3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862948734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.862948734
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.491919993
Short name T808
Test name
Test status
Simulation time 43760900 ps
CPU time 131.28 seconds
Started Jul 22 05:35:17 PM PDT 24
Finished Jul 22 05:37:30 PM PDT 24
Peak memory 260212 kb
Host smart-b0afc2d3-c4a9-41ec-9ddc-7b0c51517c91
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491919993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_ot
p_reset.491919993
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.1957827401
Short name T788
Test name
Test status
Simulation time 13733000 ps
CPU time 13.49 seconds
Started Jul 22 05:35:17 PM PDT 24
Finished Jul 22 05:35:31 PM PDT 24
Peak memory 284368 kb
Host smart-3b8bf896-9979-4ccb-b9c7-706393dfd656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957827401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.1957827401
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.967025113
Short name T707
Test name
Test status
Simulation time 72675800 ps
CPU time 132.5 seconds
Started Jul 22 05:35:15 PM PDT 24
Finished Jul 22 05:37:28 PM PDT 24
Peak memory 260064 kb
Host smart-d7501501-66cf-42b9-9a9b-f6bede842f65
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967025113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_ot
p_reset.967025113
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.1902670496
Short name T491
Test name
Test status
Simulation time 55075300 ps
CPU time 13.3 seconds
Started Jul 22 05:35:17 PM PDT 24
Finished Jul 22 05:35:31 PM PDT 24
Peak memory 274960 kb
Host smart-4eef8ac2-1863-405b-a99b-c94777e549f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902670496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.1902670496
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.3340883779
Short name T17
Test name
Test status
Simulation time 135189300 ps
CPU time 112.9 seconds
Started Jul 22 05:35:16 PM PDT 24
Finished Jul 22 05:37:10 PM PDT 24
Peak memory 261064 kb
Host smart-5d680c8b-ffb0-4c63-be1e-c92d2881015b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340883779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.3340883779
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.2553624366
Short name T631
Test name
Test status
Simulation time 14911500 ps
CPU time 15.6 seconds
Started Jul 22 05:35:18 PM PDT 24
Finished Jul 22 05:35:35 PM PDT 24
Peak memory 284312 kb
Host smart-0f60b24e-7e96-43b3-bd18-272594991564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553624366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2553624366
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.1173094485
Short name T496
Test name
Test status
Simulation time 75145900 ps
CPU time 110.88 seconds
Started Jul 22 05:35:18 PM PDT 24
Finished Jul 22 05:37:10 PM PDT 24
Peak memory 260344 kb
Host smart-50fe1abf-7fe2-4f79-bc6b-8661aa3c57fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173094485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.1173094485
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.1154977440
Short name T112
Test name
Test status
Simulation time 50694200 ps
CPU time 16.01 seconds
Started Jul 22 05:35:17 PM PDT 24
Finished Jul 22 05:35:34 PM PDT 24
Peak memory 274936 kb
Host smart-b09e41da-0f67-452a-a90e-325f1c5caf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154977440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.1154977440
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.3576128654
Short name T545
Test name
Test status
Simulation time 74712000 ps
CPU time 133.23 seconds
Started Jul 22 05:35:17 PM PDT 24
Finished Jul 22 05:37:31 PM PDT 24
Peak memory 261128 kb
Host smart-4449b481-bc89-4d27-99f3-6b59a7b1350a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576128654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o
tp_reset.3576128654
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.2479077488
Short name T813
Test name
Test status
Simulation time 13074800 ps
CPU time 15.81 seconds
Started Jul 22 05:35:16 PM PDT 24
Finished Jul 22 05:35:33 PM PDT 24
Peak memory 274932 kb
Host smart-331580be-d0d6-47b1-aa00-d7fb79cfd936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479077488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.2479077488
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.3563984819
Short name T314
Test name
Test status
Simulation time 40965900 ps
CPU time 110.21 seconds
Started Jul 22 05:35:15 PM PDT 24
Finished Jul 22 05:37:05 PM PDT 24
Peak memory 260448 kb
Host smart-2ce58072-451f-40d9-a26d-9ce76639e215
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563984819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.3563984819
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.4180281290
Short name T653
Test name
Test status
Simulation time 16476700 ps
CPU time 13.98 seconds
Started Jul 22 05:35:15 PM PDT 24
Finished Jul 22 05:35:30 PM PDT 24
Peak memory 274964 kb
Host smart-702050f8-b937-4bf6-a6d2-5b384d41cfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180281290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.4180281290
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.3392545348
Short name T594
Test name
Test status
Simulation time 37671400 ps
CPU time 131.48 seconds
Started Jul 22 05:35:15 PM PDT 24
Finished Jul 22 05:37:28 PM PDT 24
Peak memory 264804 kb
Host smart-14af1a2c-0ee0-4357-8f8c-9ee1bde5f795
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392545348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.3392545348
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.2666479463
Short name T916
Test name
Test status
Simulation time 13453400 ps
CPU time 13.36 seconds
Started Jul 22 05:35:31 PM PDT 24
Finished Jul 22 05:35:44 PM PDT 24
Peak memory 274808 kb
Host smart-c34ef930-a51a-4351-9674-eaa75fb6395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666479463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.2666479463
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.2053278013
Short name T175
Test name
Test status
Simulation time 38655900 ps
CPU time 133.3 seconds
Started Jul 22 05:35:15 PM PDT 24
Finished Jul 22 05:37:29 PM PDT 24
Peak memory 260184 kb
Host smart-603d3e17-8595-4da4-8766-a2a1f49ea32c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053278013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.2053278013
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.963204804
Short name T500
Test name
Test status
Simulation time 113170700 ps
CPU time 14.03 seconds
Started Jul 22 05:28:59 PM PDT 24
Finished Jul 22 05:29:13 PM PDT 24
Peak memory 258360 kb
Host smart-f078f7c2-9d06-4efa-b8cd-2dc39c853080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963204804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.963204804
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.47710886
Short name T435
Test name
Test status
Simulation time 26346900 ps
CPU time 13.31 seconds
Started Jul 22 05:28:55 PM PDT 24
Finished Jul 22 05:29:08 PM PDT 24
Peak memory 284444 kb
Host smart-8506c13d-7310-4161-8f8a-df4be153a64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47710886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.47710886
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.2688318553
Short name T775
Test name
Test status
Simulation time 28185100 ps
CPU time 22.04 seconds
Started Jul 22 05:28:54 PM PDT 24
Finished Jul 22 05:29:16 PM PDT 24
Peak memory 273620 kb
Host smart-4b525575-d452-417b-be8b-59db5811dd8d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688318553 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.2688318553
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.932174838
Short name T552
Test name
Test status
Simulation time 5042083500 ps
CPU time 2472.49 seconds
Started Jul 22 05:28:53 PM PDT 24
Finished Jul 22 06:10:06 PM PDT 24
Peak memory 262828 kb
Host smart-e1713d37-b4c8-4562-9a82-a3fbe491c075
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=932174838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.932174838
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.1834617327
Short name T802
Test name
Test status
Simulation time 2199661700 ps
CPU time 847.64 seconds
Started Jul 22 05:28:56 PM PDT 24
Finished Jul 22 05:43:04 PM PDT 24
Peak memory 273164 kb
Host smart-5b90ba2d-199a-46d4-9d50-89a9879a57f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834617327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.1834617327
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.672906909
Short name T573
Test name
Test status
Simulation time 546147200 ps
CPU time 30.16 seconds
Started Jul 22 05:28:53 PM PDT 24
Finished Jul 22 05:29:24 PM PDT 24
Peak memory 262528 kb
Host smart-75fb9db2-cb82-4663-b2d6-5571a91feaf3
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672906909 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.flash_ctrl_fetch_code.672906909
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.1996816038
Short name T928
Test name
Test status
Simulation time 10033459800 ps
CPU time 53.25 seconds
Started Jul 22 05:28:53 PM PDT 24
Finished Jul 22 05:29:47 PM PDT 24
Peak memory 271972 kb
Host smart-408068af-0658-4512-b8ff-6d1432840c76
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996816038 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.1996816038
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.3048570383
Short name T738
Test name
Test status
Simulation time 15536900 ps
CPU time 13.38 seconds
Started Jul 22 05:28:53 PM PDT 24
Finished Jul 22 05:29:07 PM PDT 24
Peak memory 264940 kb
Host smart-3060eb0b-29d5-4600-9e75-86ef3bd56375
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048570383 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.3048570383
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.2631506189
Short name T1032
Test name
Test status
Simulation time 80139521400 ps
CPU time 844.57 seconds
Started Jul 22 05:28:47 PM PDT 24
Finished Jul 22 05:42:52 PM PDT 24
Peak memory 262432 kb
Host smart-28c9d51c-5376-4bcd-a3be-75ed45e5b018
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631506189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.2631506189
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.3453350473
Short name T319
Test name
Test status
Simulation time 14489290900 ps
CPU time 136.15 seconds
Started Jul 22 05:28:48 PM PDT 24
Finished Jul 22 05:31:04 PM PDT 24
Peak memory 261068 kb
Host smart-549c10d8-1399-40f4-8941-7c093962c6d3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453350473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.3453350473
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.4229916520
Short name T667
Test name
Test status
Simulation time 3620184200 ps
CPU time 228.98 seconds
Started Jul 22 05:28:54 PM PDT 24
Finished Jul 22 05:32:44 PM PDT 24
Peak memory 291468 kb
Host smart-2ba314cb-1726-47e8-b137-540646177c35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229916520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_intr_rd.4229916520
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.4057828088
Short name T7
Test name
Test status
Simulation time 93717876800 ps
CPU time 183.03 seconds
Started Jul 22 05:28:55 PM PDT 24
Finished Jul 22 05:31:59 PM PDT 24
Peak memory 292724 kb
Host smart-e3c24f4b-c7ef-49f7-83e1-8b98db9250e1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057828088 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.4057828088
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.3028343241
Short name T846
Test name
Test status
Simulation time 9584593300 ps
CPU time 73.66 seconds
Started Jul 22 05:28:52 PM PDT 24
Finished Jul 22 05:30:06 PM PDT 24
Peak memory 260676 kb
Host smart-c55a916c-73ec-41f2-9a59-2cd4ef21b4ec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028343241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.3028343241
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.3160802850
Short name T951
Test name
Test status
Simulation time 25280445900 ps
CPU time 178.75 seconds
Started Jul 22 05:28:55 PM PDT 24
Finished Jul 22 05:31:55 PM PDT 24
Peak memory 265420 kb
Host smart-9d1f9034-0ec7-40f8-80d1-d4c29a4b2d32
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316
0802850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.3160802850
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.3961957602
Short name T1089
Test name
Test status
Simulation time 1699119700 ps
CPU time 74.66 seconds
Started Jul 22 05:28:55 PM PDT 24
Finished Jul 22 05:30:10 PM PDT 24
Peak memory 263396 kb
Host smart-30c55ce2-777d-4029-baef-1fca33806483
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961957602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.3961957602
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.1925463892
Short name T535
Test name
Test status
Simulation time 48697300 ps
CPU time 13.46 seconds
Started Jul 22 05:28:54 PM PDT 24
Finished Jul 22 05:29:08 PM PDT 24
Peak memory 265052 kb
Host smart-e6dd355e-2c1d-4f39-b062-5666dd306088
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925463892 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.1925463892
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.3072064384
Short name T130
Test name
Test status
Simulation time 27868697600 ps
CPU time 1040.4 seconds
Started Jul 22 05:28:47 PM PDT 24
Finished Jul 22 05:46:08 PM PDT 24
Peak memory 274316 kb
Host smart-8dd30104-f4a3-4b5f-9ec4-4487c970cef0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072064384 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.3072064384
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.3074788440
Short name T999
Test name
Test status
Simulation time 61823300 ps
CPU time 13.47 seconds
Started Jul 22 05:28:51 PM PDT 24
Finished Jul 22 05:29:05 PM PDT 24
Peak memory 265216 kb
Host smart-1dd184bc-18dc-471e-be46-c1c8660130cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074788440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.flash_ctrl_prog_reset.3074788440
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.3181212697
Short name T945
Test name
Test status
Simulation time 170628400 ps
CPU time 327.99 seconds
Started Jul 22 05:28:46 PM PDT 24
Finished Jul 22 05:34:15 PM PDT 24
Peak memory 281988 kb
Host smart-bd17976d-3445-4d55-83cf-ed1fe5436cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181212697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.3181212697
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.2963340512
Short name T976
Test name
Test status
Simulation time 55020200 ps
CPU time 33.57 seconds
Started Jul 22 05:28:54 PM PDT 24
Finished Jul 22 05:29:28 PM PDT 24
Peak memory 268520 kb
Host smart-7bdfe4ee-5a6a-48ca-b2c4-4db0fa8e3bd6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963340512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.2963340512
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.3971985986
Short name T442
Test name
Test status
Simulation time 550504500 ps
CPU time 109.02 seconds
Started Jul 22 05:28:56 PM PDT 24
Finished Jul 22 05:30:45 PM PDT 24
Peak memory 281036 kb
Host smart-fa97e19a-edb7-4330-983b-460b7ba0bb13
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971985986 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_ro.3971985986
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.3219033949
Short name T558
Test name
Test status
Simulation time 4354887300 ps
CPU time 166.56 seconds
Started Jul 22 05:28:53 PM PDT 24
Finished Jul 22 05:31:40 PM PDT 24
Peak memory 281888 kb
Host smart-5a2073ca-73fa-4186-99b8-c1902b63636e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3219033949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.3219033949
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.3860125143
Short name T851
Test name
Test status
Simulation time 1003054200 ps
CPU time 110.26 seconds
Started Jul 22 05:29:09 PM PDT 24
Finished Jul 22 05:30:59 PM PDT 24
Peak memory 292872 kb
Host smart-e6a5eacf-aadf-4dc7-84cc-6441af8ceab7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860125143 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.3860125143
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.62797828
Short name T815
Test name
Test status
Simulation time 16097420500 ps
CPU time 597.88 seconds
Started Jul 22 05:28:56 PM PDT 24
Finished Jul 22 05:38:54 PM PDT 24
Peak memory 309832 kb
Host smart-9ebda76a-6e00-4778-a2c2-9f23e7c44cb4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62797828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.flash_ctrl_rw.62797828
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.2201210722
Short name T798
Test name
Test status
Simulation time 328869600 ps
CPU time 31.72 seconds
Started Jul 22 05:28:55 PM PDT 24
Finished Jul 22 05:29:27 PM PDT 24
Peak memory 273640 kb
Host smart-43e9d673-8d09-4627-bf0d-2cb826fdc623
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201210722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_rw_evict.2201210722
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.3088554514
Short name T664
Test name
Test status
Simulation time 41663600 ps
CPU time 28.38 seconds
Started Jul 22 05:28:55 PM PDT 24
Finished Jul 22 05:29:24 PM PDT 24
Peak memory 268516 kb
Host smart-950aa1ed-1d33-45c2-8fec-56e83e8602fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088554514 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.3088554514
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_serr.2292166445
Short name T812
Test name
Test status
Simulation time 4001275000 ps
CPU time 586.84 seconds
Started Jul 22 05:28:52 PM PDT 24
Finished Jul 22 05:38:40 PM PDT 24
Peak memory 312768 kb
Host smart-491e7dde-f89d-4f1f-aaa1-456f6946d1d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292166445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_s
err.2292166445
Directory /workspace/7.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.2688998119
Short name T413
Test name
Test status
Simulation time 5734554900 ps
CPU time 80.62 seconds
Started Jul 22 05:28:53 PM PDT 24
Finished Jul 22 05:30:15 PM PDT 24
Peak memory 263696 kb
Host smart-dba8cab5-1c9c-4917-867a-4e951a2b147c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688998119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.2688998119
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.268873112
Short name T690
Test name
Test status
Simulation time 72077000 ps
CPU time 53.25 seconds
Started Jul 22 05:28:45 PM PDT 24
Finished Jul 22 05:29:39 PM PDT 24
Peak memory 271308 kb
Host smart-bc6c1efd-0ea7-46f2-9203-a8b091d5145a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268873112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.268873112
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.1412871571
Short name T864
Test name
Test status
Simulation time 5056284600 ps
CPU time 234.59 seconds
Started Jul 22 05:28:54 PM PDT 24
Finished Jul 22 05:32:49 PM PDT 24
Peak memory 265252 kb
Host smart-d27592fa-331d-471b-820b-8796ce90a75b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412871571 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.flash_ctrl_wo.1412871571
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.2614229976
Short name T114
Test name
Test status
Simulation time 15830200 ps
CPU time 16.01 seconds
Started Jul 22 05:35:25 PM PDT 24
Finished Jul 22 05:35:41 PM PDT 24
Peak memory 274904 kb
Host smart-9f2052c8-4ce6-4c84-8915-895a87cf54d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614229976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.2614229976
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.2635689418
Short name T1104
Test name
Test status
Simulation time 74268400 ps
CPU time 113.68 seconds
Started Jul 22 05:35:25 PM PDT 24
Finished Jul 22 05:37:19 PM PDT 24
Peak memory 260060 kb
Host smart-f93c509a-bfbd-4f7c-b25a-ccbee8c20c83
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635689418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.2635689418
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.4291245658
Short name T474
Test name
Test status
Simulation time 54365900 ps
CPU time 16.08 seconds
Started Jul 22 05:35:25 PM PDT 24
Finished Jul 22 05:35:42 PM PDT 24
Peak memory 275028 kb
Host smart-2a79a22a-277c-48b9-a449-7fec5e1f1f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291245658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.4291245658
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.4184669387
Short name T787
Test name
Test status
Simulation time 84841300 ps
CPU time 132.23 seconds
Started Jul 22 05:35:24 PM PDT 24
Finished Jul 22 05:37:36 PM PDT 24
Peak memory 260108 kb
Host smart-0e0fd42e-df3b-47da-aa15-a5fc8fc27842
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184669387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o
tp_reset.4184669387
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.2705028341
Short name T445
Test name
Test status
Simulation time 16427100 ps
CPU time 16.09 seconds
Started Jul 22 05:35:30 PM PDT 24
Finished Jul 22 05:35:47 PM PDT 24
Peak memory 274816 kb
Host smart-51caf9de-6295-4fdb-8b52-65af90a36b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705028341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.2705028341
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.96287254
Short name T652
Test name
Test status
Simulation time 37953600 ps
CPU time 131.94 seconds
Started Jul 22 05:35:23 PM PDT 24
Finished Jul 22 05:37:36 PM PDT 24
Peak memory 265056 kb
Host smart-89a35536-9277-4538-8844-fd46804cd23d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96287254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_otp
_reset.96287254
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.4036327924
Short name T101
Test name
Test status
Simulation time 158649600 ps
CPU time 13.48 seconds
Started Jul 22 05:35:25 PM PDT 24
Finished Jul 22 05:35:39 PM PDT 24
Peak memory 284412 kb
Host smart-1f62690c-4279-4303-8e5e-8a04c658689f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036327924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.4036327924
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.2151748866
Short name T1068
Test name
Test status
Simulation time 148555800 ps
CPU time 134.33 seconds
Started Jul 22 05:35:28 PM PDT 24
Finished Jul 22 05:37:42 PM PDT 24
Peak memory 261236 kb
Host smart-aa96cf20-4b41-43c2-ba5c-efe69a78d55a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151748866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.2151748866
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.1751251711
Short name T486
Test name
Test status
Simulation time 38316700 ps
CPU time 13.5 seconds
Started Jul 22 05:35:27 PM PDT 24
Finished Jul 22 05:35:41 PM PDT 24
Peak memory 284264 kb
Host smart-c9aec72b-6d1c-4377-99ec-4f4d96e1c77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751251711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.1751251711
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.3161113643
Short name T773
Test name
Test status
Simulation time 39867600 ps
CPU time 134.02 seconds
Started Jul 22 05:35:24 PM PDT 24
Finished Jul 22 05:37:39 PM PDT 24
Peak memory 261240 kb
Host smart-c589e799-95ad-45fe-88c0-64d0e755ec07
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161113643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.3161113643
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.1702603091
Short name T768
Test name
Test status
Simulation time 13510700 ps
CPU time 15.58 seconds
Started Jul 22 05:35:31 PM PDT 24
Finished Jul 22 05:35:47 PM PDT 24
Peak memory 284364 kb
Host smart-0cd7b786-9b19-49ab-9288-fbc3e996bc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702603091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.1702603091
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.3038119800
Short name T771
Test name
Test status
Simulation time 212985400 ps
CPU time 133.21 seconds
Started Jul 22 05:35:25 PM PDT 24
Finished Jul 22 05:37:38 PM PDT 24
Peak memory 260040 kb
Host smart-a0fc47f1-12b4-40b3-a313-0d2bf4e5b612
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038119800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.3038119800
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.4248666885
Short name T1018
Test name
Test status
Simulation time 38544800 ps
CPU time 16.16 seconds
Started Jul 22 05:35:24 PM PDT 24
Finished Jul 22 05:35:41 PM PDT 24
Peak memory 274916 kb
Host smart-72b13328-1a8b-473a-9a1f-b76dd149f533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248666885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.4248666885
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.3383558926
Short name T196
Test name
Test status
Simulation time 52724400 ps
CPU time 110.34 seconds
Started Jul 22 05:35:24 PM PDT 24
Finished Jul 22 05:37:14 PM PDT 24
Peak memory 264840 kb
Host smart-2cdcd6fe-b34a-4ea7-b421-8200983cd7f2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383558926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.3383558926
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.3306810052
Short name T454
Test name
Test status
Simulation time 51094200 ps
CPU time 16.42 seconds
Started Jul 22 05:35:25 PM PDT 24
Finished Jul 22 05:35:42 PM PDT 24
Peak memory 284452 kb
Host smart-785a012c-67b3-43fa-9b7c-06c257ad249e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306810052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.3306810052
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.676664070
Short name T887
Test name
Test status
Simulation time 128852100 ps
CPU time 131.31 seconds
Started Jul 22 05:35:26 PM PDT 24
Finished Jul 22 05:37:37 PM PDT 24
Peak memory 260028 kb
Host smart-fef7c20e-546d-4e18-9755-c36204f60a23
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676664070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_ot
p_reset.676664070
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.2555072351
Short name T731
Test name
Test status
Simulation time 44755200 ps
CPU time 15.82 seconds
Started Jul 22 05:35:26 PM PDT 24
Finished Jul 22 05:35:42 PM PDT 24
Peak memory 274928 kb
Host smart-d5c3b55f-ded3-4b1a-b034-383a746e18c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555072351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.2555072351
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.4042842361
Short name T596
Test name
Test status
Simulation time 125813800 ps
CPU time 133.6 seconds
Started Jul 22 05:35:30 PM PDT 24
Finished Jul 22 05:37:44 PM PDT 24
Peak memory 260068 kb
Host smart-cad626fe-8c3f-4ac9-9170-c6b99140b674
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042842361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.4042842361
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.2789399990
Short name T647
Test name
Test status
Simulation time 19509500 ps
CPU time 13.3 seconds
Started Jul 22 05:35:25 PM PDT 24
Finished Jul 22 05:35:39 PM PDT 24
Peak memory 284288 kb
Host smart-e1153a1e-d349-41a9-8d86-8a59f7fc4bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789399990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.2789399990
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.3797371513
Short name T585
Test name
Test status
Simulation time 117888600 ps
CPU time 134 seconds
Started Jul 22 05:35:26 PM PDT 24
Finished Jul 22 05:37:40 PM PDT 24
Peak memory 260200 kb
Host smart-7e4fb415-02b9-425e-bac6-e383f7df4dd4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797371513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.3797371513
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.3347736719
Short name T961
Test name
Test status
Simulation time 129726900 ps
CPU time 13.65 seconds
Started Jul 22 05:29:21 PM PDT 24
Finished Jul 22 05:29:35 PM PDT 24
Peak memory 265280 kb
Host smart-50d854eb-bcdb-480b-b04e-bb9726b5a8ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347736719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.3
347736719
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.943039142
Short name T601
Test name
Test status
Simulation time 38363500 ps
CPU time 16.09 seconds
Started Jul 22 05:29:20 PM PDT 24
Finished Jul 22 05:29:37 PM PDT 24
Peak memory 284504 kb
Host smart-2a96b5b7-de8c-4d58-b718-52ff6d0a58a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943039142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.943039142
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.1453474266
Short name T1020
Test name
Test status
Simulation time 16116100 ps
CPU time 22.13 seconds
Started Jul 22 05:29:19 PM PDT 24
Finished Jul 22 05:29:42 PM PDT 24
Peak memory 265624 kb
Host smart-45378b01-6bf1-4881-8440-907e92ccb9dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453474266 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.1453474266
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.3262936315
Short name T238
Test name
Test status
Simulation time 5216156100 ps
CPU time 2510.98 seconds
Started Jul 22 05:29:11 PM PDT 24
Finished Jul 22 06:11:03 PM PDT 24
Peak memory 262856 kb
Host smart-60981f89-c4da-4346-b1f2-9206ce4c3666
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3262936315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.3262936315
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.694418529
Short name T532
Test name
Test status
Simulation time 6413827200 ps
CPU time 981.02 seconds
Started Jul 22 05:29:11 PM PDT 24
Finished Jul 22 05:45:32 PM PDT 24
Peak memory 273280 kb
Host smart-64a6fe83-a187-49c2-840c-b38d615a1d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694418529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.694418529
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.814969222
Short name T756
Test name
Test status
Simulation time 589193100 ps
CPU time 22.96 seconds
Started Jul 22 05:29:34 PM PDT 24
Finished Jul 22 05:29:57 PM PDT 24
Peak memory 263720 kb
Host smart-e7aca959-db0d-4198-a55e-c4f8d69e6091
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814969222 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.flash_ctrl_fetch_code.814969222
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.1480637821
Short name T295
Test name
Test status
Simulation time 10049029600 ps
CPU time 48.52 seconds
Started Jul 22 05:30:29 PM PDT 24
Finished Jul 22 05:31:19 PM PDT 24
Peak memory 265540 kb
Host smart-36adcb83-f13b-4598-a922-85b4936cf1ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480637821 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.1480637821
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.3233342807
Short name T180
Test name
Test status
Simulation time 17105900 ps
CPU time 13.49 seconds
Started Jul 22 05:30:30 PM PDT 24
Finished Jul 22 05:30:44 PM PDT 24
Peak memory 264868 kb
Host smart-39640652-d4d0-47f5-877b-d9e6ad684fc5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233342807 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.3233342807
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.2389909444
Short name T673
Test name
Test status
Simulation time 40127672800 ps
CPU time 858.8 seconds
Started Jul 22 05:29:18 PM PDT 24
Finished Jul 22 05:43:37 PM PDT 24
Peak memory 264428 kb
Host smart-f82e52ca-cddb-477a-a135-39c5ed48acbe
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389909444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.2389909444
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.2065678031
Short name T462
Test name
Test status
Simulation time 4378417800 ps
CPU time 184.08 seconds
Started Jul 22 05:29:00 PM PDT 24
Finished Jul 22 05:32:04 PM PDT 24
Peak memory 260924 kb
Host smart-0e5c0d56-307a-4c6f-aefd-b85b844bd938
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065678031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.2065678031
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.1740956333
Short name T280
Test name
Test status
Simulation time 3279755600 ps
CPU time 192.66 seconds
Started Jul 22 05:29:28 PM PDT 24
Finished Jul 22 05:32:42 PM PDT 24
Peak memory 284892 kb
Host smart-97f74fae-6e49-4eb6-afe3-c1badf4f0518
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740956333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.1740956333
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1267639308
Short name T506
Test name
Test status
Simulation time 6060534400 ps
CPU time 132.99 seconds
Started Jul 22 05:29:18 PM PDT 24
Finished Jul 22 05:31:32 PM PDT 24
Peak memory 292776 kb
Host smart-57fd57a7-098e-490a-a819-095f3eabb752
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267639308 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.1267639308
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.942663743
Short name T587
Test name
Test status
Simulation time 11351870600 ps
CPU time 87.81 seconds
Started Jul 22 05:30:30 PM PDT 24
Finished Jul 22 05:31:59 PM PDT 24
Peak memory 265292 kb
Host smart-0d5f92c4-a457-4cd7-827c-fd80f8ad5ffe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942663743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.flash_ctrl_intr_wr.942663743
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.741271965
Short name T1026
Test name
Test status
Simulation time 77603270000 ps
CPU time 197.06 seconds
Started Jul 22 05:29:42 PM PDT 24
Finished Jul 22 05:32:59 PM PDT 24
Peak memory 260444 kb
Host smart-dc835cee-563e-4754-abac-e36c54bc1d44
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741
271965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.741271965
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.3846492594
Short name T346
Test name
Test status
Simulation time 980061800 ps
CPU time 93.88 seconds
Started Jul 22 05:29:09 PM PDT 24
Finished Jul 22 05:30:43 PM PDT 24
Peak memory 262636 kb
Host smart-09ceae0a-1607-4f22-94be-494e6f8d551f
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846492594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3846492594
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.1654312882
Short name T973
Test name
Test status
Simulation time 55220300 ps
CPU time 13.9 seconds
Started Jul 22 05:29:21 PM PDT 24
Finished Jul 22 05:29:35 PM PDT 24
Peak memory 264880 kb
Host smart-e58193ea-10e2-4ddc-89d9-3a3dd4f5fcd4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654312882 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.1654312882
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.3480486321
Short name T499
Test name
Test status
Simulation time 33248500 ps
CPU time 133.26 seconds
Started Jul 22 05:29:02 PM PDT 24
Finished Jul 22 05:31:16 PM PDT 24
Peak memory 260028 kb
Host smart-5a5f2074-296b-42c2-8bb5-8734edddefd1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480486321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot
p_reset.3480486321
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.1313411628
Short name T457
Test name
Test status
Simulation time 106320500 ps
CPU time 279.6 seconds
Started Jul 22 05:29:00 PM PDT 24
Finished Jul 22 05:33:40 PM PDT 24
Peak memory 263372 kb
Host smart-c910f747-f505-474f-aba0-a61fc21e199a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313411628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.1313411628
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.3626663385
Short name T915
Test name
Test status
Simulation time 1964626000 ps
CPU time 186.18 seconds
Started Jul 22 05:29:19 PM PDT 24
Finished Jul 22 05:32:26 PM PDT 24
Peak memory 265164 kb
Host smart-125befbd-9224-4553-a6ee-418107772fc9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626663385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.flash_ctrl_prog_reset.3626663385
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.3521620011
Short name T168
Test name
Test status
Simulation time 519456100 ps
CPU time 494.1 seconds
Started Jul 22 05:29:14 PM PDT 24
Finished Jul 22 05:37:29 PM PDT 24
Peak memory 282712 kb
Host smart-9c21e43f-188d-4e24-a80d-4bcf89807aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521620011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3521620011
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.2950019195
Short name T470
Test name
Test status
Simulation time 283723700 ps
CPU time 33.04 seconds
Started Jul 22 05:29:21 PM PDT 24
Finished Jul 22 05:29:55 PM PDT 24
Peak memory 275680 kb
Host smart-c92179e4-a02d-43ef-bf5a-bd1e41d22231
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950019195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.2950019195
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.984833962
Short name T1016
Test name
Test status
Simulation time 654385500 ps
CPU time 115.34 seconds
Started Jul 22 05:29:09 PM PDT 24
Finished Jul 22 05:31:04 PM PDT 24
Peak memory 281748 kb
Host smart-cd9ddd52-5997-47c7-aee5-4dc616caf5f1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984833962 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.flash_ctrl_ro.984833962
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.4170769104
Short name T55
Test name
Test status
Simulation time 1103289800 ps
CPU time 113.39 seconds
Started Jul 22 05:29:19 PM PDT 24
Finished Jul 22 05:31:13 PM PDT 24
Peak memory 281804 kb
Host smart-86f2e8ed-5e94-4f07-b7a4-bf086e2f7f16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4170769104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.4170769104
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.4069998045
Short name T1057
Test name
Test status
Simulation time 1210003100 ps
CPU time 147.16 seconds
Started Jul 22 05:29:18 PM PDT 24
Finished Jul 22 05:31:46 PM PDT 24
Peak memory 281796 kb
Host smart-201eeba3-37d8-4a27-bbce-b18afacdc5df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069998045 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.4069998045
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.3884461641
Short name T281
Test name
Test status
Simulation time 19283226200 ps
CPU time 525.72 seconds
Started Jul 22 05:29:08 PM PDT 24
Finished Jul 22 05:37:55 PM PDT 24
Peak memory 309928 kb
Host smart-001d2e92-8d90-4f84-bd92-9a75e1cc59f4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884461641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.flash_ctrl_rw.3884461641
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_derr.1808507873
Short name T253
Test name
Test status
Simulation time 13214792000 ps
CPU time 554.79 seconds
Started Jul 22 05:29:20 PM PDT 24
Finished Jul 22 05:38:35 PM PDT 24
Peak memory 323140 kb
Host smart-691cb707-8556-4e37-9353-d6d65dc9cadf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808507873 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_rw_derr.1808507873
Directory /workspace/8.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.2635331937
Short name T562
Test name
Test status
Simulation time 40356000 ps
CPU time 30.72 seconds
Started Jul 22 05:29:18 PM PDT 24
Finished Jul 22 05:29:49 PM PDT 24
Peak memory 275708 kb
Host smart-bd1a4934-54e7-4df1-af94-a46bc4b75628
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635331937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_rw_evict.2635331937
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.3848649306
Short name T872
Test name
Test status
Simulation time 23400389000 ps
CPU time 706.6 seconds
Started Jul 22 05:29:09 PM PDT 24
Finished Jul 22 05:40:56 PM PDT 24
Peak memory 312812 kb
Host smart-0a278f92-aad5-4b36-8e35-8326da489c41
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848649306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s
err.3848649306
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.39483578
Short name T412
Test name
Test status
Simulation time 2061424700 ps
CPU time 67.37 seconds
Started Jul 22 05:29:20 PM PDT 24
Finished Jul 22 05:30:28 PM PDT 24
Peak memory 263224 kb
Host smart-ae4a364f-d915-401b-9c14-5be0944fefec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39483578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.39483578
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.2306152836
Short name T960
Test name
Test status
Simulation time 148382800 ps
CPU time 145.71 seconds
Started Jul 22 05:29:01 PM PDT 24
Finished Jul 22 05:31:27 PM PDT 24
Peak memory 278288 kb
Host smart-6252ff2f-9640-437f-8d6d-1b47a2342216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306152836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.2306152836
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.3179474196
Short name T942
Test name
Test status
Simulation time 4061879900 ps
CPU time 150.23 seconds
Started Jul 22 05:29:09 PM PDT 24
Finished Jul 22 05:31:40 PM PDT 24
Peak memory 261100 kb
Host smart-a5f3bc39-7197-4df4-9ee9-31844747af7a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179474196 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.flash_ctrl_wo.3179474196
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.2287738586
Short name T593
Test name
Test status
Simulation time 150742900 ps
CPU time 14.37 seconds
Started Jul 22 05:29:44 PM PDT 24
Finished Jul 22 05:29:59 PM PDT 24
Peak memory 258272 kb
Host smart-b0492fc7-86b7-4f31-8e80-700f50fd9e0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287738586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2
287738586
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.1627356512
Short name T586
Test name
Test status
Simulation time 28971300 ps
CPU time 13.47 seconds
Started Jul 22 05:29:44 PM PDT 24
Finished Jul 22 05:29:58 PM PDT 24
Peak memory 274896 kb
Host smart-0c422b82-6578-4680-8d74-28de94deefad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627356512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.1627356512
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.856674669
Short name T700
Test name
Test status
Simulation time 11004700 ps
CPU time 21.82 seconds
Started Jul 22 05:29:36 PM PDT 24
Finished Jul 22 05:29:59 PM PDT 24
Peak memory 273572 kb
Host smart-d912e191-9c50-465c-ae32-a9b0171948ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856674669 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.856674669
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.405381461
Short name T709
Test name
Test status
Simulation time 7331371200 ps
CPU time 2367.2 seconds
Started Jul 22 05:29:43 PM PDT 24
Finished Jul 22 06:09:11 PM PDT 24
Peak memory 262856 kb
Host smart-e64849cb-c58e-43f1-9c7c-5f001de9d773
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=405381461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.405381461
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.1413144271
Short name T158
Test name
Test status
Simulation time 416215700 ps
CPU time 1028.9 seconds
Started Jul 22 05:29:43 PM PDT 24
Finished Jul 22 05:46:52 PM PDT 24
Peak memory 273424 kb
Host smart-6faede2b-232f-44dc-ad71-b9df2b4f9e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413144271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.1413144271
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.1897192234
Short name T53
Test name
Test status
Simulation time 500414000 ps
CPU time 24.94 seconds
Started Jul 22 05:29:27 PM PDT 24
Finished Jul 22 05:29:52 PM PDT 24
Peak memory 262560 kb
Host smart-7312d647-cb8c-4c4b-b331-ef0270fbeacf
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897192234 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_fetch_code.1897192234
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.840093911
Short name T83
Test name
Test status
Simulation time 10018977200 ps
CPU time 189.34 seconds
Started Jul 22 05:29:45 PM PDT 24
Finished Jul 22 05:32:55 PM PDT 24
Peak memory 297408 kb
Host smart-c73a467e-0074-43ea-a407-9d5c18593b6a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840093911 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.840093911
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.649096499
Short name T633
Test name
Test status
Simulation time 65423200 ps
CPU time 13.55 seconds
Started Jul 22 05:29:45 PM PDT 24
Finished Jul 22 05:29:59 PM PDT 24
Peak memory 258604 kb
Host smart-5fb1425d-7fa0-4762-8c20-ffda5bdf6487
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649096499 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.649096499
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.70758922
Short name T187
Test name
Test status
Simulation time 160179438200 ps
CPU time 975.37 seconds
Started Jul 22 05:29:26 PM PDT 24
Finished Jul 22 05:45:41 PM PDT 24
Peak memory 264312 kb
Host smart-90f37919-f36e-4191-9987-1912af65bfdc
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70758922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.flash_ctrl_hw_rma_reset.70758922
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.330343466
Short name T551
Test name
Test status
Simulation time 7590260900 ps
CPU time 166.55 seconds
Started Jul 22 05:29:27 PM PDT 24
Finished Jul 22 05:32:14 PM PDT 24
Peak memory 263200 kb
Host smart-1a487ed5-cd26-40cc-8af8-0bac7033ecd2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330343466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw
_sec_otp.330343466
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.3399099175
Short name T335
Test name
Test status
Simulation time 10897198900 ps
CPU time 268.79 seconds
Started Jul 22 05:29:39 PM PDT 24
Finished Jul 22 05:34:08 PM PDT 24
Peak memory 284856 kb
Host smart-06d7d653-b828-4420-9251-5a836a05796f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399099175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.3399099175
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.4119579737
Short name T1076
Test name
Test status
Simulation time 66110689900 ps
CPU time 318.56 seconds
Started Jul 22 05:29:47 PM PDT 24
Finished Jul 22 05:35:06 PM PDT 24
Peak memory 294040 kb
Host smart-95e2ff4c-5bfb-4af6-8dd2-747297b07a20
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119579737 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.4119579737
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.3163044106
Short name T901
Test name
Test status
Simulation time 4375551700 ps
CPU time 68.36 seconds
Started Jul 22 05:29:36 PM PDT 24
Finished Jul 22 05:30:45 PM PDT 24
Peak memory 260568 kb
Host smart-6345676a-741f-426f-b23a-f07a7a3862b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163044106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.3163044106
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.2523302752
Short name T958
Test name
Test status
Simulation time 25577402500 ps
CPU time 202.01 seconds
Started Jul 22 05:29:37 PM PDT 24
Finished Jul 22 05:32:59 PM PDT 24
Peak memory 265308 kb
Host smart-432d6197-aaef-4337-9e03-a272f5f4691f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252
3302752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.2523302752
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.1555186879
Short name T722
Test name
Test status
Simulation time 13871582300 ps
CPU time 84.77 seconds
Started Jul 22 05:29:26 PM PDT 24
Finished Jul 22 05:30:51 PM PDT 24
Peak memory 263292 kb
Host smart-60218dd1-47b0-4a03-9ac4-d66aa5aee102
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555186879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.1555186879
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.4203773517
Short name T113
Test name
Test status
Simulation time 26217100 ps
CPU time 13.69 seconds
Started Jul 22 05:29:45 PM PDT 24
Finished Jul 22 05:29:59 PM PDT 24
Peak memory 259836 kb
Host smart-f5f931b5-3cf5-4a52-b596-4cbc7e6ec2c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203773517 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.4203773517
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.3967515552
Short name T943
Test name
Test status
Simulation time 231053400 ps
CPU time 130.65 seconds
Started Jul 22 05:29:32 PM PDT 24
Finished Jul 22 05:31:43 PM PDT 24
Peak memory 265012 kb
Host smart-d34a6c36-bd48-4a84-bc53-910a7ca74dcd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967515552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.3967515552
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.2435601567
Short name T981
Test name
Test status
Simulation time 78321900 ps
CPU time 150.73 seconds
Started Jul 22 05:29:32 PM PDT 24
Finished Jul 22 05:32:03 PM PDT 24
Peak memory 263192 kb
Host smart-82b56742-17bb-4a27-bf55-af16590b85e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2435601567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.2435601567
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.4194406838
Short name T920
Test name
Test status
Simulation time 131800600 ps
CPU time 17.49 seconds
Started Jul 22 05:29:37 PM PDT 24
Finished Jul 22 05:29:55 PM PDT 24
Peak memory 260076 kb
Host smart-4b3c77b7-c3bd-4ebe-abe7-1aade29b9cca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194406838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.flash_ctrl_prog_reset.4194406838
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.2660066729
Short name T924
Test name
Test status
Simulation time 46441300 ps
CPU time 233.03 seconds
Started Jul 22 05:29:36 PM PDT 24
Finished Jul 22 05:33:30 PM PDT 24
Peak memory 280320 kb
Host smart-ad188946-c02e-41b4-8ef4-8a033b57ef09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660066729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.2660066729
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.1440375540
Short name T626
Test name
Test status
Simulation time 227177900 ps
CPU time 36.06 seconds
Started Jul 22 05:29:47 PM PDT 24
Finished Jul 22 05:30:24 PM PDT 24
Peak memory 275664 kb
Host smart-cf859139-101b-448a-bf13-45a571531d53
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440375540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.1440375540
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.863398979
Short name T44
Test name
Test status
Simulation time 2185355000 ps
CPU time 113.41 seconds
Started Jul 22 05:29:35 PM PDT 24
Finished Jul 22 05:31:29 PM PDT 24
Peak memory 281844 kb
Host smart-167ca318-d751-49e4-a50a-18d342ffbbae
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863398979 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.flash_ctrl_ro.863398979
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.86764882
Short name T65
Test name
Test status
Simulation time 1166545600 ps
CPU time 135.1 seconds
Started Jul 22 05:29:36 PM PDT 24
Finished Jul 22 05:31:52 PM PDT 24
Peak memory 281856 kb
Host smart-144d9f2d-c94a-41e6-ac19-9c0f07b93898
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
86764882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.86764882
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.1473831836
Short name T6
Test name
Test status
Simulation time 2144793700 ps
CPU time 139.26 seconds
Started Jul 22 05:29:36 PM PDT 24
Finished Jul 22 05:31:55 PM PDT 24
Peak memory 281800 kb
Host smart-362e5c50-c44e-4705-95db-e583c321fe22
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473831836 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.1473831836
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.264556687
Short name T1051
Test name
Test status
Simulation time 41261482200 ps
CPU time 733.86 seconds
Started Jul 22 05:29:35 PM PDT 24
Finished Jul 22 05:41:49 PM PDT 24
Peak memory 314580 kb
Host smart-b3a94a38-60cc-44ac-a483-1e49143b61e7
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264556687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.flash_ctrl_rw.264556687
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.4063507655
Short name T862
Test name
Test status
Simulation time 32596000 ps
CPU time 31.8 seconds
Started Jul 22 05:29:35 PM PDT 24
Finished Jul 22 05:30:07 PM PDT 24
Peak memory 268424 kb
Host smart-3adb41d0-dafe-49d6-a63f-ada325d559ec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063507655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.4063507655
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.1131982790
Short name T279
Test name
Test status
Simulation time 27080600 ps
CPU time 31.14 seconds
Started Jul 22 05:29:35 PM PDT 24
Finished Jul 22 05:30:07 PM PDT 24
Peak memory 273576 kb
Host smart-1d3c8737-7586-4480-8072-e4fa83efdebf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131982790 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.1131982790
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.421366609
Short name T510
Test name
Test status
Simulation time 3913022900 ps
CPU time 672.88 seconds
Started Jul 22 05:29:36 PM PDT 24
Finished Jul 22 05:40:49 PM PDT 24
Peak memory 326448 kb
Host smart-107406b2-3ebb-4540-a910-1eb8e513b90d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421366609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_se
rr.421366609
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.4038555790
Short name T498
Test name
Test status
Simulation time 4532920600 ps
CPU time 76.26 seconds
Started Jul 22 05:29:44 PM PDT 24
Finished Jul 22 05:31:00 PM PDT 24
Peak memory 263032 kb
Host smart-cb2bd10c-3ecd-47e4-bef9-1d791ac6f205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038555790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.4038555790
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.693077002
Short name T635
Test name
Test status
Simulation time 18399300 ps
CPU time 50.18 seconds
Started Jul 22 05:29:19 PM PDT 24
Finished Jul 22 05:30:09 PM PDT 24
Peak memory 271332 kb
Host smart-81ea8bf2-7848-41ac-8960-da0761c2bd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693077002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.693077002
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.1194857882
Short name T18
Test name
Test status
Simulation time 3547027100 ps
CPU time 191.08 seconds
Started Jul 22 05:29:35 PM PDT 24
Finished Jul 22 05:32:47 PM PDT 24
Peak memory 265264 kb
Host smart-9d28d8c8-1200-454a-b8f3-b2eb09932501
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194857882 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.flash_ctrl_wo.1194857882
Directory /workspace/9.flash_ctrl_wo/latest
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