Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24743012	1		T1	12690		T2	161689		T3	303
full_word	8134081	1		T1	10238		T2	30183		T3	115

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32876803	1		T1	22928		T2	191872		T3	418
auto[TlIntgErrCmd]	100	1		T102	5		T104	9		T255	7
auto[TlIntgErrData]	97	1		T102	1		T104	4		T255	7
auto[TlIntgErrBoth]	93	1		T102	4		T104	7		T255	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28219470	1		T1	19579		T2	171342		T3	337
auto[1]	4657623	1		T1	3349		T2	20530		T3	81

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23947007	1		T1	11768		T2	158998		T3	285
auto[TlIntgErrNone]	partial	auto[1]	795741	1		T1	922		T2	2691		T3	18
auto[TlIntgErrNone]	full_word	auto[0]	4272347	1		T1	7811		T2	12344		T3	52
auto[TlIntgErrNone]	full_word	auto[1]	3861708	1		T1	2427		T2	17839		T3	63
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T102	3		T104	2		T255	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T102	2		T104	6		T255	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T379	2		T292	1		T375	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T104	1		T290	1		T292	1
auto[TlIntgErrData]	partial	auto[0]	32	1		T102	1		T104	1		T255	2
auto[TlIntgErrData]	partial	auto[1]	55	1		T104	3		T255	5		T297	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T297	1		T290	1		T278	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T375	1		T380	1		T378	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T102	2		T104	2		T255	4
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T102	2		T104	5		T255	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T255	1		T381	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T297	1		T290	2		T375	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19752	1		T102	7		T103	289		T104	15
full_word	3935720	1		T1	16518		T2	41700		T3	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3955208	1		T1	16518		T2	41700		T3	6
auto[TlIntgErrCmd]	79	1		T102	1		T104	5		T255	6
auto[TlIntgErrData]	101	1		T102	7		T104	6		T255	9
auto[TlIntgErrBoth]	84	1		T104	6		T255	5		T297	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3929624	1		T1	16518		T2	41700		T3	6
auto[1]	25848	1		T102	5		T103	406		T104	11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1266	1		T103	17		T220	11		T221	3
auto[TlIntgErrNone]	partial	auto[1]	18248	1		T103	272		T220	170		T221	118
auto[TlIntgErrNone]	full_word	auto[0]	3928249	1		T1	16518		T2	41700		T3	6
auto[TlIntgErrNone]	full_word	auto[1]	7445	1		T103	134		T220	33		T221	25
auto[TlIntgErrCmd]	partial	auto[0]	21	1		T104	2		T297	3		T290	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T102	1		T104	3		T255	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T255	1		T292	1		T382	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T292	1		T377	1		-	-
auto[TlIntgErrData]	partial	auto[0]	48	1		T102	3		T104	1		T255	4
auto[TlIntgErrData]	partial	auto[1]	42	1		T102	3		T104	4		T255	5
auto[TlIntgErrData]	full_word	auto[0]	6	1		T104	1		T297	2		T382	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T102	1		T278	2		T383	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T104	2		T255	2		T297	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1		T104	3		T255	3		T297	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T384	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1		T104	1		T297	1		T292	1