Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1523707284	1520211396	0	0
CheckNGreaterZero_A	4164	4164	0	0
GntImpliesReady_A	1523707284	394587627	0	0
GntImpliesValid_A	1523707284	394587627	0	0
GrantKnown_A	1523707284	1520211396	0	0
IdxKnown_A	1523707284	1520211396	0	0
IndexIsCorrect_A	1523707284	394587627	0	0
NoReadyValidNoGrant_A	1523707284	182198036	0	0
Priority_A	1523707284	418067823	0	0
ReadyAndValidImplyGrant_A	1523707284	394587627	0	0
ReqAndReadyImplyGrant_A	1523707284	394587627	0	0
ReqImpliesValid_A	1523707284	418067823	0	0
ValidKnown_A	1523707284	1520211396	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523707284	1520211396	0	0
T1	224032	223728	0	0
T2	1568972	1568572	0	0
T3	8828	8376	0	0
T4	1763764	1763496	0	0
T15	144628	144324	0	0
T16	336204	315660	0	0
T17	7296	7008	0	0
T18	259940	259312	0	0
T19	247428	247084	0	0
T20	613860	613344	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4164	4164	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523707284	394587627	0	0
T1	224032	45106	0	0
T2	1568972	514746	0	0
T3	8828	362	0	0
T4	1763764	559982	0	0
T15	144628	2648	0	0
T16	336204	102288	0	0
T17	7296	356	0	0
T18	259940	42906	0	0
T19	247428	42244	0	0
T20	613860	82740	0	0
T24	0	582	0	0
T33	0	41336	0	0
T46	0	23598	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523707284	394587627	0	0
T1	224032	45106	0	0
T2	1568972	514746	0	0
T3	8828	362	0	0
T4	1763764	559982	0	0
T15	144628	2648	0	0
T16	336204	102288	0	0
T17	7296	356	0	0
T18	259940	42906	0	0
T19	247428	42244	0	0
T20	613860	82740	0	0
T24	0	582	0	0
T33	0	41336	0	0
T46	0	23598	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523707284	1520211396	0	0
T1	224032	223728	0	0
T2	1568972	1568572	0	0
T3	8828	8376	0	0
T4	1763764	1763496	0	0
T15	144628	144324	0	0
T16	336204	315660	0	0
T17	7296	7008	0	0
T18	259940	259312	0	0
T19	247428	247084	0	0
T20	613860	613344	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523707284	1520211396	0	0
T1	224032	223728	0	0
T2	1568972	1568572	0	0
T3	8828	8376	0	0
T4	1763764	1763496	0	0
T15	144628	144324	0	0
T16	336204	315660	0	0
T17	7296	7008	0	0
T18	259940	259312	0	0
T19	247428	247084	0	0
T20	613860	613344	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523707284	394587627	0	0
T1	224032	45106	0	0
T2	1568972	514746	0	0
T3	8828	362	0	0
T4	1763764	559982	0	0
T15	144628	2648	0	0
T16	336204	102288	0	0
T17	7296	356	0	0
T18	259940	42906	0	0
T19	247428	42244	0	0
T20	613860	82740	0	0
T24	0	582	0	0
T33	0	41336	0	0
T46	0	23598	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523707284	182198036	0	0
T1	224032	60104	0	0
T2	1568972	201316	0	0
T3	8828	740	0	0
T4	1763764	364402	0	0
T15	144628	2816	0	0
T16	336204	25352	0	0
T17	7296	696	0	0
T18	259940	424	0	0
T19	247428	120428	0	0
T20	613860	225800	0	0
T24	0	172	0	0
T33	0	1297108	0	0
T46	0	27806	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523707284	418067823	0	0
T1	224032	56076	0	0
T2	1568972	618474	0	0
T3	8828	362	0	0
T4	1763764	629526	0	0
T15	144628	2648	0	0
T16	336204	102288	0	0
T17	7296	356	0	0
T18	259940	42906	0	0
T19	247428	45456	0	0
T20	613860	86526	0	0
T24	0	582	0	0
T33	0	256946	0	0
T46	0	35820	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523707284	394587627	0	0
T1	224032	45106	0	0
T2	1568972	514746	0	0
T3	8828	362	0	0
T4	1763764	559982	0	0
T15	144628	2648	0	0
T16	336204	102288	0	0
T17	7296	356	0	0
T18	259940	42906	0	0
T19	247428	42244	0	0
T20	613860	82740	0	0
T24	0	582	0	0
T33	0	41336	0	0
T46	0	23598	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523707284	394587627	0	0
T1	224032	45106	0	0
T2	1568972	514746	0	0
T3	8828	362	0	0
T4	1763764	559982	0	0
T15	144628	2648	0	0
T16	336204	102288	0	0
T17	7296	356	0	0
T18	259940	42906	0	0
T19	247428	42244	0	0
T20	613860	82740	0	0
T24	0	582	0	0
T33	0	41336	0	0
T46	0	23598	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523707284	418067823	0	0
T1	224032	56076	0	0
T2	1568972	618474	0	0
T3	8828	362	0	0
T4	1763764	629526	0	0
T15	144628	2648	0	0
T16	336204	102288	0	0
T17	7296	356	0	0
T18	259940	42906	0	0
T19	247428	45456	0	0
T20	613860	86526	0	0
T24	0	582	0	0
T33	0	256946	0	0
T46	0	35820	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523707284	1520211396	0	0
T1	224032	223728	0	0
T2	1568972	1568572	0	0
T3	8828	8376	0	0
T4	1763764	1763496	0	0
T15	144628	144324	0	0
T16	336204	315660	0	0
T17	7296	7008	0	0
T18	259940	259312	0	0
T19	247428	247084	0	0
T20	613860	613344	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380926821	380052849	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	380926821	102978759	0	0
GntImpliesValid_A	380926821	102978759	0	0
GrantKnown_A	380926821	380052849	0	0
IdxKnown_A	380926821	380052849	0	0
IndexIsCorrect_A	380926821	102978759	0	0
NoReadyValidNoGrant_A	380926821	47119637	0	0
Priority_A	380926821	108926621	0	0
ReadyAndValidImplyGrant_A	380926821	102978759	0	0
ReqAndReadyImplyGrant_A	380926821	102978759	0	0
ReqImpliesValid_A	380926821	108926621	0	0
ValidKnown_A	380926821	380052849	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	102978759	0	0
T1	56008	12950	0	0
T2	392243	91488	0	0
T3	2207	174	0	0
T4	440941	136915	0	0
T15	36157	1324	0	0
T16	84051	51144	0	0
T17	1824	178	0	0
T18	64985	13458	0	0
T19	61857	9900	0	0
T20	153465	20583	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	102978759	0	0
T1	56008	12950	0	0
T2	392243	91488	0	0
T3	2207	174	0	0
T4	440941	136915	0	0
T15	36157	1324	0	0
T16	84051	51144	0	0
T17	1824	178	0	0
T18	64985	13458	0	0
T19	61857	9900	0	0
T20	153465	20583	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	102978759	0	0
T1	56008	12950	0	0
T2	392243	91488	0	0
T3	2207	174	0	0
T4	440941	136915	0	0
T15	36157	1324	0	0
T16	84051	51144	0	0
T17	1824	178	0	0
T18	64985	13458	0	0
T19	61857	9900	0	0
T20	153465	20583	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	47119637	0	0
T1	56008	17296	0	0
T2	392243	39146	0	0
T3	2207	351	0	0
T4	440941	94881	0	0
T15	36157	1408	0	0
T16	84051	12676	0	0
T17	1824	348	0	0
T18	64985	158	0	0
T19	61857	28408	0	0
T20	153465	56320	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	108926621	0	0
T1	56008	16179	0	0
T2	392243	112131	0	0
T3	2207	174	0	0
T4	440941	155946	0	0
T15	36157	1324	0	0
T16	84051	51144	0	0
T17	1824	178	0	0
T18	64985	13458	0	0
T19	61857	10758	0	0
T20	153465	21373	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	102978759	0	0
T1	56008	12950	0	0
T2	392243	91488	0	0
T3	2207	174	0	0
T4	440941	136915	0	0
T15	36157	1324	0	0
T16	84051	51144	0	0
T17	1824	178	0	0
T18	64985	13458	0	0
T19	61857	9900	0	0
T20	153465	20583	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	102978759	0	0
T1	56008	12950	0	0
T2	392243	91488	0	0
T3	2207	174	0	0
T4	440941	136915	0	0
T15	36157	1324	0	0
T16	84051	51144	0	0
T17	1824	178	0	0
T18	64985	13458	0	0
T19	61857	9900	0	0
T20	153465	20583	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	108926621	0	0
T1	56008	16179	0	0
T2	392243	112131	0	0
T3	2207	174	0	0
T4	440941	155946	0	0
T15	36157	1324	0	0
T16	84051	51144	0	0
T17	1824	178	0	0
T18	64985	13458	0	0
T19	61857	10758	0	0
T20	153465	21373	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380926821	380052849	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	380926821	102978694	0	0
GntImpliesValid_A	380926821	102978694	0	0
GrantKnown_A	380926821	380052849	0	0
IdxKnown_A	380926821	380052849	0	0
IndexIsCorrect_A	380926821	102978694	0	0
NoReadyValidNoGrant_A	380926821	47119563	0	0
Priority_A	380926821	108926630	0	0
ReadyAndValidImplyGrant_A	380926821	102978694	0	0
ReqAndReadyImplyGrant_A	380926821	102978694	0	0
ReqImpliesValid_A	380926821	108926630	0	0
ValidKnown_A	380926821	380052849	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	102978694	0	0
T1	56008	12950	0	0
T2	392243	91488	0	0
T3	2207	174	0	0
T4	440941	136915	0	0
T15	36157	1324	0	0
T16	84051	51144	0	0
T17	1824	178	0	0
T18	64985	13458	0	0
T19	61857	9900	0	0
T20	153465	20583	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	102978694	0	0
T1	56008	12950	0	0
T2	392243	91488	0	0
T3	2207	174	0	0
T4	440941	136915	0	0
T15	36157	1324	0	0
T16	84051	51144	0	0
T17	1824	178	0	0
T18	64985	13458	0	0
T19	61857	9900	0	0
T20	153465	20583	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	102978694	0	0
T1	56008	12950	0	0
T2	392243	91488	0	0
T3	2207	174	0	0
T4	440941	136915	0	0
T15	36157	1324	0	0
T16	84051	51144	0	0
T17	1824	178	0	0
T18	64985	13458	0	0
T19	61857	9900	0	0
T20	153465	20583	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	47119563	0	0
T1	56008	17296	0	0
T2	392243	39146	0	0
T3	2207	351	0	0
T4	440941	94881	0	0
T15	36157	1408	0	0
T16	84051	12676	0	0
T17	1824	348	0	0
T18	64985	158	0	0
T19	61857	28408	0	0
T20	153465	56320	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	108926630	0	0
T1	56008	16179	0	0
T2	392243	112131	0	0
T3	2207	174	0	0
T4	440941	155946	0	0
T15	36157	1324	0	0
T16	84051	51144	0	0
T17	1824	178	0	0
T18	64985	13458	0	0
T19	61857	10758	0	0
T20	153465	21373	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	102978694	0	0
T1	56008	12950	0	0
T2	392243	91488	0	0
T3	2207	174	0	0
T4	440941	136915	0	0
T15	36157	1324	0	0
T16	84051	51144	0	0
T17	1824	178	0	0
T18	64985	13458	0	0
T19	61857	9900	0	0
T20	153465	20583	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	102978694	0	0
T1	56008	12950	0	0
T2	392243	91488	0	0
T3	2207	174	0	0
T4	440941	136915	0	0
T15	36157	1324	0	0
T16	84051	51144	0	0
T17	1824	178	0	0
T18	64985	13458	0	0
T19	61857	9900	0	0
T20	153465	20583	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	108926630	0	0
T1	56008	16179	0	0
T2	392243	112131	0	0
T3	2207	174	0	0
T4	440941	155946	0	0
T15	36157	1324	0	0
T16	84051	51144	0	0
T17	1824	178	0	0
T18	64985	13458	0	0
T19	61857	10758	0	0
T20	153465	21373	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380926821	380052849	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	380926821	94315087	0	0
GntImpliesValid_A	380926821	94315087	0	0
GrantKnown_A	380926821	380052849	0	0
IdxKnown_A	380926821	380052849	0	0
IndexIsCorrect_A	380926821	94315087	0	0
NoReadyValidNoGrant_A	380926821	43979418	0	0
Priority_A	380926821	100107286	0	0
ReadyAndValidImplyGrant_A	380926821	94315087	0	0
ReqAndReadyImplyGrant_A	380926821	94315087	0	0
ReqImpliesValid_A	380926821	100107286	0	0
ValidKnown_A	380926821	380052849	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	94315087	0	0
T1	56008	9603	0	0
T2	392243	165885	0	0
T3	2207	7	0	0
T4	440941	143076	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	7995	0	0
T19	61857	11222	0	0
T20	153465	20787	0	0
T24	0	291	0	0
T33	0	20668	0	0
T46	0	11799	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	94315087	0	0
T1	56008	9603	0	0
T2	392243	165885	0	0
T3	2207	7	0	0
T4	440941	143076	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	7995	0	0
T19	61857	11222	0	0
T20	153465	20787	0	0
T24	0	291	0	0
T33	0	20668	0	0
T46	0	11799	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	94315087	0	0
T1	56008	9603	0	0
T2	392243	165885	0	0
T3	2207	7	0	0
T4	440941	143076	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	7995	0	0
T19	61857	11222	0	0
T20	153465	20787	0	0
T24	0	291	0	0
T33	0	20668	0	0
T46	0	11799	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	43979418	0	0
T1	56008	12756	0	0
T2	392243	61512	0	0
T3	2207	19	0	0
T4	440941	87320	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	54	0	0
T19	61857	31806	0	0
T20	153465	56580	0	0
T24	0	86	0	0
T33	0	648554	0	0
T46	0	13903	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	100107286	0	0
T1	56008	11859	0	0
T2	392243	197106	0	0
T3	2207	7	0	0
T4	440941	158817	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	7995	0	0
T19	61857	11970	0	0
T20	153465	21890	0	0
T24	0	291	0	0
T33	0	128473	0	0
T46	0	17910	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	94315087	0	0
T1	56008	9603	0	0
T2	392243	165885	0	0
T3	2207	7	0	0
T4	440941	143076	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	7995	0	0
T19	61857	11222	0	0
T20	153465	20787	0	0
T24	0	291	0	0
T33	0	20668	0	0
T46	0	11799	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	94315087	0	0
T1	56008	9603	0	0
T2	392243	165885	0	0
T3	2207	7	0	0
T4	440941	143076	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	7995	0	0
T19	61857	11222	0	0
T20	153465	20787	0	0
T24	0	291	0	0
T33	0	20668	0	0
T46	0	11799	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	100107286	0	0
T1	56008	11859	0	0
T2	392243	197106	0	0
T3	2207	7	0	0
T4	440941	158817	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	7995	0	0
T19	61857	11970	0	0
T20	153465	21890	0	0
T24	0	291	0	0
T33	0	128473	0	0
T46	0	17910	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380926821	380052849	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	380926821	94315087	0	0
GntImpliesValid_A	380926821	94315087	0	0
GrantKnown_A	380926821	380052849	0	0
IdxKnown_A	380926821	380052849	0	0
IndexIsCorrect_A	380926821	94315087	0	0
NoReadyValidNoGrant_A	380926821	43979418	0	0
Priority_A	380926821	100107286	0	0
ReadyAndValidImplyGrant_A	380926821	94315087	0	0
ReqAndReadyImplyGrant_A	380926821	94315087	0	0
ReqImpliesValid_A	380926821	100107286	0	0
ValidKnown_A	380926821	380052849	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	94315087	0	0
T1	56008	9603	0	0
T2	392243	165885	0	0
T3	2207	7	0	0
T4	440941	143076	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	7995	0	0
T19	61857	11222	0	0
T20	153465	20787	0	0
T24	0	291	0	0
T33	0	20668	0	0
T46	0	11799	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	94315087	0	0
T1	56008	9603	0	0
T2	392243	165885	0	0
T3	2207	7	0	0
T4	440941	143076	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	7995	0	0
T19	61857	11222	0	0
T20	153465	20787	0	0
T24	0	291	0	0
T33	0	20668	0	0
T46	0	11799	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	94315087	0	0
T1	56008	9603	0	0
T2	392243	165885	0	0
T3	2207	7	0	0
T4	440941	143076	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	7995	0	0
T19	61857	11222	0	0
T20	153465	20787	0	0
T24	0	291	0	0
T33	0	20668	0	0
T46	0	11799	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	43979418	0	0
T1	56008	12756	0	0
T2	392243	61512	0	0
T3	2207	19	0	0
T4	440941	87320	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	54	0	0
T19	61857	31806	0	0
T20	153465	56580	0	0
T24	0	86	0	0
T33	0	648554	0	0
T46	0	13903	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	100107286	0	0
T1	56008	11859	0	0
T2	392243	197106	0	0
T3	2207	7	0	0
T4	440941	158817	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	7995	0	0
T19	61857	11970	0	0
T20	153465	21890	0	0
T24	0	291	0	0
T33	0	128473	0	0
T46	0	17910	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	94315087	0	0
T1	56008	9603	0	0
T2	392243	165885	0	0
T3	2207	7	0	0
T4	440941	143076	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	7995	0	0
T19	61857	11222	0	0
T20	153465	20787	0	0
T24	0	291	0	0
T33	0	20668	0	0
T46	0	11799	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	94315087	0	0
T1	56008	9603	0	0
T2	392243	165885	0	0
T3	2207	7	0	0
T4	440941	143076	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	7995	0	0
T19	61857	11222	0	0
T20	153465	20787	0	0
T24	0	291	0	0
T33	0	20668	0	0
T46	0	11799	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	100107286	0	0
T1	56008	11859	0	0
T2	392243	197106	0	0
T3	2207	7	0	0
T4	440941	158817	0	0
T15	36157	0	0	0
T16	84051	0	0	0
T17	1824	0	0	0
T18	64985	7995	0	0
T19	61857	11970	0	0
T20	153465	21890	0	0
T24	0	291	0	0
T33	0	128473	0	0
T46	0	17910	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380926821	380052849	0	0
T1	56008	55932	0	0
T2	392243	392143	0	0
T3	2207	2094	0	0
T4	440941	440874	0	0
T15	36157	36081	0	0
T16	84051	78915	0	0
T17	1824	1752	0	0
T18	64985	64828	0	0
T19	61857	61771	0	0
T20	153465	153336	0	0