Line Coverage for Instance : tb.dut.u_sw_rd_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sw_rd_fifo
| Total | Covered | Percent |
Conditions | 24 | 19 | 79.17 |
Logical | 24 | 19 | 79.17 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T15,T21,T29 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (39'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sw_rd_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sw_rd_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
50316837 |
0 |
0 |
T1 |
56008 |
27220 |
0 |
0 |
T2 |
392243 |
41659 |
0 |
0 |
T3 |
2207 |
210 |
0 |
0 |
T4 |
440941 |
27556 |
0 |
0 |
T15 |
36157 |
26638 |
0 |
0 |
T16 |
84051 |
6883 |
0 |
0 |
T17 |
1824 |
615 |
0 |
0 |
T18 |
64985 |
91 |
0 |
0 |
T19 |
61857 |
24591 |
0 |
0 |
T20 |
153465 |
138039 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
380052849 |
0 |
0 |
T1 |
56008 |
55932 |
0 |
0 |
T2 |
392243 |
392143 |
0 |
0 |
T3 |
2207 |
2094 |
0 |
0 |
T4 |
440941 |
440874 |
0 |
0 |
T15 |
36157 |
36081 |
0 |
0 |
T16 |
84051 |
78915 |
0 |
0 |
T17 |
1824 |
1752 |
0 |
0 |
T18 |
64985 |
64828 |
0 |
0 |
T19 |
61857 |
61771 |
0 |
0 |
T20 |
153465 |
153336 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
380052849 |
0 |
0 |
T1 |
56008 |
55932 |
0 |
0 |
T2 |
392243 |
392143 |
0 |
0 |
T3 |
2207 |
2094 |
0 |
0 |
T4 |
440941 |
440874 |
0 |
0 |
T15 |
36157 |
36081 |
0 |
0 |
T16 |
84051 |
78915 |
0 |
0 |
T17 |
1824 |
1752 |
0 |
0 |
T18 |
64985 |
64828 |
0 |
0 |
T19 |
61857 |
61771 |
0 |
0 |
T20 |
153465 |
153336 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
380052849 |
0 |
0 |
T1 |
56008 |
55932 |
0 |
0 |
T2 |
392243 |
392143 |
0 |
0 |
T3 |
2207 |
2094 |
0 |
0 |
T4 |
440941 |
440874 |
0 |
0 |
T15 |
36157 |
36081 |
0 |
0 |
T16 |
84051 |
78915 |
0 |
0 |
T17 |
1824 |
1752 |
0 |
0 |
T18 |
64985 |
64828 |
0 |
0 |
T19 |
61857 |
61771 |
0 |
0 |
T20 |
153465 |
153336 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
50316837 |
0 |
0 |
T1 |
56008 |
27220 |
0 |
0 |
T2 |
392243 |
41659 |
0 |
0 |
T3 |
2207 |
210 |
0 |
0 |
T4 |
440941 |
27556 |
0 |
0 |
T15 |
36157 |
26638 |
0 |
0 |
T16 |
84051 |
6883 |
0 |
0 |
T17 |
1824 |
615 |
0 |
0 |
T18 |
64985 |
91 |
0 |
0 |
T19 |
61857 |
24591 |
0 |
0 |
T20 |
153465 |
138039 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
34055914 |
0 |
0 |
T1 |
56008 |
28232 |
0 |
0 |
T2 |
392243 |
133012 |
0 |
0 |
T3 |
2207 |
24 |
0 |
0 |
T4 |
440941 |
186228 |
0 |
0 |
T15 |
36157 |
0 |
0 |
0 |
T16 |
84051 |
0 |
0 |
0 |
T17 |
1824 |
0 |
0 |
0 |
T18 |
64985 |
0 |
0 |
0 |
T19 |
61857 |
45371 |
0 |
0 |
T20 |
153465 |
46942 |
0 |
0 |
T24 |
0 |
74 |
0 |
0 |
T33 |
0 |
596320 |
0 |
0 |
T46 |
0 |
29058 |
0 |
0 |
T47 |
0 |
524 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
380052849 |
0 |
0 |
T1 |
56008 |
55932 |
0 |
0 |
T2 |
392243 |
392143 |
0 |
0 |
T3 |
2207 |
2094 |
0 |
0 |
T4 |
440941 |
440874 |
0 |
0 |
T15 |
36157 |
36081 |
0 |
0 |
T16 |
84051 |
78915 |
0 |
0 |
T17 |
1824 |
1752 |
0 |
0 |
T18 |
64985 |
64828 |
0 |
0 |
T19 |
61857 |
61771 |
0 |
0 |
T20 |
153465 |
153336 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
380052849 |
0 |
0 |
T1 |
56008 |
55932 |
0 |
0 |
T2 |
392243 |
392143 |
0 |
0 |
T3 |
2207 |
2094 |
0 |
0 |
T4 |
440941 |
440874 |
0 |
0 |
T15 |
36157 |
36081 |
0 |
0 |
T16 |
84051 |
78915 |
0 |
0 |
T17 |
1824 |
1752 |
0 |
0 |
T18 |
64985 |
64828 |
0 |
0 |
T19 |
61857 |
61771 |
0 |
0 |
T20 |
153465 |
153336 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
380052849 |
0 |
0 |
T1 |
56008 |
55932 |
0 |
0 |
T2 |
392243 |
392143 |
0 |
0 |
T3 |
2207 |
2094 |
0 |
0 |
T4 |
440941 |
440874 |
0 |
0 |
T15 |
36157 |
36081 |
0 |
0 |
T16 |
84051 |
78915 |
0 |
0 |
T17 |
1824 |
1752 |
0 |
0 |
T18 |
64985 |
64828 |
0 |
0 |
T19 |
61857 |
61771 |
0 |
0 |
T20 |
153465 |
153336 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
34055914 |
0 |
0 |
T1 |
56008 |
28232 |
0 |
0 |
T2 |
392243 |
133012 |
0 |
0 |
T3 |
2207 |
24 |
0 |
0 |
T4 |
440941 |
186228 |
0 |
0 |
T15 |
36157 |
0 |
0 |
0 |
T16 |
84051 |
0 |
0 |
0 |
T17 |
1824 |
0 |
0 |
0 |
T18 |
64985 |
0 |
0 |
0 |
T19 |
61857 |
45371 |
0 |
0 |
T20 |
153465 |
46942 |
0 |
0 |
T24 |
0 |
74 |
0 |
0 |
T33 |
0 |
596320 |
0 |
0 |
T46 |
0 |
29058 |
0 |
0 |
T47 |
0 |
524 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
32637600 |
0 |
0 |
T1 |
56008 |
28232 |
0 |
0 |
T2 |
392243 |
133012 |
0 |
0 |
T3 |
2207 |
24 |
0 |
0 |
T4 |
440941 |
186228 |
0 |
0 |
T15 |
36157 |
0 |
0 |
0 |
T16 |
84051 |
0 |
0 |
0 |
T17 |
1824 |
0 |
0 |
0 |
T18 |
64985 |
0 |
0 |
0 |
T19 |
61857 |
45371 |
0 |
0 |
T20 |
153465 |
46942 |
0 |
0 |
T24 |
0 |
74 |
0 |
0 |
T33 |
0 |
596320 |
0 |
0 |
T46 |
0 |
29058 |
0 |
0 |
T47 |
0 |
524 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
380052849 |
0 |
0 |
T1 |
56008 |
55932 |
0 |
0 |
T2 |
392243 |
392143 |
0 |
0 |
T3 |
2207 |
2094 |
0 |
0 |
T4 |
440941 |
440874 |
0 |
0 |
T15 |
36157 |
36081 |
0 |
0 |
T16 |
84051 |
78915 |
0 |
0 |
T17 |
1824 |
1752 |
0 |
0 |
T18 |
64985 |
64828 |
0 |
0 |
T19 |
61857 |
61771 |
0 |
0 |
T20 |
153465 |
153336 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
380052849 |
0 |
0 |
T1 |
56008 |
55932 |
0 |
0 |
T2 |
392243 |
392143 |
0 |
0 |
T3 |
2207 |
2094 |
0 |
0 |
T4 |
440941 |
440874 |
0 |
0 |
T15 |
36157 |
36081 |
0 |
0 |
T16 |
84051 |
78915 |
0 |
0 |
T17 |
1824 |
1752 |
0 |
0 |
T18 |
64985 |
64828 |
0 |
0 |
T19 |
61857 |
61771 |
0 |
0 |
T20 |
153465 |
153336 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
380052849 |
0 |
0 |
T1 |
56008 |
55932 |
0 |
0 |
T2 |
392243 |
392143 |
0 |
0 |
T3 |
2207 |
2094 |
0 |
0 |
T4 |
440941 |
440874 |
0 |
0 |
T15 |
36157 |
36081 |
0 |
0 |
T16 |
84051 |
78915 |
0 |
0 |
T17 |
1824 |
1752 |
0 |
0 |
T18 |
64985 |
64828 |
0 |
0 |
T19 |
61857 |
61771 |
0 |
0 |
T20 |
153465 |
153336 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
32637600 |
0 |
0 |
T1 |
56008 |
28232 |
0 |
0 |
T2 |
392243 |
133012 |
0 |
0 |
T3 |
2207 |
24 |
0 |
0 |
T4 |
440941 |
186228 |
0 |
0 |
T15 |
36157 |
0 |
0 |
0 |
T16 |
84051 |
0 |
0 |
0 |
T17 |
1824 |
0 |
0 |
0 |
T18 |
64985 |
0 |
0 |
0 |
T19 |
61857 |
45371 |
0 |
0 |
T20 |
153465 |
46942 |
0 |
0 |
T24 |
0 |
74 |
0 |
0 |
T33 |
0 |
596320 |
0 |
0 |
T46 |
0 |
29058 |
0 |
0 |
T47 |
0 |
524 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo
| Total | Covered | Percent |
Conditions | 24 | 19 | 79.17 |
Logical | 24 | 19 | 79.17 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T39,T42,T45 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T19,T20 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T39,T40,T41 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T35,T55,T56 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
5548285 |
0 |
0 |
T1 |
56008 |
16518 |
0 |
0 |
T2 |
392243 |
41700 |
0 |
0 |
T3 |
2207 |
6 |
0 |
0 |
T4 |
440941 |
42653 |
0 |
0 |
T15 |
36157 |
0 |
0 |
0 |
T16 |
84051 |
0 |
0 |
0 |
T17 |
1824 |
0 |
0 |
0 |
T18 |
64985 |
0 |
0 |
0 |
T19 |
61857 |
16369 |
0 |
0 |
T20 |
153465 |
16570 |
0 |
0 |
T24 |
0 |
21 |
0 |
0 |
T33 |
0 |
16798 |
0 |
0 |
T46 |
0 |
16793 |
0 |
0 |
T47 |
0 |
228 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
380052849 |
0 |
0 |
T1 |
56008 |
55932 |
0 |
0 |
T2 |
392243 |
392143 |
0 |
0 |
T3 |
2207 |
2094 |
0 |
0 |
T4 |
440941 |
440874 |
0 |
0 |
T15 |
36157 |
36081 |
0 |
0 |
T16 |
84051 |
78915 |
0 |
0 |
T17 |
1824 |
1752 |
0 |
0 |
T18 |
64985 |
64828 |
0 |
0 |
T19 |
61857 |
61771 |
0 |
0 |
T20 |
153465 |
153336 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
380052849 |
0 |
0 |
T1 |
56008 |
55932 |
0 |
0 |
T2 |
392243 |
392143 |
0 |
0 |
T3 |
2207 |
2094 |
0 |
0 |
T4 |
440941 |
440874 |
0 |
0 |
T15 |
36157 |
36081 |
0 |
0 |
T16 |
84051 |
78915 |
0 |
0 |
T17 |
1824 |
1752 |
0 |
0 |
T18 |
64985 |
64828 |
0 |
0 |
T19 |
61857 |
61771 |
0 |
0 |
T20 |
153465 |
153336 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
380052849 |
0 |
0 |
T1 |
56008 |
55932 |
0 |
0 |
T2 |
392243 |
392143 |
0 |
0 |
T3 |
2207 |
2094 |
0 |
0 |
T4 |
440941 |
440874 |
0 |
0 |
T15 |
36157 |
36081 |
0 |
0 |
T16 |
84051 |
78915 |
0 |
0 |
T17 |
1824 |
1752 |
0 |
0 |
T18 |
64985 |
64828 |
0 |
0 |
T19 |
61857 |
61771 |
0 |
0 |
T20 |
153465 |
153336 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
5548285 |
0 |
0 |
T1 |
56008 |
16518 |
0 |
0 |
T2 |
392243 |
41700 |
0 |
0 |
T3 |
2207 |
6 |
0 |
0 |
T4 |
440941 |
42653 |
0 |
0 |
T15 |
36157 |
0 |
0 |
0 |
T16 |
84051 |
0 |
0 |
0 |
T17 |
1824 |
0 |
0 |
0 |
T18 |
64985 |
0 |
0 |
0 |
T19 |
61857 |
16369 |
0 |
0 |
T20 |
153465 |
16570 |
0 |
0 |
T24 |
0 |
21 |
0 |
0 |
T33 |
0 |
16798 |
0 |
0 |
T46 |
0 |
16793 |
0 |
0 |
T47 |
0 |
228 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
32637600 |
0 |
0 |
T1 |
56008 |
28232 |
0 |
0 |
T2 |
392243 |
133012 |
0 |
0 |
T3 |
2207 |
24 |
0 |
0 |
T4 |
440941 |
186228 |
0 |
0 |
T15 |
36157 |
0 |
0 |
0 |
T16 |
84051 |
0 |
0 |
0 |
T17 |
1824 |
0 |
0 |
0 |
T18 |
64985 |
0 |
0 |
0 |
T19 |
61857 |
45371 |
0 |
0 |
T20 |
153465 |
46942 |
0 |
0 |
T24 |
0 |
74 |
0 |
0 |
T33 |
0 |
596320 |
0 |
0 |
T46 |
0 |
29058 |
0 |
0 |
T47 |
0 |
524 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
380052849 |
0 |
0 |
T1 |
56008 |
55932 |
0 |
0 |
T2 |
392243 |
392143 |
0 |
0 |
T3 |
2207 |
2094 |
0 |
0 |
T4 |
440941 |
440874 |
0 |
0 |
T15 |
36157 |
36081 |
0 |
0 |
T16 |
84051 |
78915 |
0 |
0 |
T17 |
1824 |
1752 |
0 |
0 |
T18 |
64985 |
64828 |
0 |
0 |
T19 |
61857 |
61771 |
0 |
0 |
T20 |
153465 |
153336 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
380052849 |
0 |
0 |
T1 |
56008 |
55932 |
0 |
0 |
T2 |
392243 |
392143 |
0 |
0 |
T3 |
2207 |
2094 |
0 |
0 |
T4 |
440941 |
440874 |
0 |
0 |
T15 |
36157 |
36081 |
0 |
0 |
T16 |
84051 |
78915 |
0 |
0 |
T17 |
1824 |
1752 |
0 |
0 |
T18 |
64985 |
64828 |
0 |
0 |
T19 |
61857 |
61771 |
0 |
0 |
T20 |
153465 |
153336 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
380052849 |
0 |
0 |
T1 |
56008 |
55932 |
0 |
0 |
T2 |
392243 |
392143 |
0 |
0 |
T3 |
2207 |
2094 |
0 |
0 |
T4 |
440941 |
440874 |
0 |
0 |
T15 |
36157 |
36081 |
0 |
0 |
T16 |
84051 |
78915 |
0 |
0 |
T17 |
1824 |
1752 |
0 |
0 |
T18 |
64985 |
64828 |
0 |
0 |
T19 |
61857 |
61771 |
0 |
0 |
T20 |
153465 |
153336 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380926821 |
32637600 |
0 |
0 |
T1 |
56008 |
28232 |
0 |
0 |
T2 |
392243 |
133012 |
0 |
0 |
T3 |
2207 |
24 |
0 |
0 |
T4 |
440941 |
186228 |
0 |
0 |
T15 |
36157 |
0 |
0 |
0 |
T16 |
84051 |
0 |
0 |
0 |
T17 |
1824 |
0 |
0 |
0 |
T18 |
64985 |
0 |
0 |
0 |
T19 |
61857 |
45371 |
0 |
0 |
T20 |
153465 |
46942 |
0 |
0 |
T24 |
0 |
74 |
0 |
0 |
T33 |
0 |
596320 |
0 |
0 |
T46 |
0 |
29058 |
0 |
0 |
T47 |
0 |
524 |
0 |
0 |