| T1080 |
/workspace/coverage/default/10.flash_ctrl_rand_ops.1356167827 |
|
|
Jul 23 04:45:08 PM PDT 24 |
Jul 23 05:00:44 PM PDT 24 |
754731700 ps |
| T1081 |
/workspace/coverage/default/15.flash_ctrl_connect.3806624910 |
|
|
Jul 23 04:45:46 PM PDT 24 |
Jul 23 04:46:04 PM PDT 24 |
24454500 ps |
| T1082 |
/workspace/coverage/default/6.flash_ctrl_alert_test.252007040 |
|
|
Jul 23 04:44:47 PM PDT 24 |
Jul 23 04:45:04 PM PDT 24 |
77094600 ps |
| T1083 |
/workspace/coverage/default/29.flash_ctrl_alert_test.1036229905 |
|
|
Jul 23 04:46:52 PM PDT 24 |
Jul 23 04:47:14 PM PDT 24 |
33213400 ps |
| T1084 |
/workspace/coverage/default/60.flash_ctrl_connect.1714494279 |
|
|
Jul 23 04:48:02 PM PDT 24 |
Jul 23 04:48:22 PM PDT 24 |
52568100 ps |
| T1085 |
/workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.670040032 |
|
|
Jul 23 04:44:31 PM PDT 24 |
Jul 23 04:45:06 PM PDT 24 |
43784100 ps |
| T1086 |
/workspace/coverage/default/78.flash_ctrl_connect.2279843670 |
|
|
Jul 23 04:48:10 PM PDT 24 |
Jul 23 04:48:32 PM PDT 24 |
71801600 ps |
| T1087 |
/workspace/coverage/default/38.flash_ctrl_hw_sec_otp.3790122465 |
|
|
Jul 23 04:47:25 PM PDT 24 |
Jul 23 04:51:20 PM PDT 24 |
2938488000 ps |
| T1088 |
/workspace/coverage/default/7.flash_ctrl_error_prog_win.1062812328 |
|
|
Jul 23 04:44:52 PM PDT 24 |
Jul 23 04:56:34 PM PDT 24 |
2633435200 ps |
| T1089 |
/workspace/coverage/default/34.flash_ctrl_smoke.2210687637 |
|
|
Jul 23 04:47:16 PM PDT 24 |
Jul 23 04:50:30 PM PDT 24 |
84994800 ps |
| T1090 |
/workspace/coverage/default/37.flash_ctrl_sec_info_access.1545129877 |
|
|
Jul 23 04:47:25 PM PDT 24 |
Jul 23 04:48:31 PM PDT 24 |
787135900 ps |
| T1091 |
/workspace/coverage/default/0.flash_ctrl_smoke.1396249325 |
|
|
Jul 23 04:43:18 PM PDT 24 |
Jul 23 04:45:47 PM PDT 24 |
198639200 ps |
| T1092 |
/workspace/coverage/default/3.flash_ctrl_intr_wr.1248954630 |
|
|
Jul 23 04:44:24 PM PDT 24 |
Jul 23 04:45:30 PM PDT 24 |
2176357300 ps |
| T342 |
/workspace/coverage/default/28.flash_ctrl_hw_sec_otp.285222849 |
|
|
Jul 23 04:46:55 PM PDT 24 |
Jul 23 04:48:12 PM PDT 24 |
1934148500 ps |
| T1093 |
/workspace/coverage/default/39.flash_ctrl_hw_sec_otp.1044045637 |
|
|
Jul 23 04:47:31 PM PDT 24 |
Jul 23 04:49:03 PM PDT 24 |
5896165800 ps |
| T1094 |
/workspace/coverage/default/7.flash_ctrl_phy_arb.1199745590 |
|
|
Jul 23 04:44:52 PM PDT 24 |
Jul 23 04:49:40 PM PDT 24 |
1443843800 ps |
| T1095 |
/workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.752481129 |
|
|
Jul 23 04:45:18 PM PDT 24 |
Jul 23 04:45:49 PM PDT 24 |
44738200 ps |
| T1096 |
/workspace/coverage/default/42.flash_ctrl_disable.507976775 |
|
|
Jul 23 04:47:38 PM PDT 24 |
Jul 23 04:47:59 PM PDT 24 |
46028800 ps |
| T1097 |
/workspace/coverage/default/5.flash_ctrl_disable.2002055153 |
|
|
Jul 23 04:44:33 PM PDT 24 |
Jul 23 04:44:58 PM PDT 24 |
43667500 ps |
| T1098 |
/workspace/coverage/default/19.flash_ctrl_disable.2014254591 |
|
|
Jul 23 04:46:15 PM PDT 24 |
Jul 23 04:46:38 PM PDT 24 |
59204300 ps |
| T1099 |
/workspace/coverage/default/4.flash_ctrl_mid_op_rst.560219858 |
|
|
Jul 23 04:44:28 PM PDT 24 |
Jul 23 04:45:40 PM PDT 24 |
932645700 ps |
| T1100 |
/workspace/coverage/default/6.flash_ctrl_re_evict.810550306 |
|
|
Jul 23 04:44:41 PM PDT 24 |
Jul 23 04:45:20 PM PDT 24 |
68545100 ps |
| T1101 |
/workspace/coverage/default/5.flash_ctrl_rw_derr.2894127996 |
|
|
Jul 23 04:44:36 PM PDT 24 |
Jul 23 04:54:31 PM PDT 24 |
8558978800 ps |
| T1102 |
/workspace/coverage/default/13.flash_ctrl_rand_ops.2557221313 |
|
|
Jul 23 04:45:24 PM PDT 24 |
Jul 23 04:49:39 PM PDT 24 |
245012200 ps |
| T1103 |
/workspace/coverage/default/0.flash_ctrl_rd_ooo.1909093876 |
|
|
Jul 23 04:43:38 PM PDT 24 |
Jul 23 04:44:37 PM PDT 24 |
63232800 ps |
| T1104 |
/workspace/coverage/default/3.flash_ctrl_oversize_error.2441968849 |
|
|
Jul 23 04:44:25 PM PDT 24 |
Jul 23 04:47:08 PM PDT 24 |
2367377800 ps |
| T411 |
/workspace/coverage/default/25.flash_ctrl_sec_info_access.1579807589 |
|
|
Jul 23 04:46:44 PM PDT 24 |
Jul 23 04:47:49 PM PDT 24 |
481156800 ps |
| T1105 |
/workspace/coverage/default/9.flash_ctrl_rw_derr.1102630935 |
|
|
Jul 23 04:45:01 PM PDT 24 |
Jul 23 04:56:18 PM PDT 24 |
3574955900 ps |
| T1106 |
/workspace/coverage/default/33.flash_ctrl_intr_rd.1355401253 |
|
|
Jul 23 04:47:09 PM PDT 24 |
Jul 23 04:50:53 PM PDT 24 |
20098146600 ps |
| T1107 |
/workspace/coverage/default/1.flash_ctrl_connect.741717517 |
|
|
Jul 23 04:43:51 PM PDT 24 |
Jul 23 04:44:13 PM PDT 24 |
22652900 ps |
| T1108 |
/workspace/coverage/default/0.flash_ctrl_intr_wr.2508814388 |
|
|
Jul 23 04:43:31 PM PDT 24 |
Jul 23 04:44:59 PM PDT 24 |
2188661400 ps |
| T249 |
/workspace/coverage/default/1.flash_ctrl_wr_intg.2225943999 |
|
|
Jul 23 04:43:50 PM PDT 24 |
Jul 23 04:44:14 PM PDT 24 |
45162200 ps |
| T1109 |
/workspace/coverage/default/73.flash_ctrl_otp_reset.1501521713 |
|
|
Jul 23 04:48:05 PM PDT 24 |
Jul 23 04:50:23 PM PDT 24 |
42505500 ps |
| T1110 |
/workspace/coverage/default/1.flash_ctrl_intr_wr.3220663380 |
|
|
Jul 23 04:43:48 PM PDT 24 |
Jul 23 04:45:07 PM PDT 24 |
33784196000 ps |
| T1111 |
/workspace/coverage/default/0.flash_ctrl_rand_ops.3212461710 |
|
|
Jul 23 04:43:18 PM PDT 24 |
Jul 23 04:47:57 PM PDT 24 |
476803500 ps |
| T1112 |
/workspace/coverage/default/11.flash_ctrl_sec_info_access.1146252989 |
|
|
Jul 23 04:45:17 PM PDT 24 |
Jul 23 04:46:33 PM PDT 24 |
21644033300 ps |
| T1113 |
/workspace/coverage/default/30.flash_ctrl_sec_info_access.322751602 |
|
|
Jul 23 04:46:59 PM PDT 24 |
Jul 23 04:47:59 PM PDT 24 |
457900600 ps |
| T1114 |
/workspace/coverage/default/4.flash_ctrl_mp_regions.4047479039 |
|
|
Jul 23 04:44:27 PM PDT 24 |
Jul 23 04:49:23 PM PDT 24 |
19382246700 ps |
| T1115 |
/workspace/coverage/default/5.flash_ctrl_invalid_op.3003204817 |
|
|
Jul 23 04:44:35 PM PDT 24 |
Jul 23 04:45:50 PM PDT 24 |
2185297600 ps |
| T1116 |
/workspace/coverage/default/7.flash_ctrl_sec_info_access.1056573345 |
|
|
Jul 23 04:44:48 PM PDT 24 |
Jul 23 04:46:06 PM PDT 24 |
2297721700 ps |
| T1117 |
/workspace/coverage/default/34.flash_ctrl_intr_rd.2174291721 |
|
|
Jul 23 04:47:18 PM PDT 24 |
Jul 23 04:51:31 PM PDT 24 |
2353203700 ps |
| T60 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1836577738 |
|
|
Jul 23 04:39:43 PM PDT 24 |
Jul 23 04:40:16 PM PDT 24 |
213460700 ps |
| T281 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.33294773 |
|
|
Jul 23 04:39:38 PM PDT 24 |
Jul 23 04:39:53 PM PDT 24 |
15658800 ps |
| T1118 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.4204534372 |
|
|
Jul 23 04:39:05 PM PDT 24 |
Jul 23 04:39:21 PM PDT 24 |
28626900 ps |
| T1119 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.864265148 |
|
|
Jul 23 04:39:32 PM PDT 24 |
Jul 23 04:39:50 PM PDT 24 |
44580100 ps |
| T1120 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3802413293 |
|
|
Jul 23 04:39:28 PM PDT 24 |
Jul 23 04:39:44 PM PDT 24 |
47410000 ps |
| T1121 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.4264696057 |
|
|
Jul 23 04:39:27 PM PDT 24 |
Jul 23 04:39:45 PM PDT 24 |
23792500 ps |
| T282 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1404182441 |
|
|
Jul 23 04:39:57 PM PDT 24 |
Jul 23 04:40:13 PM PDT 24 |
24365500 ps |
| T61 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2767228092 |
|
|
Jul 23 04:39:32 PM PDT 24 |
Jul 23 04:39:49 PM PDT 24 |
22952100 ps |
| T283 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2058753773 |
|
|
Jul 23 04:39:40 PM PDT 24 |
Jul 23 04:39:54 PM PDT 24 |
43069700 ps |
| T1122 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3442854846 |
|
|
Jul 23 04:39:33 PM PDT 24 |
Jul 23 04:39:51 PM PDT 24 |
33951600 ps |
| T352 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1744327922 |
|
|
Jul 23 04:39:42 PM PDT 24 |
Jul 23 04:39:58 PM PDT 24 |
91349700 ps |
| T62 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.78995929 |
|
|
Jul 23 04:39:09 PM PDT 24 |
Jul 23 04:39:42 PM PDT 24 |
228610800 ps |
| T102 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1413532245 |
|
|
Jul 23 04:39:35 PM PDT 24 |
Jul 23 04:47:18 PM PDT 24 |
872820600 ps |
| T103 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2291458957 |
|
|
Jul 23 04:39:03 PM PDT 24 |
Jul 23 04:39:25 PM PDT 24 |
41169200 ps |
| T350 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3201527177 |
|
|
Jul 23 04:39:57 PM PDT 24 |
Jul 23 04:40:13 PM PDT 24 |
15301400 ps |
| T353 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1102689992 |
|
|
Jul 23 04:39:40 PM PDT 24 |
Jul 23 04:39:54 PM PDT 24 |
44935400 ps |
| T104 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1330558216 |
|
|
Jul 23 04:39:45 PM PDT 24 |
Jul 23 04:52:32 PM PDT 24 |
705670800 ps |
| T220 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2168309552 |
|
|
Jul 23 04:39:35 PM PDT 24 |
Jul 23 04:39:56 PM PDT 24 |
215343500 ps |
| T221 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3412781273 |
|
|
Jul 23 04:39:17 PM PDT 24 |
Jul 23 04:39:36 PM PDT 24 |
50925700 ps |
| T1123 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3433090479 |
|
|
Jul 23 04:39:35 PM PDT 24 |
Jul 23 04:39:53 PM PDT 24 |
31808400 ps |
| T222 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.51153039 |
|
|
Jul 23 04:39:47 PM PDT 24 |
Jul 23 04:40:08 PM PDT 24 |
210300600 ps |
| T253 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1644698971 |
|
|
Jul 23 04:39:25 PM PDT 24 |
Jul 23 04:39:43 PM PDT 24 |
48714100 ps |
| T223 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.4224862755 |
|
|
Jul 23 04:39:02 PM PDT 24 |
Jul 23 04:39:20 PM PDT 24 |
57566300 ps |
| T254 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2613600627 |
|
|
Jul 23 04:39:46 PM PDT 24 |
Jul 23 04:40:07 PM PDT 24 |
341917900 ps |
| T255 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2864953868 |
|
|
Jul 23 04:39:43 PM PDT 24 |
Jul 23 04:54:49 PM PDT 24 |
344585500 ps |
| T321 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2433870539 |
|
|
Jul 23 04:39:17 PM PDT 24 |
Jul 23 04:39:36 PM PDT 24 |
399295400 ps |
| T256 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3576784001 |
|
|
Jul 23 04:39:21 PM PDT 24 |
Jul 23 04:39:43 PM PDT 24 |
467995100 ps |
| T351 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.194405241 |
|
|
Jul 23 04:39:06 PM PDT 24 |
Jul 23 04:39:21 PM PDT 24 |
26162700 ps |
| T257 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3686993228 |
|
|
Jul 23 04:39:29 PM PDT 24 |
Jul 23 04:39:47 PM PDT 24 |
68643300 ps |
| T1124 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2146534466 |
|
|
Jul 23 04:39:32 PM PDT 24 |
Jul 23 04:39:51 PM PDT 24 |
24099900 ps |
| T1125 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2737463678 |
|
|
Jul 23 04:39:43 PM PDT 24 |
Jul 23 04:40:22 PM PDT 24 |
167622800 ps |
| T258 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2915239599 |
|
|
Jul 23 04:39:17 PM PDT 24 |
Jul 23 04:39:32 PM PDT 24 |
84341500 ps |
| T279 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1490619858 |
|
|
Jul 23 04:39:29 PM PDT 24 |
Jul 23 04:39:48 PM PDT 24 |
79829700 ps |
| T369 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2529517892 |
|
|
Jul 23 04:39:59 PM PDT 24 |
Jul 23 04:40:16 PM PDT 24 |
114955600 ps |
| T354 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2582145232 |
|
|
Jul 23 04:39:57 PM PDT 24 |
Jul 23 04:40:13 PM PDT 24 |
26465700 ps |
| T322 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2192002558 |
|
|
Jul 23 04:39:05 PM PDT 24 |
Jul 23 04:39:46 PM PDT 24 |
99865300 ps |
| T1126 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3428844997 |
|
|
Jul 23 04:39:42 PM PDT 24 |
Jul 23 04:39:57 PM PDT 24 |
32595900 ps |
| T371 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2455259359 |
|
|
Jul 23 04:39:57 PM PDT 24 |
Jul 23 04:40:13 PM PDT 24 |
18812000 ps |
| T297 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3070561644 |
|
|
Jul 23 04:39:33 PM PDT 24 |
Jul 23 04:54:31 PM PDT 24 |
344946800 ps |
| T1127 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.107369704 |
|
|
Jul 23 04:39:29 PM PDT 24 |
Jul 23 04:39:48 PM PDT 24 |
19982600 ps |
| T275 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3436804500 |
|
|
Jul 23 04:39:35 PM PDT 24 |
Jul 23 04:39:55 PM PDT 24 |
117095400 ps |
| T1128 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2133580296 |
|
|
Jul 23 04:39:19 PM PDT 24 |
Jul 23 04:39:34 PM PDT 24 |
23555800 ps |
| T286 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.4172603582 |
|
|
Jul 23 04:39:04 PM PDT 24 |
Jul 23 04:39:27 PM PDT 24 |
180571200 ps |
| T1129 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.300874827 |
|
|
Jul 23 04:39:36 PM PDT 24 |
Jul 23 04:39:55 PM PDT 24 |
187840100 ps |
| T277 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.811115617 |
|
|
Jul 23 04:39:32 PM PDT 24 |
Jul 23 04:39:51 PM PDT 24 |
144940900 ps |
| T1130 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3532258424 |
|
|
Jul 23 04:39:02 PM PDT 24 |
Jul 23 04:39:20 PM PDT 24 |
17582200 ps |
| T1131 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.4271446695 |
|
|
Jul 23 04:39:28 PM PDT 24 |
Jul 23 04:39:47 PM PDT 24 |
266157700 ps |
| T323 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1795845931 |
|
|
Jul 23 04:39:01 PM PDT 24 |
Jul 23 04:39:35 PM PDT 24 |
460052800 ps |
| T372 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1483518504 |
|
|
Jul 23 04:39:18 PM PDT 24 |
Jul 23 04:39:34 PM PDT 24 |
17004100 ps |
| T1132 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2223909521 |
|
|
Jul 23 04:39:43 PM PDT 24 |
Jul 23 04:40:19 PM PDT 24 |
626638700 ps |
| T1133 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3992105747 |
|
|
Jul 23 04:39:19 PM PDT 24 |
Jul 23 04:39:38 PM PDT 24 |
27178200 ps |
| T280 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3873869244 |
|
|
Jul 23 04:39:35 PM PDT 24 |
Jul 23 04:39:56 PM PDT 24 |
221086600 ps |
| T1134 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2339058235 |
|
|
Jul 23 04:39:47 PM PDT 24 |
Jul 23 04:40:06 PM PDT 24 |
25082400 ps |
| T324 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2749132727 |
|
|
Jul 23 04:39:45 PM PDT 24 |
Jul 23 04:40:04 PM PDT 24 |
149434200 ps |
| T1135 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.313609380 |
|
|
Jul 23 04:39:10 PM PDT 24 |
Jul 23 04:39:49 PM PDT 24 |
332944000 ps |
| T1136 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2652524746 |
|
|
Jul 23 04:39:02 PM PDT 24 |
Jul 23 04:39:20 PM PDT 24 |
41837500 ps |
| T1137 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.752145225 |
|
|
Jul 23 04:39:55 PM PDT 24 |
Jul 23 04:40:10 PM PDT 24 |
55573000 ps |
| T1138 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3320629245 |
|
|
Jul 23 04:39:42 PM PDT 24 |
Jul 23 04:40:00 PM PDT 24 |
43203900 ps |
| T325 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.340779274 |
|
|
Jul 23 04:39:57 PM PDT 24 |
Jul 23 04:40:19 PM PDT 24 |
572649300 ps |
| T373 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.592582037 |
|
|
Jul 23 04:39:59 PM PDT 24 |
Jul 23 04:40:16 PM PDT 24 |
15583500 ps |
| T1139 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.891142005 |
|
|
Jul 23 04:39:19 PM PDT 24 |
Jul 23 04:39:36 PM PDT 24 |
21044200 ps |
| T276 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3951805901 |
|
|
Jul 23 04:39:01 PM PDT 24 |
Jul 23 04:39:23 PM PDT 24 |
94963600 ps |
| T1140 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3334435551 |
|
|
Jul 23 04:39:02 PM PDT 24 |
Jul 23 04:39:20 PM PDT 24 |
20519900 ps |
| T1141 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2501747400 |
|
|
Jul 23 04:39:56 PM PDT 24 |
Jul 23 04:40:11 PM PDT 24 |
23536000 ps |
| T1142 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.182810366 |
|
|
Jul 23 04:39:44 PM PDT 24 |
Jul 23 04:40:00 PM PDT 24 |
25565400 ps |
| T289 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2613156534 |
|
|
Jul 23 04:39:44 PM PDT 24 |
Jul 23 04:40:06 PM PDT 24 |
91003400 ps |
| T1143 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1981006701 |
|
|
Jul 23 04:39:10 PM PDT 24 |
Jul 23 04:39:45 PM PDT 24 |
132447300 ps |
| T1144 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.593621707 |
|
|
Jul 23 04:39:17 PM PDT 24 |
Jul 23 04:39:34 PM PDT 24 |
37319100 ps |
| T260 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1934411768 |
|
|
Jul 23 04:39:05 PM PDT 24 |
Jul 23 04:39:20 PM PDT 24 |
25528100 ps |
| T1145 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.514593235 |
|
|
Jul 23 04:39:56 PM PDT 24 |
Jul 23 04:40:09 PM PDT 24 |
22672800 ps |
| T1146 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3605653001 |
|
|
Jul 23 04:39:58 PM PDT 24 |
Jul 23 04:40:15 PM PDT 24 |
29531400 ps |
| T1147 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2433762000 |
|
|
Jul 23 04:39:58 PM PDT 24 |
Jul 23 04:40:14 PM PDT 24 |
32049900 ps |
| T1148 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3933781160 |
|
|
Jul 23 04:39:32 PM PDT 24 |
Jul 23 04:39:54 PM PDT 24 |
87983200 ps |
| T1149 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.4035590249 |
|
|
Jul 23 04:39:57 PM PDT 24 |
Jul 23 04:40:14 PM PDT 24 |
82145400 ps |
| T1150 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2833359160 |
|
|
Jul 23 04:39:17 PM PDT 24 |
Jul 23 04:39:32 PM PDT 24 |
42399100 ps |
| T1151 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.599643305 |
|
|
Jul 23 04:40:03 PM PDT 24 |
Jul 23 04:40:18 PM PDT 24 |
15369800 ps |
| T1152 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1121409446 |
|
|
Jul 23 04:39:41 PM PDT 24 |
Jul 23 04:39:57 PM PDT 24 |
20030000 ps |
| T1153 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1401349402 |
|
|
Jul 23 04:39:58 PM PDT 24 |
Jul 23 04:40:15 PM PDT 24 |
27125100 ps |
| T1154 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3194647156 |
|
|
Jul 23 04:39:01 PM PDT 24 |
Jul 23 04:40:07 PM PDT 24 |
1320622500 ps |
| T290 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3567195526 |
|
|
Jul 23 04:39:33 PM PDT 24 |
Jul 23 04:52:23 PM PDT 24 |
16087644000 ps |
| T326 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.29968227 |
|
|
Jul 23 04:39:32 PM PDT 24 |
Jul 23 04:39:54 PM PDT 24 |
438267200 ps |
| T1155 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2204061177 |
|
|
Jul 23 04:39:50 PM PDT 24 |
Jul 23 04:40:05 PM PDT 24 |
16136800 ps |
| T1156 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3415091137 |
|
|
Jul 23 04:39:36 PM PDT 24 |
Jul 23 04:39:54 PM PDT 24 |
87467100 ps |
| T295 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1206017878 |
|
|
Jul 23 04:39:16 PM PDT 24 |
Jul 23 04:46:59 PM PDT 24 |
897532300 ps |
| T1157 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2198704090 |
|
|
Jul 23 04:40:00 PM PDT 24 |
Jul 23 04:40:16 PM PDT 24 |
96065100 ps |
| T278 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.382675842 |
|
|
Jul 23 04:39:00 PM PDT 24 |
Jul 23 04:45:30 PM PDT 24 |
1457914600 ps |
| T1158 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3924160295 |
|
|
Jul 23 04:39:31 PM PDT 24 |
Jul 23 04:39:48 PM PDT 24 |
214008900 ps |
| T1159 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2459150107 |
|
|
Jul 23 04:39:42 PM PDT 24 |
Jul 23 04:39:58 PM PDT 24 |
30504700 ps |
| T1160 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1795997400 |
|
|
Jul 23 04:39:20 PM PDT 24 |
Jul 23 04:40:07 PM PDT 24 |
27314900 ps |
| T1161 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2963092460 |
|
|
Jul 23 04:39:28 PM PDT 24 |
Jul 23 04:39:44 PM PDT 24 |
53455500 ps |
| T1162 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3727577323 |
|
|
Jul 23 04:39:59 PM PDT 24 |
Jul 23 04:40:16 PM PDT 24 |
52814600 ps |
| T1163 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1728579810 |
|
|
Jul 23 04:39:52 PM PDT 24 |
Jul 23 04:40:07 PM PDT 24 |
41336800 ps |
| T1164 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3623127710 |
|
|
Jul 23 04:39:57 PM PDT 24 |
Jul 23 04:40:17 PM PDT 24 |
67764700 ps |
| T284 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3458285636 |
|
|
Jul 23 04:39:35 PM PDT 24 |
Jul 23 04:39:53 PM PDT 24 |
131027900 ps |
| T261 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3652241480 |
|
|
Jul 23 04:39:08 PM PDT 24 |
Jul 23 04:39:23 PM PDT 24 |
78599900 ps |
| T1165 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3967341380 |
|
|
Jul 23 04:40:01 PM PDT 24 |
Jul 23 04:40:19 PM PDT 24 |
13851900 ps |
| T1166 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.323646791 |
|
|
Jul 23 04:39:28 PM PDT 24 |
Jul 23 04:40:10 PM PDT 24 |
1331792600 ps |
| T1167 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1008456160 |
|
|
Jul 23 04:39:32 PM PDT 24 |
Jul 23 04:40:10 PM PDT 24 |
329943400 ps |
| T1168 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1689956478 |
|
|
Jul 23 04:39:45 PM PDT 24 |
Jul 23 04:40:06 PM PDT 24 |
178484400 ps |
| T1169 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1446493724 |
|
|
Jul 23 04:39:46 PM PDT 24 |
Jul 23 04:40:04 PM PDT 24 |
20846800 ps |
| T1170 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4232271256 |
|
|
Jul 23 04:39:46 PM PDT 24 |
Jul 23 04:40:04 PM PDT 24 |
72639600 ps |
| T379 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.892750672 |
|
|
Jul 23 04:39:27 PM PDT 24 |
Jul 23 04:47:07 PM PDT 24 |
569734300 ps |
| T292 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3200957170 |
|
|
Jul 23 04:39:48 PM PDT 24 |
Jul 23 04:54:47 PM PDT 24 |
1580009000 ps |
| T1171 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1797223416 |
|
|
Jul 23 04:39:58 PM PDT 24 |
Jul 23 04:40:14 PM PDT 24 |
46534000 ps |
| T1172 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1229979684 |
|
|
Jul 23 04:39:57 PM PDT 24 |
Jul 23 04:40:14 PM PDT 24 |
28229200 ps |
| T1173 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.803869442 |
|
|
Jul 23 04:39:10 PM PDT 24 |
Jul 23 04:39:57 PM PDT 24 |
46034900 ps |
| T1174 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2447723739 |
|
|
Jul 23 04:39:23 PM PDT 24 |
Jul 23 04:39:40 PM PDT 24 |
42715900 ps |
| T1175 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2623995874 |
|
|
Jul 23 04:40:03 PM PDT 24 |
Jul 23 04:40:20 PM PDT 24 |
10988900 ps |
| T327 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.4026333110 |
|
|
Jul 23 04:39:57 PM PDT 24 |
Jul 23 04:40:17 PM PDT 24 |
210410200 ps |
| T1176 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.872677838 |
|
|
Jul 23 04:39:59 PM PDT 24 |
Jul 23 04:40:16 PM PDT 24 |
35549200 ps |
| T1177 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1889074756 |
|
|
Jul 23 04:39:54 PM PDT 24 |
Jul 23 04:40:11 PM PDT 24 |
29117800 ps |
| T288 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1747909489 |
|
|
Jul 23 04:39:17 PM PDT 24 |
Jul 23 04:39:37 PM PDT 24 |
215476700 ps |
| T1178 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.473356829 |
|
|
Jul 23 04:39:25 PM PDT 24 |
Jul 23 04:39:40 PM PDT 24 |
16123500 ps |
| T1179 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1449807039 |
|
|
Jul 23 04:39:06 PM PDT 24 |
Jul 23 04:39:23 PM PDT 24 |
56129900 ps |
| T1180 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2141048478 |
|
|
Jul 23 04:39:45 PM PDT 24 |
Jul 23 04:40:01 PM PDT 24 |
24152300 ps |
| T1181 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3585644801 |
|
|
Jul 23 04:39:58 PM PDT 24 |
Jul 23 04:40:14 PM PDT 24 |
15182000 ps |
| T1182 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2394863605 |
|
|
Jul 23 04:39:44 PM PDT 24 |
Jul 23 04:40:21 PM PDT 24 |
300737800 ps |
| T1183 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1855149264 |
|
|
Jul 23 04:39:41 PM PDT 24 |
Jul 23 04:40:02 PM PDT 24 |
147079900 ps |
| T1184 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1720938714 |
|
|
Jul 23 04:39:50 PM PDT 24 |
Jul 23 04:40:04 PM PDT 24 |
21152800 ps |
| T1185 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1169198849 |
|
|
Jul 23 04:39:39 PM PDT 24 |
Jul 23 04:39:57 PM PDT 24 |
89411900 ps |
| T1186 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3585007225 |
|
|
Jul 23 04:39:58 PM PDT 24 |
Jul 23 04:40:15 PM PDT 24 |
20545800 ps |
| T1187 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1312620130 |
|
|
Jul 23 04:39:02 PM PDT 24 |
Jul 23 04:39:18 PM PDT 24 |
43780500 ps |
| T1188 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1026463814 |
|
|
Jul 23 04:39:23 PM PDT 24 |
Jul 23 04:40:03 PM PDT 24 |
659236900 ps |
| T1189 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.605573523 |
|
|
Jul 23 04:39:32 PM PDT 24 |
Jul 23 04:39:53 PM PDT 24 |
312915100 ps |
| T1190 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.619210667 |
|
|
Jul 23 04:39:42 PM PDT 24 |
Jul 23 04:40:21 PM PDT 24 |
1473950400 ps |
| T328 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3744604855 |
|
|
Jul 23 04:39:18 PM PDT 24 |
Jul 23 04:39:37 PM PDT 24 |
463581600 ps |
| T1191 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.818359867 |
|
|
Jul 23 04:39:42 PM PDT 24 |
Jul 23 04:40:00 PM PDT 24 |
134170400 ps |
| T1192 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3009889141 |
|
|
Jul 23 04:39:42 PM PDT 24 |
Jul 23 04:40:03 PM PDT 24 |
119417300 ps |
| T375 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3951378562 |
|
|
Jul 23 04:39:45 PM PDT 24 |
Jul 23 04:54:50 PM PDT 24 |
813396000 ps |
| T1193 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.4027293480 |
|
|
Jul 23 04:39:47 PM PDT 24 |
Jul 23 04:40:06 PM PDT 24 |
47005700 ps |
| T1194 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3118082290 |
|
|
Jul 23 04:39:59 PM PDT 24 |
Jul 23 04:40:16 PM PDT 24 |
14770500 ps |
| T376 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3463455337 |
|
|
Jul 23 04:39:38 PM PDT 24 |
Jul 23 04:47:19 PM PDT 24 |
847371800 ps |
| T1195 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.752687457 |
|
|
Jul 23 04:39:18 PM PDT 24 |
Jul 23 04:39:36 PM PDT 24 |
20636200 ps |
| T1196 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3909163805 |
|
|
Jul 23 04:39:44 PM PDT 24 |
Jul 23 04:40:04 PM PDT 24 |
253440100 ps |
| T382 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.197332144 |
|
|
Jul 23 04:39:02 PM PDT 24 |
Jul 23 04:46:47 PM PDT 24 |
666256600 ps |
| T383 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.326887027 |
|
|
Jul 23 04:39:43 PM PDT 24 |
Jul 23 04:46:19 PM PDT 24 |
1375435500 ps |
| T1197 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.4110461208 |
|
|
Jul 23 04:39:31 PM PDT 24 |
Jul 23 04:40:09 PM PDT 24 |
624783700 ps |
| T1198 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.4225990044 |
|
|
Jul 23 04:39:58 PM PDT 24 |
Jul 23 04:40:15 PM PDT 24 |
25494400 ps |
| T1199 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.4227614 |
|
|
Jul 23 04:39:56 PM PDT 24 |
Jul 23 04:40:11 PM PDT 24 |
51100400 ps |
| T1200 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1757137261 |
|
|
Jul 23 04:39:43 PM PDT 24 |
Jul 23 04:40:00 PM PDT 24 |
141691000 ps |
| T329 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3401341650 |
|
|
Jul 23 04:39:05 PM PDT 24 |
Jul 23 04:39:24 PM PDT 24 |
258048900 ps |
| T384 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3387497337 |
|
|
Jul 23 04:39:42 PM PDT 24 |
Jul 23 04:54:51 PM PDT 24 |
400878500 ps |
| T1201 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3540417456 |
|
|
Jul 23 04:39:28 PM PDT 24 |
Jul 23 04:40:05 PM PDT 24 |
214622500 ps |
| T1202 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1569912350 |
|
|
Jul 23 04:39:46 PM PDT 24 |
Jul 23 04:40:05 PM PDT 24 |
148358200 ps |
| T1203 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3323402799 |
|
|
Jul 23 04:39:31 PM PDT 24 |
Jul 23 04:39:50 PM PDT 24 |
125812300 ps |
| T291 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.239330744 |
|
|
Jul 23 04:39:06 PM PDT 24 |
Jul 23 04:39:27 PM PDT 24 |
69896200 ps |
| T285 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2190498673 |
|
|
Jul 23 04:39:33 PM PDT 24 |
Jul 23 04:39:54 PM PDT 24 |
89783600 ps |
| T1204 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3704412225 |
|
|
Jul 23 04:39:41 PM PDT 24 |
Jul 23 04:39:59 PM PDT 24 |
58725200 ps |
| T293 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.279836500 |
|
|
Jul 23 04:39:42 PM PDT 24 |
Jul 23 04:40:04 PM PDT 24 |
58956700 ps |
| T1205 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1973837874 |
|
|
Jul 23 04:39:58 PM PDT 24 |
Jul 23 04:40:15 PM PDT 24 |
29404500 ps |
| T1206 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2119594777 |
|
|
Jul 23 04:39:03 PM PDT 24 |
Jul 23 04:39:21 PM PDT 24 |
14240700 ps |
| T1207 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3887634485 |
|
|
Jul 23 04:39:48 PM PDT 24 |
Jul 23 04:40:05 PM PDT 24 |
38343400 ps |
| T1208 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1201778142 |
|
|
Jul 23 04:39:05 PM PDT 24 |
Jul 23 04:39:21 PM PDT 24 |
56156700 ps |
| T1209 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3223260235 |
|
|
Jul 23 04:39:02 PM PDT 24 |
Jul 23 04:39:19 PM PDT 24 |
30473000 ps |
| T262 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3417528102 |
|
|
Jul 23 04:39:05 PM PDT 24 |
Jul 23 04:39:20 PM PDT 24 |
15946000 ps |
| T1210 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2424441799 |
|
|
Jul 23 04:39:56 PM PDT 24 |
Jul 23 04:40:12 PM PDT 24 |
27815700 ps |
| T1211 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.267099717 |
|
|
Jul 23 04:39:29 PM PDT 24 |
Jul 23 04:39:46 PM PDT 24 |
11282700 ps |
| T1212 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3607925219 |
|
|
Jul 23 04:39:46 PM PDT 24 |
Jul 23 04:40:04 PM PDT 24 |
24355700 ps |
| T1213 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1880596190 |
|
|
Jul 23 04:39:31 PM PDT 24 |
Jul 23 04:47:09 PM PDT 24 |
648304900 ps |
| T1214 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2374067357 |
|
|
Jul 23 04:39:19 PM PDT 24 |
Jul 23 04:40:53 PM PDT 24 |
11886946200 ps |
| T1215 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2326081425 |
|
|
Jul 23 04:39:57 PM PDT 24 |
Jul 23 04:40:14 PM PDT 24 |
18726200 ps |
| T1216 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3380207749 |
|
|
Jul 23 04:39:00 PM PDT 24 |
Jul 23 04:39:32 PM PDT 24 |
30500600 ps |
| T287 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1129706475 |
|
|
Jul 23 04:39:43 PM PDT 24 |
Jul 23 04:40:04 PM PDT 24 |
191685500 ps |
| T298 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3559139367 |
|
|
Jul 23 04:39:28 PM PDT 24 |
Jul 23 04:47:07 PM PDT 24 |
366241500 ps |
| T1217 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3447138224 |
|
|
Jul 23 04:39:44 PM PDT 24 |
Jul 23 04:40:01 PM PDT 24 |
24424700 ps |
| T1218 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2042009538 |
|
|
Jul 23 04:39:41 PM PDT 24 |
Jul 23 04:39:55 PM PDT 24 |
12782000 ps |
| T296 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1404017156 |
|
|
Jul 23 04:39:45 PM PDT 24 |
Jul 23 04:40:07 PM PDT 24 |
348127600 ps |
| T380 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.756937545 |
|
|
Jul 23 04:39:43 PM PDT 24 |
Jul 23 04:47:22 PM PDT 24 |
1686296800 ps |
| T1219 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2813869523 |
|
|
Jul 23 04:39:31 PM PDT 24 |
Jul 23 04:39:50 PM PDT 24 |
366691200 ps |
| T1220 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1132127411 |
|
|
Jul 23 04:39:30 PM PDT 24 |
Jul 23 04:39:47 PM PDT 24 |
38193000 ps |
| T1221 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1923449495 |
|
|
Jul 23 04:39:43 PM PDT 24 |
Jul 23 04:40:02 PM PDT 24 |
41215100 ps |
| T259 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3051421918 |
|
|
Jul 23 04:39:17 PM PDT 24 |
Jul 23 04:39:32 PM PDT 24 |
48410800 ps |
| T1222 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3410542483 |
|
|
Jul 23 04:39:30 PM PDT 24 |
Jul 23 04:39:46 PM PDT 24 |
26499900 ps |
| T378 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1533755171 |
|
|
Jul 23 04:39:06 PM PDT 24 |
Jul 23 04:54:06 PM PDT 24 |
1273247700 ps |
| T1223 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.210365058 |
|
|
Jul 23 04:39:43 PM PDT 24 |
Jul 23 04:40:01 PM PDT 24 |
14866100 ps |
| T1224 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3287319268 |
|
|
Jul 23 04:39:09 PM PDT 24 |
Jul 23 04:39:24 PM PDT 24 |
16035000 ps |
| T1225 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1286953365 |
|
|
Jul 23 04:39:36 PM PDT 24 |
Jul 23 04:39:52 PM PDT 24 |
57737900 ps |
| T1226 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2661251184 |
|
|
Jul 23 04:39:03 PM PDT 24 |
Jul 23 04:39:40 PM PDT 24 |
622028500 ps |
| T1227 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.271483429 |
|
|
Jul 23 04:39:17 PM PDT 24 |
Jul 23 04:39:49 PM PDT 24 |
629522100 ps |
| T1228 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2668116570 |
|
|
Jul 23 04:39:35 PM PDT 24 |
Jul 23 04:39:56 PM PDT 24 |
64176900 ps |
| T294 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2951609055 |
|
|
Jul 23 04:39:07 PM PDT 24 |
Jul 23 04:39:28 PM PDT 24 |
234577500 ps |
| T330 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2809233840 |
|
|
Jul 23 04:39:02 PM PDT 24 |
Jul 23 04:40:14 PM PDT 24 |
7102536500 ps |
| T1229 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1004917488 |
|
|
Jul 23 04:39:56 PM PDT 24 |
Jul 23 04:40:12 PM PDT 24 |
17326300 ps |
| T1230 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1649946966 |
|
|
Jul 23 04:39:31 PM PDT 24 |
Jul 23 04:39:47 PM PDT 24 |
13235000 ps |
| T1231 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3061636024 |
|
|
Jul 23 04:39:46 PM PDT 24 |
Jul 23 04:40:03 PM PDT 24 |
185798600 ps |
| T1232 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3456610512 |
|
|
Jul 23 04:39:58 PM PDT 24 |
Jul 23 04:40:14 PM PDT 24 |
55280100 ps |
| T377 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.4097478926 |
|
|
Jul 23 04:39:18 PM PDT 24 |
Jul 23 04:46:59 PM PDT 24 |
343097800 ps |
| T331 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.569779025 |
|
|
Jul 23 04:39:44 PM PDT 24 |
Jul 23 04:40:08 PM PDT 24 |
827924300 ps |
| T332 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1294381153 |
|
|
Jul 23 04:39:21 PM PDT 24 |
Jul 23 04:39:53 PM PDT 24 |
441100500 ps |
| T1233 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2119356421 |
|
|
Jul 23 04:39:25 PM PDT 24 |
Jul 23 04:39:40 PM PDT 24 |
18267500 ps |
| T1234 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.816809175 |
|
|
Jul 23 04:39:37 PM PDT 24 |
Jul 23 04:39:51 PM PDT 24 |
13426900 ps |
| T1235 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.284799917 |
|
|
Jul 23 04:39:30 PM PDT 24 |
Jul 23 04:39:45 PM PDT 24 |
54552500 ps |
| T1236 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2218596337 |
|
|
Jul 23 04:39:31 PM PDT 24 |
Jul 23 04:39:47 PM PDT 24 |
43545000 ps |
| T1237 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.260007544 |
|
|
Jul 23 04:39:43 PM PDT 24 |
Jul 23 04:40:01 PM PDT 24 |
14737200 ps |
| T1238 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1459314739 |
|
|
Jul 23 04:39:31 PM PDT 24 |
Jul 23 04:39:50 PM PDT 24 |
30566300 ps |
| T1239 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1619343114 |
|
|
Jul 23 04:39:04 PM PDT 24 |
Jul 23 04:39:21 PM PDT 24 |
104750700 ps |
| T1240 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.313626566 |
|
|
Jul 23 04:39:46 PM PDT 24 |
Jul 23 04:40:01 PM PDT 24 |
13143400 ps |
| T381 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2350286031 |
|
|
Jul 23 04:39:28 PM PDT 24 |
Jul 23 04:54:37 PM PDT 24 |
2939699200 ps |
| T1241 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.4160279242 |
|
|
Jul 23 04:39:57 PM PDT 24 |
Jul 23 04:40:12 PM PDT 24 |
57540100 ps |
| T1242 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2770129458 |
|
|
Jul 23 04:39:42 PM PDT 24 |
Jul 23 04:40:00 PM PDT 24 |
331787200 ps |
| T1243 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3992902493 |
|
|
Jul 23 04:39:44 PM PDT 24 |
Jul 23 04:40:02 PM PDT 24 |
46592700 ps |
| T374 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2756083325 |
|
|
Jul 23 04:39:43 PM PDT 24 |
Jul 23 04:40:05 PM PDT 24 |
909952000 ps |
| T1244 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.4101392776 |
|
|
Jul 23 04:39:42 PM PDT 24 |
Jul 23 04:39:59 PM PDT 24 |
18614400 ps |
| T1245 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3929288825 |
|
|
Jul 23 04:39:33 PM PDT 24 |
Jul 23 04:40:10 PM PDT 24 |
260704300 ps |
| T1246 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2379355786 |
|
|
Jul 23 04:39:18 PM PDT 24 |
Jul 23 04:40:06 PM PDT 24 |
159398700 ps |
| T1247 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3204849044 |
|
|
Jul 23 04:39:10 PM PDT 24 |
Jul 23 04:39:27 PM PDT 24 |
56018800 ps |
| T1248 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.927320413 |
|
|
Jul 23 04:39:42 PM PDT 24 |
Jul 23 04:39:58 PM PDT 24 |
18448500 ps |
| T1249 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2431548822 |
|
|
Jul 23 04:39:02 PM PDT 24 |
Jul 23 04:39:40 PM PDT 24 |
415252600 ps |
| T1250 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.499316052 |
|
|
Jul 23 04:39:29 PM PDT 24 |
Jul 23 04:39:47 PM PDT 24 |
53025200 ps |