Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.10	95.71	94.08	98.31	91.16	98.19	96.99	98.24

Total test records in report: 1256

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1251	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3281643283			Jul 23 04:39:42 PM PDT 24	Jul 23 04:40:01 PM PDT 24	465880100 ps
T1252	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2373056885			Jul 23 04:39:01 PM PDT 24	Jul 23 04:39:17 PM PDT 24	14873800 ps
T1253	/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3500932436			Jul 23 04:39:30 PM PDT 24	Jul 23 04:39:47 PM PDT 24	36732900 ps
T1254	/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2117348890			Jul 23 04:40:00 PM PDT 24	Jul 23 04:40:16 PM PDT 24	16341500 ps
T1255	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2757498417			Jul 23 04:39:10 PM PDT 24	Jul 23 04:39:46 PM PDT 24	2001580900 ps
T1256	/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1082964428			Jul 23 04:39:03 PM PDT 24	Jul 23 04:39:19 PM PDT 24	29427500 ps

Test location	/workspace/coverage/default/7.flash_ctrl_rw_serr.2310583482
Short name	T4
Test name
Test status
Simulation time	22047111600 ps
CPU time	679.13 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 04:56:09 PM PDT 24
Peak memory	320832 kb
Host	smart-f0ddba0e-f79f-41fc-a580-aa7db80fcc2e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310583482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_s err.2310583482
Directory	/workspace/7.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1413532245
Short name	T102
Test name
Test status
Simulation time	872820600 ps
CPU time	462.3 seconds
Started	Jul 23 04:39:35 PM PDT 24
Finished	Jul 23 04:47:18 PM PDT 24
Peak memory	264508 kb
Host	smart-21b57df9-4ad0-4f58-9273-5d7a525add35
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413532245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl _tl_intg_err.1413532245
Directory	/workspace/8.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mid_op_rst.2118993143
Short name	T18
Test name
Test status
Simulation time	818841800 ps
CPU time	74.62 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 04:45:10 PM PDT 24
Peak memory	260820 kb
Host	smart-5210b3ef-b0a6-4cf6-b4e4-8391d4678a8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2118993143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.2118993143
Directory	/workspace/1.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_cm.1358438965
Short name	T13
Test name
Test status
Simulation time	4137793500 ps
CPU time	4710.15 seconds
Started	Jul 23 04:44:26 PM PDT 24
Finished	Jul 23 06:03:01 PM PDT 24
Peak memory	283356 kb
Host	smart-ce04b770-483f-4355-8fe2-662a23db5ffc
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358438965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.1358438965
Directory	/workspace/3.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/22.flash_ctrl_hw_sec_otp.1529096069
Short name	T16
Test name
Test status
Simulation time	2471122000 ps
CPU time	80.61 seconds
Started	Jul 23 04:46:35 PM PDT 24
Finished	Jul 23 04:47:58 PM PDT 24
Peak memory	260912 kb
Host	smart-1cdbc235-5a97-4673-b7f2-43c47f74155a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529096069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_ hw_sec_otp.1529096069
Directory	/workspace/22.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mp_regions.3509603577
Short name	T64
Test name
Test status
Simulation time	32151846800 ps
CPU time	209.54 seconds
Started	Jul 23 04:44:00 PM PDT 24
Finished	Jul 23 04:47:33 PM PDT 24
Peak memory	274304 kb
Host	smart-286c27af-56dd-4519-a04d-9df17567d9a5
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509603577 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.3509603577
Directory	/workspace/2.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_rma_reset.1656606770
Short name	T112
Test name
Test status
Simulation time	40119632700 ps
CPU time	810.74 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 04:58:21 PM PDT 24
Peak memory	265100 kb
Host	smart-c5c7e3a1-988c-48c0-9ad2-13937aaf475a
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656606770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 8.flash_ctrl_hw_rma_reset.1656606770
Directory	/workspace/8.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd.1641148241
Short name	T20
Test name
Test status
Simulation time	3069349600 ps
CPU time	217.3 seconds
Started	Jul 23 04:46:45 PM PDT 24
Finished	Jul 23 04:50:28 PM PDT 24
Peak memory	284848 kb
Host	smart-ba25af0b-53f7-43da-8ce8-d25dcd58603c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641148241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla sh_ctrl_intr_rd.1641148241
Directory	/workspace/26.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_erase_suspend.2208241695
Short name	T207
Test name
Test status
Simulation time	5618472300 ps
CPU time	491.59 seconds
Started	Jul 23 04:44:28 PM PDT 24
Finished	Jul 23 04:52:43 PM PDT 24
Peak memory	263400 kb
Host	smart-4fa43ac0-20ac-45f9-99df-113a3b61d825
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2208241695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.2208241695
Directory	/workspace/4.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.4224862755
Short name	T223
Test name
Test status
Simulation time	57566300 ps
CPU time	15.87 seconds
Started	Jul 23 04:39:02 PM PDT 24
Finished	Jul 23 04:39:20 PM PDT 24
Peak memory	264188 kb
Host	smart-fa307aec-13ee-4099-bba0-7e903813093c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224862755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.4 224862755
Directory	/workspace/3.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.2348139867
Short name	T10
Test name
Test status
Simulation time	27278500 ps
CPU time	14.02 seconds
Started	Jul 23 04:44:33 PM PDT 24
Finished	Jul 23 04:44:51 PM PDT 24
Peak memory	262964 kb
Host	smart-ac482cdc-2ed0-4d0a-8d60-af66588189b2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348139867 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.2348139867
Directory	/workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_type.3558856784
Short name	T82
Test name
Test status
Simulation time	10656691700 ps
CPU time	2563.1 seconds
Started	Jul 23 04:44:26 PM PDT 24
Finished	Jul 23 05:27:14 PM PDT 24
Peak memory	262016 kb
Host	smart-e0bf90fe-5411-4b63-b16c-f36a602abde4
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558856784 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.3558856784
Directory	/workspace/3.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/6.flash_ctrl_otp_reset.3617077103
Short name	T190
Test name
Test status
Simulation time	73850500 ps
CPU time	111.45 seconds
Started	Jul 23 04:44:33 PM PDT 24
Finished	Jul 23 04:46:28 PM PDT 24
Peak memory	260148 kb
Host	smart-3585eaed-01c1-4b45-843c-6a1570c1cc97
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617077103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot p_reset.3617077103
Directory	/workspace/6.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/53.flash_ctrl_otp_reset.3682382157
Short name	T186
Test name
Test status
Simulation time	69880900 ps
CPU time	134.93 seconds
Started	Jul 23 04:48:00 PM PDT 24
Finished	Jul 23 04:50:17 PM PDT 24
Peak memory	260324 kb
Host	smart-acbc18c6-a682-4fc1-87f1-066d7d4ea035
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682382157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o tp_reset.3682382157
Directory	/workspace/53.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_otp_reset.1815621821
Short name	T179
Test name
Test status
Simulation time	65062100 ps
CPU time	134 seconds
Started	Jul 23 04:43:17 PM PDT 24
Finished	Jul 23 04:46:01 PM PDT 24
Peak memory	260268 kb
Host	smart-deb1b033-cfc8-486f-9e35-c638d89f77db
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815621821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot p_reset.1815621821
Directory	/workspace/0.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2582145232
Short name	T354
Test name
Test status
Simulation time	26465700 ps
CPU time	13.36 seconds
Started	Jul 23 04:39:57 PM PDT 24
Finished	Jul 23 04:40:13 PM PDT 24
Peak memory	261900 kb
Host	smart-15d578cb-553d-4d65-b29a-e83e25d7c3fe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582145232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test. 2582145232
Directory	/workspace/26.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb_redun.1792170247
Short name	T47
Test name
Test status
Simulation time	916005000 ps
CPU time	21.7 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 04:44:17 PM PDT 24
Peak memory	265452 kb
Host	smart-eabfb677-f17e-431f-8842-0d60284896bf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792170247 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.1792170247
Directory	/workspace/0.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.568689838
Short name	T110
Test name
Test status
Simulation time	10019381800 ps
CPU time	84.03 seconds
Started	Jul 23 04:45:54 PM PDT 24
Finished	Jul 23 04:47:20 PM PDT 24
Peak memory	314452 kb
Host	smart-a2721d58-7a52-46c2-8b49-707ebdcb568c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568689838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.568689838
Directory	/workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_lcmgr_intg.1266110747
Short name	T170
Test name
Test status
Simulation time	23144300 ps
CPU time	13.64 seconds
Started	Jul 23 04:44:39 PM PDT 24
Finished	Jul 23 04:44:57 PM PDT 24
Peak memory	264848 kb
Host	smart-8f94a93d-c596-4f60-a53f-2dea15cd8ae7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266110747 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.1266110747
Directory	/workspace/6.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rma_err.156335916
Short name	T77
Test name
Test status
Simulation time	178952864700 ps
CPU time	997.87 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 05:00:33 PM PDT 24
Peak memory	263816 kb
Host	smart-73301aac-5b4d-40bf-bac3-1df3c11a05d9
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156335916 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.156335916
Directory	/workspace/0.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3070561644
Short name	T297
Test name
Test status
Simulation time	344946800 ps
CPU time	895.49 seconds
Started	Jul 23 04:39:33 PM PDT 24
Finished	Jul 23 04:54:31 PM PDT 24
Peak memory	264424 kb
Host	smart-58560c0a-35bd-49ad-8145-7b545ddf90c6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070561644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr l_tl_intg_err.3070561644
Directory	/workspace/12.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_access_after_disable.3822568275
Short name	T5
Test name
Test status
Simulation time	22348500 ps
CPU time	13.54 seconds
Started	Jul 23 04:44:07 PM PDT 24
Finished	Jul 23 04:44:22 PM PDT 24
Peak memory	265380 kb
Host	smart-b4ee233c-43fa-46fe-bcf8-d419a6befcd5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822568275 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.3822568275
Directory	/workspace/2.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/48.flash_ctrl_sec_info_access.2495149672
Short name	T413
Test name
Test status
Simulation time	3295564400 ps
CPU time	71.27 seconds
Started	Jul 23 04:47:55 PM PDT 24
Finished	Jul 23 04:49:09 PM PDT 24
Peak memory	264172 kb
Host	smart-44accdf1-1a2e-427c-b444-a6d88c259dd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2495149672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.2495149672
Directory	/workspace/48.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/78.flash_ctrl_otp_reset.462982184
Short name	T692
Test name
Test status
Simulation time	73056600 ps
CPU time	130.43 seconds
Started	Jul 23 04:48:13 PM PDT 24
Finished	Jul 23 04:50:29 PM PDT 24
Peak memory	264732 kb
Host	smart-bb770d5b-3234-4499-aa59-31bb12e623f7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462982184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_ot p_reset.462982184
Directory	/workspace/78.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2387302935
Short name	T871
Test name
Test status
Simulation time	10034065900 ps
CPU time	105.46 seconds
Started	Jul 23 04:45:44 PM PDT 24
Finished	Jul 23 04:47:31 PM PDT 24
Peak memory	275656 kb
Host	smart-49d647a5-acd0-4ea6-8522-9d57211821b5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387302935 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.2387302935
Directory	/workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/30.flash_ctrl_alert_test.232330618
Short name	T91
Test name
Test status
Simulation time	50075400 ps
CPU time	14.05 seconds
Started	Jul 23 04:47:02 PM PDT 24
Finished	Jul 23 04:47:20 PM PDT 24
Peak memory	258256 kb
Host	smart-68a070ec-453d-4c8b-82b4-54960867c461
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232330618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.232330618
Directory	/workspace/30.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_derr.3232378093
Short name	T215
Test name
Test status
Simulation time	4711000600 ps
CPU time	715.97 seconds
Started	Jul 23 04:44:40 PM PDT 24
Finished	Jul 23 04:56:40 PM PDT 24
Peak memory	326348 kb
Host	smart-7448c04f-252d-4d2a-9c44-39b344c7d857
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232378093 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 6.flash_ctrl_rw_derr.3232378093
Directory	/workspace/6.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.2142895269
Short name	T212
Test name
Test status
Simulation time	72939600 ps
CPU time	14.1 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 04:44:09 PM PDT 24
Peak memory	262860 kb
Host	smart-211f37c7-955d-457b-9551-e0af55401ab6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142895269 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2142895269
Directory	/workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rand_ops.1118661400
Short name	T63
Test name
Test status
Simulation time	903573600 ps
CPU time	398.19 seconds
Started	Jul 23 04:45:17 PM PDT 24
Finished	Jul 23 04:51:57 PM PDT 24
Peak memory	282540 kb
Host	smart-bab96b29-7160-46a4-a0a0-8c7bbb54f79c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1118661400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.1118661400
Directory	/workspace/12.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/0.flash_ctrl_fetch_code.2365678750
Short name	T39
Test name
Test status
Simulation time	1150503000 ps
CPU time	24.15 seconds
Started	Jul 23 04:43:22 PM PDT 24
Finished	Jul 23 04:44:12 PM PDT 24
Peak memory	262620 kb
Host	smart-4d4b91d1-1d47-4c8b-85ce-b9156435fc5e
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365678750 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.2365678750
Directory	/workspace/0.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.580306547
Short name	T34
Test name
Test status
Simulation time	24042376800 ps
CPU time	275.33 seconds
Started	Jul 23 04:47:31 PM PDT 24
Finished	Jul 23 04:52:09 PM PDT 24
Peak memory	290904 kb
Host	smart-2c976927-062a-432f-aff8-68ab52920f14
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580306547 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.580306547
Directory	/workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3436804500
Short name	T275
Test name
Test status
Simulation time	117095400 ps
CPU time	18.73 seconds
Started	Jul 23 04:39:35 PM PDT 24
Finished	Jul 23 04:39:55 PM PDT 24
Peak memory	264428 kb
Host	smart-cc546593-d360-4af2-999b-145eb0be329a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436804500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors. 3436804500
Directory	/workspace/10.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/15.flash_ctrl_re_evict.2095937659
Short name	T24
Test name
Test status
Simulation time	225203300 ps
CPU time	34.09 seconds
Started	Jul 23 04:45:46 PM PDT 24
Finished	Jul 23 04:46:22 PM PDT 24
Peak memory	275576 kb
Host	smart-c3065497-6e2e-40d2-98e2-776d81217cb2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095937659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl ash_ctrl_re_evict.2095937659
Directory	/workspace/15.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3051421918
Short name	T259
Test name
Test status
Simulation time	48410800 ps
CPU time	13.52 seconds
Started	Jul 23 04:39:17 PM PDT 24
Finished	Jul 23 04:39:32 PM PDT 24
Peak memory	263320 kb
Host	smart-b4ff95ae-f755-4911-a7a3-c76a7acf5e01
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051421918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_mem_partial_access.3051421918
Directory	/workspace/3.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/18.flash_ctrl_mp_regions.3158694046
Short name	T145
Test name
Test status
Simulation time	41471283500 ps
CPU time	208.71 seconds
Started	Jul 23 04:46:07 PM PDT 24
Finished	Jul 23 04:49:38 PM PDT 24
Peak memory	265208 kb
Host	smart-45d821f0-43e2-4252-86e9-55ec999016a9
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158694046 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_mp_regions.3158694046
Directory	/workspace/18.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_evict.905248629
Short name	T227
Test name
Test status
Simulation time	31829700 ps
CPU time	28.17 seconds
Started	Jul 23 04:44:31 PM PDT 24
Finished	Jul 23 04:45:03 PM PDT 24
Peak memory	275556 kb
Host	smart-eb9b0eb3-f187-4a5d-b6bf-aef04853d588
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905248629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_rw_evict.905248629
Directory	/workspace/4.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd.3062005537
Short name	T356
Test name
Test status
Simulation time	993142500 ps
CPU time	142.84 seconds
Started	Jul 23 04:44:52 PM PDT 24
Finished	Jul 23 04:47:18 PM PDT 24
Peak memory	293964 kb
Host	smart-9f9f3289-dde6-43b2-ad0a-9ac655c3e8fc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062005537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_intr_rd.3062005537
Directory	/workspace/7.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1404182441
Short name	T282
Test name
Test status
Simulation time	24365500 ps
CPU time	13.53 seconds
Started	Jul 23 04:39:57 PM PDT 24
Finished	Jul 23 04:40:13 PM PDT 24
Peak memory	261848 kb
Host	smart-b590e4ad-68a5-449c-9671-02851abf5de3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404182441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test. 1404182441
Directory	/workspace/35.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/5.flash_ctrl_re_evict.3333355322
Short name	T237
Test name
Test status
Simulation time	374596100 ps
CPU time	34.24 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 04:45:15 PM PDT 24
Peak memory	275584 kb
Host	smart-dbf02020-3b37-4fa6-9efb-33b8e0250a36
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333355322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_re_evict.3333355322
Directory	/workspace/5.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_cm.3663009917
Short name	T14
Test name
Test status
Simulation time	992654200 ps
CPU time	4752.27 seconds
Started	Jul 23 04:43:39 PM PDT 24
Finished	Jul 23 06:03:07 PM PDT 24
Peak memory	286636 kb
Host	smart-610e333a-efff-4044-9234-550cb71de183
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663009917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.3663009917
Directory	/workspace/0.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/13.flash_ctrl_invalid_op.736914533
Short name	T160
Test name
Test status
Simulation time	4018018200 ps
CPU time	87.44 seconds
Started	Jul 23 04:45:37 PM PDT 24
Finished	Jul 23 04:47:07 PM PDT 24
Peak memory	263552 kb
Host	smart-e7e542a8-2484-40ce-bd68-35214c2cc59b
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736914533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.736914533
Directory	/workspace/13.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_wr_intg.3901845470
Short name	T6
Test name
Test status
Simulation time	83951000 ps
CPU time	14.71 seconds
Started	Jul 23 04:43:40 PM PDT 24
Finished	Jul 23 04:44:10 PM PDT 24
Peak memory	265084 kb
Host	smart-bd59fa8b-c261-4fdb-b59e-d95ce5803808
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901845470 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.3901845470
Directory	/workspace/0.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2756083325
Short name	T374
Test name
Test status
Simulation time	909952000 ps
CPU time	20.12 seconds
Started	Jul 23 04:39:43 PM PDT 24
Finished	Jul 23 04:40:05 PM PDT 24
Peak memory	264424 kb
Host	smart-19c42c01-fe64-42bc-9bd0-22b6da1ab318
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756083325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors. 2756083325
Directory	/workspace/16.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3200957170
Short name	T292
Test name
Test status
Simulation time	1580009000 ps
CPU time	898.44 seconds
Started	Jul 23 04:39:48 PM PDT 24
Finished	Jul 23 04:54:47 PM PDT 24
Peak memory	264512 kb
Host	smart-06c721fc-ca88-4789-9181-b64738c05629
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200957170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr l_tl_intg_err.3200957170
Directory	/workspace/19.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_derr.2840551089
Short name	T218
Test name
Test status
Simulation time	2054805100 ps
CPU time	134.22 seconds
Started	Jul 23 04:44:42 PM PDT 24
Finished	Jul 23 04:46:59 PM PDT 24
Peak memory	281756 kb
Host	smart-b6f30470-2732-4564-80c7-a35fc49d8d3a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2840551089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.2840551089
Directory	/workspace/6.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.1229571740
Short name	T75
Test name
Test status
Simulation time	567195435000 ps
CPU time	2584.7 seconds
Started	Jul 23 04:44:25 PM PDT 24
Finished	Jul 23 05:27:34 PM PDT 24
Peak memory	265168 kb
Host	smart-1eebacd0-8398-4722-b677-b5906c35827c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229571740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.flash_ctrl_host_ctrl_arb.1229571740
Directory	/workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro.1762568600
Short name	T46
Test name
Test status
Simulation time	1597269100 ps
CPU time	124.22 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 04:46:56 PM PDT 24
Peak memory	289784 kb
Host	smart-ff0e12e6-4f6a-4ace-8633-9fd83ba245e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762568600 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_ro.1762568600
Directory	/workspace/8.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/11.flash_ctrl_lcmgr_intg.1926116650
Short name	T171
Test name
Test status
Simulation time	26491400 ps
CPU time	13.29 seconds
Started	Jul 23 04:45:15 PM PDT 24
Finished	Jul 23 04:45:30 PM PDT 24
Peak memory	260800 kb
Host	smart-9a53f7b0-7ea8-4b3b-aada-ac8b2cc56052
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926116650 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.1926116650
Directory	/workspace/11.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_arb_redun.2796339119
Short name	T70
Test name
Test status
Simulation time	816475300 ps
CPU time	21.92 seconds
Started	Jul 23 04:44:33 PM PDT 24
Finished	Jul 23 04:44:59 PM PDT 24
Peak memory	265468 kb
Host	smart-0a767a34-b3f8-4786-8d21-d6f3433bcd30
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796339119 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.2796339119
Directory	/workspace/4.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fs_sup.485292277
Short name	T436
Test name
Test status
Simulation time	629947900 ps
CPU time	39.88 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 04:45:20 PM PDT 24
Peak memory	263012 kb
Host	smart-1b3966a0-df53-47cc-affc-e0d87c0ee247
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485292277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 4.flash_ctrl_fs_sup.485292277
Directory	/workspace/4.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2192002558
Short name	T322
Test name
Test status
Simulation time	99865300 ps
CPU time	39.29 seconds
Started	Jul 23 04:39:05 PM PDT 24
Finished	Jul 23 04:39:46 PM PDT 24
Peak memory	261828 kb
Host	smart-8bae5f96-8e04-46bb-b49a-e46f52bf47ba
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192002558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_hw_reset.2192002558
Directory	/workspace/1.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/default/46.flash_ctrl_disable.2782512096
Short name	T99
Test name
Test status
Simulation time	19288000 ps
CPU time	21.72 seconds
Started	Jul 23 04:47:56 PM PDT 24
Finished	Jul 23 04:48:21 PM PDT 24
Peak memory	273480 kb
Host	smart-d511582c-0737-4947-82ce-fee8c099452d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782512096 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_disable.2782512096
Directory	/workspace/46.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.372162019
Short name	T247
Test name
Test status
Simulation time	15432300 ps
CPU time	13.79 seconds
Started	Jul 23 04:44:33 PM PDT 24
Finished	Jul 23 04:44:51 PM PDT 24
Peak memory	265076 kb
Host	smart-386edae3-b795-4530-b850-9bff4a85ab1d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=372162019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.372162019
Directory	/workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/3.flash_ctrl_re_evict.481493091
Short name	T299
Test name
Test status
Simulation time	269194600 ps
CPU time	34.38 seconds
Started	Jul 23 04:44:22 PM PDT 24
Finished	Jul 23 04:45:00 PM PDT 24
Peak memory	275628 kb
Host	smart-e7d13908-6d0e-45ee-bdc9-9fe57de676de
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481493091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_re_evict.481493091
Directory	/workspace/3.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_oversize_error.1903451452
Short name	T137
Test name
Test status
Simulation time	3748583100 ps
CPU time	188.48 seconds
Started	Jul 23 04:44:08 PM PDT 24
Finished	Jul 23 04:47:20 PM PDT 24
Peak memory	281704 kb
Host	smart-236f2f1c-b884-4171-a4cf-224ea92dd728
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903451452 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.1903451452
Directory	/workspace/2.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/59.flash_ctrl_connect.2452958702
Short name	T54
Test name
Test status
Simulation time	49612800 ps
CPU time	13.29 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:48:24 PM PDT 24
Peak memory	274820 kb
Host	smart-08d16be9-b3a4-46b2-82ff-4b9350f919ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2452958702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.2452958702
Directory	/workspace/59.flash_ctrl_connect/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2350286031
Short name	T381
Test name
Test status
Simulation time	2939699200 ps
CPU time	906.89 seconds
Started	Jul 23 04:39:28 PM PDT 24
Finished	Jul 23 04:54:37 PM PDT 24
Peak memory	264404 kb
Host	smart-1bee257e-67bf-4bf3-af1d-69ce0c5984f3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350286031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl _tl_intg_err.2350286031
Directory	/workspace/4.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.1801236643
Short name	T169
Test name
Test status
Simulation time	54714800 ps
CPU time	13.53 seconds
Started	Jul 23 04:45:16 PM PDT 24
Finished	Jul 23 04:45:31 PM PDT 24
Peak memory	264856 kb
Host	smart-5a4cfcd2-c252-42df-a63a-fcf48c963806
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801236643 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.1801236643
Directory	/workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/20.flash_ctrl_rw_evict.2658784123
Short name	T435
Test name
Test status
Simulation time	38799500 ps
CPU time	31.2 seconds
Started	Jul 23 04:46:26 PM PDT 24
Finished	Jul 23 04:46:58 PM PDT 24
Peak memory	275632 kb
Host	smart-8d2c0ffc-a77c-4455-b8ef-a9bfc0861163
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658784123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl ash_ctrl_rw_evict.2658784123
Directory	/workspace/20.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3121305630
Short name	T87
Test name
Test status
Simulation time	12113620600 ps
CPU time	256.42 seconds
Started	Jul 23 04:46:53 PM PDT 24
Finished	Jul 23 04:51:17 PM PDT 24
Peak memory	294108 kb
Host	smart-3e2aad04-1f3a-497e-81ab-049189c8cf32
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121305630 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.3121305630
Directory	/workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.2051176999
Short name	T233
Test name
Test status
Simulation time	43651200 ps
CPU time	13.8 seconds
Started	Jul 23 04:44:21 PM PDT 24
Finished	Jul 23 04:44:37 PM PDT 24
Peak memory	265612 kb
Host	smart-0db37445-aa49-4c01-a527-ede3d129c1aa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051176999 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.2051176999
Directory	/workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw_evict.2093233073
Short name	T93
Test name
Test status
Simulation time	29685200 ps
CPU time	31.07 seconds
Started	Jul 23 04:45:44 PM PDT 24
Finished	Jul 23 04:46:18 PM PDT 24
Peak memory	275632 kb
Host	smart-d0975b7b-392d-4454-b2e2-361ef15af218
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093233073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl ash_ctrl_rw_evict.2093233073
Directory	/workspace/15.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3567195526
Short name	T290
Test name
Test status
Simulation time	16087644000 ps
CPU time	767.78 seconds
Started	Jul 23 04:39:33 PM PDT 24
Finished	Jul 23 04:52:23 PM PDT 24
Peak memory	264556 kb
Host	smart-355dacf9-3a5b-48b2-be70-33ff1939f3fe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567195526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr l_tl_intg_err.3567195526
Directory	/workspace/13.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.3751257330
Short name	T141
Test name
Test status
Simulation time	52296400 ps
CPU time	13.63 seconds
Started	Jul 23 04:43:38 PM PDT 24
Finished	Jul 23 04:44:07 PM PDT 24
Peak memory	258716 kb
Host	smart-d4e8b000-8e81-4c50-8cdc-6e370d198f4d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751257330 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.3751257330
Directory	/workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3402066112
Short name	T971
Test name
Test status
Simulation time	10012493100 ps
CPU time	109.12 seconds
Started	Jul 23 04:44:11 PM PDT 24
Finished	Jul 23 04:46:04 PM PDT 24
Peak memory	292104 kb
Host	smart-edff1206-da61-4c7d-89f0-72f5a052d38a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402066112 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.3402066112
Directory	/workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1401349402
Short name	T1153
Test name
Test status
Simulation time	27125100 ps
CPU time	14.36 seconds
Started	Jul 23 04:39:58 PM PDT 24
Finished	Jul 23 04:40:15 PM PDT 24
Peak memory	261744 kb
Host	smart-57158a6b-09a0-487e-8f62-4dcd19ac89bc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401349402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test. 1401349402
Directory	/workspace/19.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_info_access.716080163
Short name	T790
Test name
Test status
Simulation time	10213032700 ps
CPU time	93.33 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 04:45:29 PM PDT 24
Peak memory	263180 kb
Host	smart-49723850-041a-4698-b55d-4bf6b7516a40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=716080163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.716080163
Directory	/workspace/0.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/24.flash_ctrl_sec_info_access.3620143028
Short name	T406
Test name
Test status
Simulation time	2077061900 ps
CPU time	69.38 seconds
Started	Jul 23 04:46:45 PM PDT 24
Finished	Jul 23 04:48:00 PM PDT 24
Peak memory	264540 kb
Host	smart-96d633c5-ba7c-47b9-b72a-240acbd096f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3620143028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.3620143028
Directory	/workspace/24.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/44.flash_ctrl_smoke.3210882666
Short name	T139
Test name
Test status
Simulation time	71796300 ps
CPU time	97.29 seconds
Started	Jul 23 04:47:42 PM PDT 24
Finished	Jul 23 04:49:20 PM PDT 24
Peak memory	277324 kb
Host	smart-f20ced04-fd0f-4bae-a2f2-96219c03dfb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3210882666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.3210882666
Directory	/workspace/44.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.flash_ctrl_access_after_disable.3867133857
Short name	T22
Test name
Test status
Simulation time	13837000 ps
CPU time	13.78 seconds
Started	Jul 23 04:43:50 PM PDT 24
Finished	Jul 23 04:44:12 PM PDT 24
Peak memory	261592 kb
Host	smart-3bdf422d-ed50-4c55-bc07-d3d587f8774c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867133857 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.3867133857
Directory	/workspace/1.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.2832088694
Short name	T57
Test name
Test status
Simulation time	43038500 ps
CPU time	14.01 seconds
Started	Jul 23 04:44:10 PM PDT 24
Finished	Jul 23 04:44:28 PM PDT 24
Peak memory	279172 kb
Host	smart-6463bb26-6ffa-42df-8dea-98128da20fea
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2832088694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.2832088694
Directory	/workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/18.flash_ctrl_disable.1703089947
Short name	T11
Test name
Test status
Simulation time	10979800 ps
CPU time	21.67 seconds
Started	Jul 23 04:46:05 PM PDT 24
Finished	Jul 23 04:46:29 PM PDT 24
Peak memory	273536 kb
Host	smart-506b5706-7381-4ab7-8581-187fb55c1287
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703089947 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_disable.1703089947
Directory	/workspace/18.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/0.flash_ctrl_config_regwen.3681728789
Short name	T164
Test name
Test status
Simulation time	22856300 ps
CPU time	14.08 seconds
Started	Jul 23 04:43:39 PM PDT 24
Finished	Jul 23 04:44:09 PM PDT 24
Peak memory	261452 kb
Host	smart-55ad224d-506d-4ca0-9814-ba7008e8a62f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681728789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .flash_ctrl_config_regwen.3681728789
Directory	/workspace/0.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd.3512358996
Short name	T965
Test name
Test status
Simulation time	4801770700 ps
CPU time	198.85 seconds
Started	Jul 23 04:46:15 PM PDT 24
Finished	Jul 23 04:49:36 PM PDT 24
Peak memory	290912 kb
Host	smart-1f49af82-b9df-423a-9f1b-e31ca6d12783
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512358996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_intr_rd.3512358996
Directory	/workspace/19.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_invalid_op.620701477
Short name	T122
Test name
Test status
Simulation time	1020117200 ps
CPU time	88.3 seconds
Started	Jul 23 04:44:22 PM PDT 24
Finished	Jul 23 04:45:54 PM PDT 24
Peak memory	263556 kb
Host	smart-1b817091-8f52-4ef3-8921-7dfc940ca2ff
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620701477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.620701477
Directory	/workspace/3.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/13.flash_ctrl_lcmgr_intg.607548666
Short name	T943
Test name
Test status
Simulation time	32911200 ps
CPU time	13.28 seconds
Started	Jul 23 04:45:36 PM PDT 24
Finished	Jul 23 04:45:50 PM PDT 24
Peak memory	264856 kb
Host	smart-3e76c376-e101-4be0-92b0-6e80d4690043
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607548666 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.607548666
Directory	/workspace/13.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.239330744
Short name	T291
Test name
Test status
Simulation time	69896200 ps
CPU time	19.48 seconds
Started	Jul 23 04:39:06 PM PDT 24
Finished	Jul 23 04:39:27 PM PDT 24
Peak memory	264424 kb
Host	smart-fb9056ab-d5f7-4d72-a109-b02d40e94481
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239330744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.239330744
Directory	/workspace/0.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3463455337
Short name	T376
Test name
Test status
Simulation time	847371800 ps
CPU time	460.02 seconds
Started	Jul 23 04:39:38 PM PDT 24
Finished	Jul 23 04:47:19 PM PDT 24
Peak memory	264416 kb
Host	smart-ff611c22-8638-4f1f-8377-c83b895bb882
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463455337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr l_tl_intg_err.3463455337
Directory	/workspace/11.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3387497337
Short name	T384
Test name
Test status
Simulation time	400878500 ps
CPU time	906.83 seconds
Started	Jul 23 04:39:42 PM PDT 24
Finished	Jul 23 04:54:51 PM PDT 24
Peak memory	264440 kb
Host	smart-797471d5-cc74-4082-b196-32fe0a300ce5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387497337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr l_tl_intg_err.3387497337
Directory	/workspace/17.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_disable.579899173
Short name	T9
Test name
Test status
Simulation time	21228300 ps
CPU time	21.82 seconds
Started	Jul 23 04:43:51 PM PDT 24
Finished	Jul 23 04:44:21 PM PDT 24
Peak memory	273568 kb
Host	smart-02cec1da-2ae1-4cb7-9ec7-77faad083e0c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579899173 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_disable.579899173
Directory	/workspace/1.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.675879554
Short name	T439
Test name
Test status
Simulation time	27854900 ps
CPU time	27.96 seconds
Started	Jul 23 04:45:14 PM PDT 24
Finished	Jul 23 04:45:42 PM PDT 24
Peak memory	275636 kb
Host	smart-3c8a2709-1de0-4d11-93ea-2305cf193d0a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675879554 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.675879554
Directory	/workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/12.flash_ctrl_disable.443453612
Short name	T74
Test name
Test status
Simulation time	13734100 ps
CPU time	20.59 seconds
Started	Jul 23 04:45:27 PM PDT 24
Finished	Jul 23 04:45:50 PM PDT 24
Peak memory	273612 kb
Host	smart-9ba3f611-7e5e-4ee2-84f5-2253fdd245c9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443453612 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_disable.443453612
Directory	/workspace/12.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/12.flash_ctrl_sec_info_access.1664087822
Short name	T460
Test name
Test status
Simulation time	14693852100 ps
CPU time	67.5 seconds
Started	Jul 23 04:45:24 PM PDT 24
Finished	Jul 23 04:46:34 PM PDT 24
Peak memory	259676 kb
Host	smart-2ec3dee9-7179-4709-bc5b-cd7349e15302
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664087822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.1664087822
Directory	/workspace/12.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/15.flash_ctrl_sec_info_access.679034977
Short name	T410
Test name
Test status
Simulation time	10549575700 ps
CPU time	70.95 seconds
Started	Jul 23 04:45:46 PM PDT 24
Finished	Jul 23 04:46:59 PM PDT 24
Peak memory	263608 kb
Host	smart-e57b6b3e-59f1-47f7-9d71-2b26c372af4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=679034977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.679034977
Directory	/workspace/15.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/16.flash_ctrl_sec_info_access.2097317462
Short name	T702
Test name
Test status
Simulation time	1684678800 ps
CPU time	69.77 seconds
Started	Jul 23 04:45:50 PM PDT 24
Finished	Jul 23 04:47:01 PM PDT 24
Peak memory	265020 kb
Host	smart-20ac5326-cea8-4451-9710-ef61ccd60a45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2097317462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.2097317462
Directory	/workspace/16.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/17.flash_ctrl_disable.1263708806
Short name	T156
Test name
Test status
Simulation time	12948800 ps
CPU time	20.62 seconds
Started	Jul 23 04:45:58 PM PDT 24
Finished	Jul 23 04:46:20 PM PDT 24
Peak memory	273556 kb
Host	smart-a2035b2e-95d9-4000-add6-6dfab5e78344
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263708806 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_disable.1263708806
Directory	/workspace/17.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/18.flash_ctrl_sec_info_access.4016905908
Short name	T414
Test name
Test status
Simulation time	1830477300 ps
CPU time	62.09 seconds
Started	Jul 23 04:46:05 PM PDT 24
Finished	Jul 23 04:47:09 PM PDT 24
Peak memory	263532 kb
Host	smart-6a486b83-0f72-4e87-83c3-dc1696876620
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016905908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.4016905908
Directory	/workspace/18.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/19.flash_ctrl_sec_info_access.1608875980
Short name	T409
Test name
Test status
Simulation time	2578643300 ps
CPU time	63.73 seconds
Started	Jul 23 04:46:15 PM PDT 24
Finished	Jul 23 04:47:20 PM PDT 24
Peak memory	263540 kb
Host	smart-da187efd-6f20-47ed-b119-fa156f7cb481
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608875980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.1608875980
Directory	/workspace/19.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_disable.3553669508
Short name	T805
Test name
Test status
Simulation time	10941800 ps
CPU time	22.3 seconds
Started	Jul 23 04:44:11 PM PDT 24
Finished	Jul 23 04:44:37 PM PDT 24
Peak memory	273592 kb
Host	smart-e12c12ac-d65b-427f-8c7a-e3f2b7fc6679
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553669508 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_disable.3553669508
Directory	/workspace/2.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/23.flash_ctrl_sec_info_access.4063321699
Short name	T405
Test name
Test status
Simulation time	4839291900 ps
CPU time	69.85 seconds
Started	Jul 23 04:46:37 PM PDT 24
Finished	Jul 23 04:47:50 PM PDT 24
Peak memory	265016 kb
Host	smart-b1a4413a-f14b-424f-9e8f-a8db46d92fb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4063321699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.4063321699
Directory	/workspace/23.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/25.flash_ctrl_disable.4156470847
Short name	T1027
Test name
Test status
Simulation time	12227800 ps
CPU time	22.14 seconds
Started	Jul 23 04:46:45 PM PDT 24
Finished	Jul 23 04:47:12 PM PDT 24
Peak memory	273484 kb
Host	smart-106d5d98-21eb-4073-a070-4f4726720c86
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156470847 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_disable.4156470847
Directory	/workspace/25.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_evict.3100886535
Short name	T428
Test name
Test status
Simulation time	57324000 ps
CPU time	30.72 seconds
Started	Jul 23 04:44:21 PM PDT 24
Finished	Jul 23 04:44:53 PM PDT 24
Peak memory	273680 kb
Host	smart-03610f51-471f-4d7c-ba4b-edb0d5eed36b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100886535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_rw_evict.3100886535
Directory	/workspace/3.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/31.flash_ctrl_disable.709433594
Short name	T404
Test name
Test status
Simulation time	17266900 ps
CPU time	21.92 seconds
Started	Jul 23 04:46:59 PM PDT 24
Finished	Jul 23 04:47:27 PM PDT 24
Peak memory	265404 kb
Host	smart-388e31e1-3c85-4893-ab1f-276cf846ad89
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709433594 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_disable.709433594
Directory	/workspace/31.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_evict.1431929895
Short name	T236
Test name
Test status
Simulation time	107041400 ps
CPU time	31.39 seconds
Started	Jul 23 04:44:40 PM PDT 24
Finished	Jul 23 04:45:15 PM PDT 24
Peak memory	267484 kb
Host	smart-48e4e799-073d-4c7d-b7ee-0429039ef4bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431929895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla sh_ctrl_rw_evict.1431929895
Directory	/workspace/6.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb_redun.2397344856
Short name	T72
Test name
Test status
Simulation time	815780100 ps
CPU time	20.59 seconds
Started	Jul 23 04:43:50 PM PDT 24
Finished	Jul 23 04:44:19 PM PDT 24
Peak memory	265360 kb
Host	smart-e3034b78-d8fe-4f2c-b81b-c01c498cba5a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397344856 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.2397344856
Directory	/workspace/1.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_rma_reset.66527221
Short name	T178
Test name
Test status
Simulation time	160164335700 ps
CPU time	882.68 seconds
Started	Jul 23 04:45:45 PM PDT 24
Finished	Jul 23 05:00:30 PM PDT 24
Peak memory	264572 kb
Host	smart-6f323caf-5b51-4cb5-97d2-13df41eebda4
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66527221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 15.flash_ctrl_hw_rma_reset.66527221
Directory	/workspace/15.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr.1355972205
Short name	T789
Test name
Test status
Simulation time	11020187400 ps
CPU time	75.92 seconds
Started	Jul 23 04:44:09 PM PDT 24
Finished	Jul 23 04:45:28 PM PDT 24
Peak memory	265340 kb
Host	smart-78fb85ad-1774-4404-8e71-906a3f4351fb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355972205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_intr_wr.1355972205
Directory	/workspace/2.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_derr.3856078801
Short name	T231
Test name
Test status
Simulation time	3685922700 ps
CPU time	651.42 seconds
Started	Jul 23 04:44:22 PM PDT 24
Finished	Jul 23 04:55:16 PM PDT 24
Peak memory	325300 kb
Host	smart-5ec8161a-72e9-49d7-98bd-deb570d30783
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856078801 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_rw_derr.3856078801
Directory	/workspace/3.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw.844290751
Short name	T239
Test name
Test status
Simulation time	6683077800 ps
CPU time	508.66 seconds
Started	Jul 23 04:45:14 PM PDT 24
Finished	Jul 23 04:53:43 PM PDT 24
Peak memory	310316 kb
Host	smart-ab47fb23-7d61-4c77-b68d-743b0d74238c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844290751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw.844290751
Directory	/workspace/11.flash_ctrl_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3559139367
Short name	T298
Test name
Test status
Simulation time	366241500 ps
CPU time	456.86 seconds
Started	Jul 23 04:39:28 PM PDT 24
Finished	Jul 23 04:47:07 PM PDT 24
Peak memory	264420 kb
Host	smart-0a361c6b-2597-47f9-be9e-c74498e0e371
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559139367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl _tl_intg_err.3559139367
Directory	/workspace/7.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_mp.354656746
Short name	T158
Test name
Test status
Simulation time	6591578500 ps
CPU time	2245.42 seconds
Started	Jul 23 04:43:18 PM PDT 24
Finished	Jul 23 05:21:13 PM PDT 24
Peak memory	264408 kb
Host	smart-b60920e9-e40a-4751-bfca-4110b7105f01
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=354656746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.354656746
Directory	/workspace/0.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_win.1463089419
Short name	T219
Test name
Test status
Simulation time	325075500 ps
CPU time	792.52 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 04:57:54 PM PDT 24
Peak memory	273160 kb
Host	smart-076f0955-e610-40c6-8a86-52514ef5c0ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1463089419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.1463089419
Directory	/workspace/0.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.206823715
Short name	T232
Test name
Test status
Simulation time	985313301900 ps
CPU time	1982.9 seconds
Started	Jul 23 04:44:36 PM PDT 24
Finished	Jul 23 05:17:45 PM PDT 24
Peak memory	263948 kb
Host	smart-e8e815f7-871c-4ba5-a3e7-e95f03d41ede
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206823715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.flash_ctrl_host_ctrl_arb.206823715
Directory	/workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mid_op_rst.2928330362
Short name	T89
Test name
Test status
Simulation time	648737600 ps
CPU time	74.17 seconds
Started	Jul 23 04:43:19 PM PDT 24
Finished	Jul 23 04:45:01 PM PDT 24
Peak memory	260436 kb
Host	smart-634ae8e3-4169-4cf9-9603-0a267ac7490c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2928330362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.2928330362
Directory	/workspace/0.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mp_regions.747239449
Short name	T149
Test name
Test status
Simulation time	18476488600 ps
CPU time	302.43 seconds
Started	Jul 23 04:43:26 PM PDT 24
Finished	Jul 23 04:48:51 PM PDT 24
Peak memory	273752 kb
Host	smart-57c7626d-0f0f-4ce5-a4ef-ee28aedf4c0e
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747239449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.747239449
Directory	/workspace/0.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/1.flash_ctrl_re_evict.2820939705
Short name	T304
Test name
Test status
Simulation time	95086900 ps
CPU time	33.7 seconds
Started	Jul 23 04:43:49 PM PDT 24
Finished	Jul 23 04:44:32 PM PDT 24
Peak memory	273540 kb
Host	smart-c6396b90-1a15-4ef5-a501-afa51272a3cc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820939705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_re_evict.2820939705
Directory	/workspace/1.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_cm.3514459792
Short name	T12
Test name
Test status
Simulation time	6195266900 ps
CPU time	4719.14 seconds
Started	Jul 23 04:43:51 PM PDT 24
Finished	Jul 23 06:02:39 PM PDT 24
Peak memory	289696 kb
Host	smart-c67398ca-3668-4fcd-8b6e-8a396a9cbed9
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514459792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.3514459792
Directory	/workspace/1.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/17.flash_ctrl_re_evict.363430605
Short name	T303
Test name
Test status
Simulation time	76318600 ps
CPU time	32.83 seconds
Started	Jul 23 04:46:00 PM PDT 24
Finished	Jul 23 04:46:34 PM PDT 24
Peak memory	275560 kb
Host	smart-e63b01c0-6b48-4972-875c-6f3a4d51bbaf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363430605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla sh_ctrl_re_evict.363430605
Directory	/workspace/17.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb_redun.701160692
Short name	T71
Test name
Test status
Simulation time	885844500 ps
CPU time	23.84 seconds
Started	Jul 23 04:44:10 PM PDT 24
Finished	Jul 23 04:44:37 PM PDT 24
Peak memory	265336 kb
Host	smart-eb674e40-8fc1-459f-a2a4-67bc21c17cd7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701160692 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.701160692
Directory	/workspace/2.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/2.flash_ctrl_wr_intg.1946396580
Short name	T7
Test name
Test status
Simulation time	81184700 ps
CPU time	14.91 seconds
Started	Jul 23 04:44:10 PM PDT 24
Finished	Jul 23 04:44:29 PM PDT 24
Peak memory	260856 kb
Host	smart-4c894a5e-7a86-4f34-8657-84a4144da303
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946396580 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.1946396580
Directory	/workspace/2.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2809233840
Short name	T330
Test name
Test status
Simulation time	7102536500 ps
CPU time	68.92 seconds
Started	Jul 23 04:39:02 PM PDT 24
Finished	Jul 23 04:40:14 PM PDT 24
Peak memory	261944 kb
Host	smart-2d00ac29-6edf-44fb-a21d-f9055fa79e76
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809233840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_aliasing.2809233840
Directory	/workspace/0.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2661251184
Short name	T1226
Test name
Test status
Simulation time	622028500 ps
CPU time	34.29 seconds
Started	Jul 23 04:39:03 PM PDT 24
Finished	Jul 23 04:39:40 PM PDT 24
Peak memory	261852 kb
Host	smart-59e575b1-6835-4807-afad-8702df778f14
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661251184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_bit_bash.2661251184
Directory	/workspace/0.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3380207749
Short name	T1216
Test name
Test status
Simulation time	30500600 ps
CPU time	30.45 seconds
Started	Jul 23 04:39:00 PM PDT 24
Finished	Jul 23 04:39:32 PM PDT 24
Peak memory	261800 kb
Host	smart-0a539d7c-d3b3-4eac-9935-1824c9c50a52
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380207749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_hw_reset.3380207749
Directory	/workspace/0.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.4172603582
Short name	T286
Test name
Test status
Simulation time	180571200 ps
CPU time	18 seconds
Started	Jul 23 04:39:04 PM PDT 24
Finished	Jul 23 04:39:27 PM PDT 24
Peak memory	279844 kb
Host	smart-09635343-d7cb-4e66-b1dd-e6c15b7a9dee
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172603582 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.4172603582
Directory	/workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1201778142
Short name	T1208
Test name
Test status
Simulation time	56156700 ps
CPU time	14.65 seconds
Started	Jul 23 04:39:05 PM PDT 24
Finished	Jul 23 04:39:21 PM PDT 24
Peak memory	264404 kb
Host	smart-59200de3-9e44-4264-b32d-b29972a55f33
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201778142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_csr_rw.1201778142
Directory	/workspace/0.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3223260235
Short name	T1209
Test name
Test status
Simulation time	30473000 ps
CPU time	14.45 seconds
Started	Jul 23 04:39:02 PM PDT 24
Finished	Jul 23 04:39:19 PM PDT 24
Peak memory	261812 kb
Host	smart-a650a9aa-bbc4-4ca7-a051-cf89f6529622
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223260235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.3 223260235
Directory	/workspace/0.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3652241480
Short name	T261
Test name
Test status
Simulation time	78599900 ps
CPU time	13.51 seconds
Started	Jul 23 04:39:08 PM PDT 24
Finished	Jul 23 04:39:23 PM PDT 24
Peak memory	262620 kb
Host	smart-4421177b-aea7-4bfb-9130-e6413e94df30
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652241480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_mem_partial_access.3652241480
Directory	/workspace/0.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1312620130
Short name	T1187
Test name
Test status
Simulation time	43780500 ps
CPU time	13.5 seconds
Started	Jul 23 04:39:02 PM PDT 24
Finished	Jul 23 04:39:18 PM PDT 24
Peak memory	261728 kb
Host	smart-3f991886-96b8-4b38-aaa5-38000f6f385b
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312620130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me m_walk.1312620130
Directory	/workspace/0.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1795845931
Short name	T323
Test name
Test status
Simulation time	460052800 ps
CPU time	31.52 seconds
Started	Jul 23 04:39:01 PM PDT 24
Finished	Jul 23 04:39:35 PM PDT 24
Peak memory	262000 kb
Host	smart-03c2f2f4-3e78-4260-9998-74cafb6dc107
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795845931 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.1795845931
Directory	/workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3532258424
Short name	T1130
Test name
Test status
Simulation time	17582200 ps
CPU time	15.64 seconds
Started	Jul 23 04:39:02 PM PDT 24
Finished	Jul 23 04:39:20 PM PDT 24
Peak memory	253668 kb
Host	smart-b6dc3b34-d0e5-4e67-85f1-dc166d66c531
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532258424 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.3532258424
Directory	/workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2119594777
Short name	T1206
Test name
Test status
Simulation time	14240700 ps
CPU time	15.92 seconds
Started	Jul 23 04:39:03 PM PDT 24
Finished	Jul 23 04:39:21 PM PDT 24
Peak memory	253516 kb
Host	smart-be71b014-1da7-466d-b02f-e763556b91cd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119594777 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.2119594777
Directory	/workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.197332144
Short name	T382
Test name
Test status
Simulation time	666256600 ps
CPU time	462.07 seconds
Started	Jul 23 04:39:02 PM PDT 24
Finished	Jul 23 04:46:47 PM PDT 24
Peak memory	264388 kb
Host	smart-b44aeac1-e961-4770-bba0-cf6df8f519b2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197332144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ tl_intg_err.197332144
Directory	/workspace/0.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.78995929
Short name	T62
Test name
Test status
Simulation time	228610800 ps
CPU time	31.4 seconds
Started	Jul 23 04:39:09 PM PDT 24
Finished	Jul 23 04:39:42 PM PDT 24
Peak memory	262028 kb
Host	smart-5f3aa8c7-879b-4bb0-b571-17f1a99dcb8d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78995929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_aliasing.78995929
Directory	/workspace/1.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3194647156
Short name	T1154
Test name
Test status
Simulation time	1320622500 ps
CPU time	63.09 seconds
Started	Jul 23 04:39:01 PM PDT 24
Finished	Jul 23 04:40:07 PM PDT 24
Peak memory	261912 kb
Host	smart-a5cc0b56-820e-4823-9fdc-af57e05b0e0b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194647156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_bit_bash.3194647156
Directory	/workspace/1.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3401341650
Short name	T329
Test name
Test status
Simulation time	258048900 ps
CPU time	17.82 seconds
Started	Jul 23 04:39:05 PM PDT 24
Finished	Jul 23 04:39:24 PM PDT 24
Peak memory	278188 kb
Host	smart-2b63a608-00a5-44c4-b42c-a34e8d836457
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401341650 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.3401341650
Directory	/workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1619343114
Short name	T1239
Test name
Test status
Simulation time	104750700 ps
CPU time	14.75 seconds
Started	Jul 23 04:39:04 PM PDT 24
Finished	Jul 23 04:39:21 PM PDT 24
Peak memory	261928 kb
Host	smart-5e9de708-0bc0-422c-95c6-f587215764fa
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619343114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 1.flash_ctrl_csr_rw.1619343114
Directory	/workspace/1.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1082964428
Short name	T1256
Test name
Test status
Simulation time	29427500 ps
CPU time	13.63 seconds
Started	Jul 23 04:39:03 PM PDT 24
Finished	Jul 23 04:39:19 PM PDT 24
Peak memory	261872 kb
Host	smart-79410ba6-0a6d-4cb1-8afe-386490d3e34a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082964428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.1 082964428
Directory	/workspace/1.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3417528102
Short name	T262
Test name
Test status
Simulation time	15946000 ps
CPU time	13.42 seconds
Started	Jul 23 04:39:05 PM PDT 24
Finished	Jul 23 04:39:20 PM PDT 24
Peak memory	262084 kb
Host	smart-a89c2c55-b5fa-43be-b437-81ee183a90e0
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417528102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_mem_partial_access.3417528102
Directory	/workspace/1.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.4204534372
Short name	T1118
Test name
Test status
Simulation time	28626900 ps
CPU time	13.63 seconds
Started	Jul 23 04:39:05 PM PDT 24
Finished	Jul 23 04:39:21 PM PDT 24
Peak memory	261852 kb
Host	smart-813f1a4f-41eb-4d3a-8631-a6966f6ebc8d
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204534372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me m_walk.4204534372
Directory	/workspace/1.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1981006701
Short name	T1143
Test name
Test status
Simulation time	132447300 ps
CPU time	33.32 seconds
Started	Jul 23 04:39:10 PM PDT 24
Finished	Jul 23 04:39:45 PM PDT 24
Peak memory	262068 kb
Host	smart-98d37e58-3ea0-4dcf-9551-9eb0e942e54b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981006701 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.1981006701
Directory	/workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3334435551
Short name	T1140
Test name
Test status
Simulation time	20519900 ps
CPU time	15.54 seconds
Started	Jul 23 04:39:02 PM PDT 24
Finished	Jul 23 04:39:20 PM PDT 24
Peak memory	253548 kb
Host	smart-940bc505-b7c4-427c-ae1e-7c9510e859dd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334435551 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.3334435551
Directory	/workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2373056885
Short name	T1252
Test name
Test status
Simulation time	14873800 ps
CPU time	13.07 seconds
Started	Jul 23 04:39:01 PM PDT 24
Finished	Jul 23 04:39:17 PM PDT 24
Peak memory	253564 kb
Host	smart-6663e093-c6ca-443d-9cda-11a28ef3b197
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373056885 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.2373056885
Directory	/workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3951805901
Short name	T276
Test name
Test status
Simulation time	94963600 ps
CPU time	19.11 seconds
Started	Jul 23 04:39:01 PM PDT 24
Finished	Jul 23 04:39:23 PM PDT 24
Peak memory	264412 kb
Host	smart-82f63581-6e12-4a21-a126-84b3dbe32a14
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951805901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3 951805901
Directory	/workspace/1.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.382675842
Short name	T278
Test name
Test status
Simulation time	1457914600 ps
CPU time	387.42 seconds
Started	Jul 23 04:39:00 PM PDT 24
Finished	Jul 23 04:45:30 PM PDT 24
Peak memory	264516 kb
Host	smart-04ed061d-1a7e-4dba-84e7-5b7763162c4a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382675842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ tl_intg_err.382675842
Directory	/workspace/1.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2168309552
Short name	T220
Test name
Test status
Simulation time	215343500 ps
CPU time	19.31 seconds
Started	Jul 23 04:39:35 PM PDT 24
Finished	Jul 23 04:39:56 PM PDT 24
Peak memory	272648 kb
Host	smart-8e14c8b4-dc5d-4692-954d-30031ee0ead2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168309552 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.2168309552
Directory	/workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3415091137
Short name	T1156
Test name
Test status
Simulation time	87467100 ps
CPU time	16.7 seconds
Started	Jul 23 04:39:36 PM PDT 24
Finished	Jul 23 04:39:54 PM PDT 24
Peak memory	264428 kb
Host	smart-f6c815ba-7fe0-4845-8079-670ba78efd33
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415091137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 10.flash_ctrl_csr_rw.3415091137
Directory	/workspace/10.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.33294773
Short name	T281
Test name
Test status
Simulation time	15658800 ps
CPU time	13.54 seconds
Started	Jul 23 04:39:38 PM PDT 24
Finished	Jul 23 04:39:53 PM PDT 24
Peak memory	261900 kb
Host	smart-7c55b47e-1762-409d-acfc-10432311c6ec
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33294773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.33294773
Directory	/workspace/10.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3929288825
Short name	T1245
Test name
Test status
Simulation time	260704300 ps
CPU time	34.59 seconds
Started	Jul 23 04:39:33 PM PDT 24
Finished	Jul 23 04:40:10 PM PDT 24
Peak memory	262044 kb
Host	smart-265cd462-b47f-4d21-a833-7a6396ef7430
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929288825 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.3929288825
Directory	/workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3992902493
Short name	T1243
Test name
Test status
Simulation time	46592700 ps
CPU time	15.38 seconds
Started	Jul 23 04:39:44 PM PDT 24
Finished	Jul 23 04:40:02 PM PDT 24
Peak memory	253708 kb
Host	smart-554ce3b8-1afe-4793-a37e-87585343aaf0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992902493 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.3992902493
Directory	/workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3442854846
Short name	T1122
Test name
Test status
Simulation time	33951600 ps
CPU time	15.77 seconds
Started	Jul 23 04:39:33 PM PDT 24
Finished	Jul 23 04:39:51 PM PDT 24
Peak memory	253676 kb
Host	smart-cbcc117c-2bb7-4c36-875f-125d8fed6e47
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442854846 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.3442854846
Directory	/workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1880596190
Short name	T1213
Test name
Test status
Simulation time	648304900 ps
CPU time	455.04 seconds
Started	Jul 23 04:39:31 PM PDT 24
Finished	Jul 23 04:47:09 PM PDT 24
Peak memory	264420 kb
Host	smart-bf87d4a7-76e1-484d-8f88-5f8621fb9abf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880596190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr l_tl_intg_err.1880596190
Directory	/workspace/10.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1855149264
Short name	T1183
Test name
Test status
Simulation time	147079900 ps
CPU time	19.42 seconds
Started	Jul 23 04:39:41 PM PDT 24
Finished	Jul 23 04:40:02 PM PDT 24
Peak memory	271880 kb
Host	smart-eb1dd11b-5d6f-4199-98a3-ecbdc68092c9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855149264 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.1855149264
Directory	/workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3323402799
Short name	T1203
Test name
Test status
Simulation time	125812300 ps
CPU time	16.59 seconds
Started	Jul 23 04:39:31 PM PDT 24
Finished	Jul 23 04:39:50 PM PDT 24
Peak memory	264500 kb
Host	smart-05db3839-6254-47ea-8812-922845d0aaf8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323402799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 11.flash_ctrl_csr_rw.3323402799
Directory	/workspace/11.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1102689992
Short name	T353
Test name
Test status
Simulation time	44935400 ps
CPU time	13.32 seconds
Started	Jul 23 04:39:40 PM PDT 24
Finished	Jul 23 04:39:54 PM PDT 24
Peak memory	261872 kb
Host	smart-f4e20c8c-3f7e-427d-ab15-98f796976e5b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102689992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test. 1102689992
Directory	/workspace/11.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2223909521
Short name	T1132
Test name
Test status
Simulation time	626638700 ps
CPU time	33.86 seconds
Started	Jul 23 04:39:43 PM PDT 24
Finished	Jul 23 04:40:19 PM PDT 24
Peak memory	263236 kb
Host	smart-cf5f1644-9c80-45df-8832-2db0d7278b61
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223909521 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.2223909521
Directory	/workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2146534466
Short name	T1124
Test name
Test status
Simulation time	24099900 ps
CPU time	15.75 seconds
Started	Jul 23 04:39:32 PM PDT 24
Finished	Jul 23 04:39:51 PM PDT 24
Peak memory	253672 kb
Host	smart-3c95e6fb-c11b-47a7-a5a1-f5f85f53649f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146534466 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.2146534466
Directory	/workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.864265148
Short name	T1119
Test name
Test status
Simulation time	44580100 ps
CPU time	15.62 seconds
Started	Jul 23 04:39:32 PM PDT 24
Finished	Jul 23 04:39:50 PM PDT 24
Peak memory	253680 kb
Host	smart-87cf197d-106c-4c8a-9b4f-bcd448dc33b6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864265148 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.864265148
Directory	/workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3873869244
Short name	T280
Test name
Test status
Simulation time	221086600 ps
CPU time	20.21 seconds
Started	Jul 23 04:39:35 PM PDT 24
Finished	Jul 23 04:39:56 PM PDT 24
Peak memory	264448 kb
Host	smart-ab260e66-b14e-4320-a98c-9dfbe21a7cb5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873869244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors. 3873869244
Directory	/workspace/11.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3933781160
Short name	T1148
Test name
Test status
Simulation time	87983200 ps
CPU time	19.36 seconds
Started	Jul 23 04:39:32 PM PDT 24
Finished	Jul 23 04:39:54 PM PDT 24
Peak memory	272000 kb
Host	smart-b8983789-f3b4-4c67-ba80-1b1ee46d4ccd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933781160 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.3933781160
Directory	/workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3924160295
Short name	T1158
Test name
Test status
Simulation time	214008900 ps
CPU time	14.66 seconds
Started	Jul 23 04:39:31 PM PDT 24
Finished	Jul 23 04:39:48 PM PDT 24
Peak memory	264436 kb
Host	smart-d604d99c-942e-46b3-ac2c-c6e3fb7d03e4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924160295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 12.flash_ctrl_csr_rw.3924160295
Directory	/workspace/12.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1744327922
Short name	T352
Test name
Test status
Simulation time	91349700 ps
CPU time	13.72 seconds
Started	Jul 23 04:39:42 PM PDT 24
Finished	Jul 23 04:39:58 PM PDT 24
Peak memory	261880 kb
Host	smart-a133c16d-464e-43f5-9630-f1a3e69f2dde
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744327922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test. 1744327922
Directory	/workspace/12.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1008456160
Short name	T1167
Test name
Test status
Simulation time	329943400 ps
CPU time	35.05 seconds
Started	Jul 23 04:39:32 PM PDT 24
Finished	Jul 23 04:40:10 PM PDT 24
Peak memory	263268 kb
Host	smart-f96c9fa5-2e9e-41d9-b0fa-d23b51cca003
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008456160 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.1008456160
Directory	/workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.816809175
Short name	T1234
Test name
Test status
Simulation time	13426900 ps
CPU time	13.38 seconds
Started	Jul 23 04:39:37 PM PDT 24
Finished	Jul 23 04:39:51 PM PDT 24
Peak memory	253648 kb
Host	smart-176a12f2-b232-4ff0-ba09-6a2ca81fe2ad
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816809175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.816809175
Directory	/workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1649946966
Short name	T1230
Test name
Test status
Simulation time	13235000 ps
CPU time	13.25 seconds
Started	Jul 23 04:39:31 PM PDT 24
Finished	Jul 23 04:39:47 PM PDT 24
Peak memory	253684 kb
Host	smart-8bf17f6a-cf2c-4c55-9e14-6f7d3589cf6b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649946966 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.1649946966
Directory	/workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1459314739
Short name	T1238
Test name
Test status
Simulation time	30566300 ps
CPU time	16.06 seconds
Started	Jul 23 04:39:31 PM PDT 24
Finished	Jul 23 04:39:50 PM PDT 24
Peak memory	264532 kb
Host	smart-5448f8ee-b2dc-435f-b6a4-31af0ba39862
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459314739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors. 1459314739
Directory	/workspace/12.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3009889141
Short name	T1192
Test name
Test status
Simulation time	119417300 ps
CPU time	19.19 seconds
Started	Jul 23 04:39:42 PM PDT 24
Finished	Jul 23 04:40:03 PM PDT 24
Peak memory	272560 kb
Host	smart-51bb3173-40be-4949-ad5a-1150380c32e3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009889141 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.3009889141
Directory	/workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.818359867
Short name	T1191
Test name
Test status
Simulation time	134170400 ps
CPU time	16.93 seconds
Started	Jul 23 04:39:42 PM PDT 24
Finished	Jul 23 04:40:00 PM PDT 24
Peak memory	261844 kb
Host	smart-49a624a7-3edc-49ba-9dfd-f9e899a01e1c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818359867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.flash_ctrl_csr_rw.818359867
Directory	/workspace/13.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2141048478
Short name	T1180
Test name
Test status
Simulation time	24152300 ps
CPU time	13.62 seconds
Started	Jul 23 04:39:45 PM PDT 24
Finished	Jul 23 04:40:01 PM PDT 24
Peak memory	261744 kb
Host	smart-62dda7f2-0c98-484b-9e1e-45811f50989c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141048478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test. 2141048478
Directory	/workspace/13.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1836577738
Short name	T60
Test name
Test status
Simulation time	213460700 ps
CPU time	29.76 seconds
Started	Jul 23 04:39:43 PM PDT 24
Finished	Jul 23 04:40:16 PM PDT 24
Peak memory	262080 kb
Host	smart-5610f2ec-f645-4447-a82d-7480b691abca
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836577738 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.1836577738
Directory	/workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3320629245
Short name	T1138
Test name
Test status
Simulation time	43203900 ps
CPU time	16.16 seconds
Started	Jul 23 04:39:42 PM PDT 24
Finished	Jul 23 04:40:00 PM PDT 24
Peak memory	253704 kb
Host	smart-b772f4df-949f-4d3f-a37e-eea36821e62e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320629245 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.3320629245
Directory	/workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1446493724
Short name	T1169
Test name
Test status
Simulation time	20846800 ps
CPU time	15.89 seconds
Started	Jul 23 04:39:46 PM PDT 24
Finished	Jul 23 04:40:04 PM PDT 24
Peak memory	253600 kb
Host	smart-3b81f11e-18c6-474d-83cd-29270ddd6434
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446493724 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.1446493724
Directory	/workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2190498673
Short name	T285
Test name
Test status
Simulation time	89783600 ps
CPU time	18.69 seconds
Started	Jul 23 04:39:33 PM PDT 24
Finished	Jul 23 04:39:54 PM PDT 24
Peak memory	264424 kb
Host	smart-4f58ec08-2b22-406e-b784-e45588d98ea8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190498673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors. 2190498673
Directory	/workspace/13.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.4027293480
Short name	T1193
Test name
Test status
Simulation time	47005700 ps
CPU time	17.38 seconds
Started	Jul 23 04:39:47 PM PDT 24
Finished	Jul 23 04:40:06 PM PDT 24
Peak memory	264384 kb
Host	smart-a0f25839-60b6-4798-9520-a3fb11ecafea
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027293480 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.4027293480
Directory	/workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2749132727
Short name	T324
Test name
Test status
Simulation time	149434200 ps
CPU time	16.45 seconds
Started	Jul 23 04:39:45 PM PDT 24
Finished	Jul 23 04:40:04 PM PDT 24
Peak memory	264440 kb
Host	smart-4a85abd4-2bde-4900-b0dc-2c24a81693d7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749132727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 14.flash_ctrl_csr_rw.2749132727
Directory	/workspace/14.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.927320413
Short name	T1248
Test name
Test status
Simulation time	18448500 ps
CPU time	13.65 seconds
Started	Jul 23 04:39:42 PM PDT 24
Finished	Jul 23 04:39:58 PM PDT 24
Peak memory	261972 kb
Host	smart-c98fd90d-e347-4bc4-a2d3-f27941df6e87
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927320413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.927320413
Directory	/workspace/14.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2737463678
Short name	T1125
Test name
Test status
Simulation time	167622800 ps
CPU time	35.7 seconds
Started	Jul 23 04:39:43 PM PDT 24
Finished	Jul 23 04:40:22 PM PDT 24
Peak memory	263608 kb
Host	smart-ec7d72e3-cf7c-4ce2-a7e9-4614b2929b1d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737463678 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.2737463678
Directory	/workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3887634485
Short name	T1207
Test name
Test status
Simulation time	38343400 ps
CPU time	15.7 seconds
Started	Jul 23 04:39:48 PM PDT 24
Finished	Jul 23 04:40:05 PM PDT 24
Peak memory	253724 kb
Host	smart-25d36569-7f0e-4c77-bffa-428a7515912c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887634485 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.3887634485
Directory	/workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3607925219
Short name	T1212
Test name
Test status
Simulation time	24355700 ps
CPU time	15.84 seconds
Started	Jul 23 04:39:46 PM PDT 24
Finished	Jul 23 04:40:04 PM PDT 24
Peak memory	253668 kb
Host	smart-77fc06a9-37cb-4b8d-80c4-b0d254e4c944
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607925219 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.3607925219
Directory	/workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1129706475
Short name	T287
Test name
Test status
Simulation time	191685500 ps
CPU time	18.79 seconds
Started	Jul 23 04:39:43 PM PDT 24
Finished	Jul 23 04:40:04 PM PDT 24
Peak memory	264516 kb
Host	smart-6ab1185c-5e73-4163-8024-7cb58abbc456
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129706475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors. 1129706475
Directory	/workspace/14.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.326887027
Short name	T383
Test name
Test status
Simulation time	1375435500 ps
CPU time	393.11 seconds
Started	Jul 23 04:39:43 PM PDT 24
Finished	Jul 23 04:46:19 PM PDT 24
Peak memory	264436 kb
Host	smart-08e9fd04-c8e6-4d24-bf02-a977c8c0da6b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326887027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl _tl_intg_err.326887027
Directory	/workspace/14.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2613600627
Short name	T254
Test name
Test status
Simulation time	341917900 ps
CPU time	18.57 seconds
Started	Jul 23 04:39:46 PM PDT 24
Finished	Jul 23 04:40:07 PM PDT 24
Peak memory	272056 kb
Host	smart-1160e4fb-4e62-436c-9c25-3b939b342ca1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613600627 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.2613600627
Directory	/workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3281643283
Short name	T1251
Test name
Test status
Simulation time	465880100 ps
CPU time	17.93 seconds
Started	Jul 23 04:39:42 PM PDT 24
Finished	Jul 23 04:40:01 PM PDT 24
Peak memory	261952 kb
Host	smart-8f0bcd0d-5bbd-4b0a-b2a4-dcfd1a4bca0e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281643283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 15.flash_ctrl_csr_rw.3281643283
Directory	/workspace/15.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2204061177
Short name	T1155
Test name
Test status
Simulation time	16136800 ps
CPU time	14.5 seconds
Started	Jul 23 04:39:50 PM PDT 24
Finished	Jul 23 04:40:05 PM PDT 24
Peak memory	261732 kb
Host	smart-bdea2dbf-4e43-49df-8b26-6fb4aede1907
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204061177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test. 2204061177
Directory	/workspace/15.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.619210667
Short name	T1190
Test name
Test status
Simulation time	1473950400 ps
CPU time	36.61 seconds
Started	Jul 23 04:39:42 PM PDT 24
Finished	Jul 23 04:40:21 PM PDT 24
Peak memory	263188 kb
Host	smart-c5249512-715d-4b98-97de-6fc7ff876f00
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619210667 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.619210667
Directory	/workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.210365058
Short name	T1223
Test name
Test status
Simulation time	14866100 ps
CPU time	16.15 seconds
Started	Jul 23 04:39:43 PM PDT 24
Finished	Jul 23 04:40:01 PM PDT 24
Peak memory	253756 kb
Host	smart-49ef26f9-e7c2-4517-8e2d-c35bd174db2f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210365058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.210365058
Directory	/workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3704412225
Short name	T1204
Test name
Test status
Simulation time	58725200 ps
CPU time	16.47 seconds
Started	Jul 23 04:39:41 PM PDT 24
Finished	Jul 23 04:39:59 PM PDT 24
Peak memory	253776 kb
Host	smart-881c4d7b-c39e-410d-ac31-8f7e82fd66ca
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704412225 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.3704412225
Directory	/workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.279836500
Short name	T293
Test name
Test status
Simulation time	58956700 ps
CPU time	20.39 seconds
Started	Jul 23 04:39:42 PM PDT 24
Finished	Jul 23 04:40:04 PM PDT 24
Peak memory	264500 kb
Host	smart-2fc6c845-3ea6-4366-8c39-b778b557a63f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279836500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.279836500
Directory	/workspace/15.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.756937545
Short name	T380
Test name
Test status
Simulation time	1686296800 ps
CPU time	457.11 seconds
Started	Jul 23 04:39:43 PM PDT 24
Finished	Jul 23 04:47:22 PM PDT 24
Peak memory	264412 kb
Host	smart-d83c00ec-28d6-440a-9da1-8b2ab565309d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756937545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl _tl_intg_err.756937545
Directory	/workspace/15.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2339058235
Short name	T1134
Test name
Test status
Simulation time	25082400 ps
CPU time	17.48 seconds
Started	Jul 23 04:39:47 PM PDT 24
Finished	Jul 23 04:40:06 PM PDT 24
Peak memory	277964 kb
Host	smart-342bf0ff-ef74-4bd8-b757-72e545a18726
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339058235 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.2339058235
Directory	/workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1569912350
Short name	T1202
Test name
Test status
Simulation time	148358200 ps
CPU time	16.75 seconds
Started	Jul 23 04:39:46 PM PDT 24
Finished	Jul 23 04:40:05 PM PDT 24
Peak memory	263244 kb
Host	smart-846bc1df-7e4c-4213-bc10-f944338e05c0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569912350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 16.flash_ctrl_csr_rw.1569912350
Directory	/workspace/16.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2459150107
Short name	T1159
Test name
Test status
Simulation time	30504700 ps
CPU time	14.51 seconds
Started	Jul 23 04:39:42 PM PDT 24
Finished	Jul 23 04:39:58 PM PDT 24
Peak memory	261760 kb
Host	smart-720c675f-e738-42cb-a779-8911196214ed
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459150107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test. 2459150107
Directory	/workspace/16.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2394863605
Short name	T1182
Test name
Test status
Simulation time	300737800 ps
CPU time	34.64 seconds
Started	Jul 23 04:39:44 PM PDT 24
Finished	Jul 23 04:40:21 PM PDT 24
Peak memory	263524 kb
Host	smart-6afe415f-aaba-4f0b-a793-8d3ef61e3492
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394863605 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.2394863605
Directory	/workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.260007544
Short name	T1237
Test name
Test status
Simulation time	14737200 ps
CPU time	16.17 seconds
Started	Jul 23 04:39:43 PM PDT 24
Finished	Jul 23 04:40:01 PM PDT 24
Peak memory	253824 kb
Host	smart-6f4c4957-bbe6-4632-bbb2-316f2c7dc2b2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260007544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.260007544
Directory	/workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1720938714
Short name	T1184
Test name
Test status
Simulation time	21152800 ps
CPU time	13.93 seconds
Started	Jul 23 04:39:50 PM PDT 24
Finished	Jul 23 04:40:04 PM PDT 24
Peak memory	253664 kb
Host	smart-6c5c54b0-6558-4bba-95e6-53e0562e8a9a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720938714 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.1720938714
Directory	/workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2864953868
Short name	T255
Test name
Test status
Simulation time	344585500 ps
CPU time	902.91 seconds
Started	Jul 23 04:39:43 PM PDT 24
Finished	Jul 23 04:54:49 PM PDT 24
Peak memory	264440 kb
Host	smart-405d0dca-cf77-48ee-980c-6d02fec6ee90
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864953868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr l_tl_intg_err.2864953868
Directory	/workspace/16.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3061636024
Short name	T1231
Test name
Test status
Simulation time	185798600 ps
CPU time	15.12 seconds
Started	Jul 23 04:39:46 PM PDT 24
Finished	Jul 23 04:40:03 PM PDT 24
Peak memory	272576 kb
Host	smart-303f06d1-07d7-444f-8b81-efc06719fd1e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061636024 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.3061636024
Directory	/workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1689956478
Short name	T1168
Test name
Test status
Simulation time	178484400 ps
CPU time	18.27 seconds
Started	Jul 23 04:39:45 PM PDT 24
Finished	Jul 23 04:40:06 PM PDT 24
Peak memory	264404 kb
Host	smart-7bda65a1-4617-49bd-badb-953fe0457632
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689956478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 17.flash_ctrl_csr_rw.1689956478
Directory	/workspace/17.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.182810366
Short name	T1142
Test name
Test status
Simulation time	25565400 ps
CPU time	13.67 seconds
Started	Jul 23 04:39:44 PM PDT 24
Finished	Jul 23 04:40:00 PM PDT 24
Peak memory	261892 kb
Host	smart-a5d1edcb-0de3-4bb3-ad24-efa69cfdd01f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182810366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.182810366
Directory	/workspace/17.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.569779025
Short name	T331
Test name
Test status
Simulation time	827924300 ps
CPU time	20.81 seconds
Started	Jul 23 04:39:44 PM PDT 24
Finished	Jul 23 04:40:08 PM PDT 24
Peak memory	263208 kb
Host	smart-dea61cad-f4ba-4ec3-93c2-ae4a0d122ccb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569779025 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.569779025
Directory	/workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1728579810
Short name	T1163
Test name
Test status
Simulation time	41336800 ps
CPU time	13.79 seconds
Started	Jul 23 04:39:52 PM PDT 24
Finished	Jul 23 04:40:07 PM PDT 24
Peak memory	253552 kb
Host	smart-856d10f0-9878-404b-b9f2-fd8dd9badc85
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728579810 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.1728579810
Directory	/workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.4101392776
Short name	T1244
Test name
Test status
Simulation time	18614400 ps
CPU time	15.44 seconds
Started	Jul 23 04:39:42 PM PDT 24
Finished	Jul 23 04:39:59 PM PDT 24
Peak memory	253780 kb
Host	smart-cf147b74-4a38-4633-bfac-a2fc8dcfc08c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101392776 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.4101392776
Directory	/workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1404017156
Short name	T296
Test name
Test status
Simulation time	348127600 ps
CPU time	19.47 seconds
Started	Jul 23 04:39:45 PM PDT 24
Finished	Jul 23 04:40:07 PM PDT 24
Peak memory	263568 kb
Host	smart-8e75d071-1486-4270-afbc-01e813d355fb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404017156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors. 1404017156
Directory	/workspace/17.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3909163805
Short name	T1196
Test name
Test status
Simulation time	253440100 ps
CPU time	17.73 seconds
Started	Jul 23 04:39:44 PM PDT 24
Finished	Jul 23 04:40:04 PM PDT 24
Peak memory	277492 kb
Host	smart-aadccdc6-00c5-49c8-9805-81016c73cbd3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909163805 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.3909163805
Directory	/workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4232271256
Short name	T1170
Test name
Test status
Simulation time	72639600 ps
CPU time	16.37 seconds
Started	Jul 23 04:39:46 PM PDT 24
Finished	Jul 23 04:40:04 PM PDT 24
Peak memory	261932 kb
Host	smart-b4a0e2c6-9101-48e7-8f99-0df3ab471d33
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232271256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 18.flash_ctrl_csr_rw.4232271256
Directory	/workspace/18.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3447138224
Short name	T1217
Test name
Test status
Simulation time	24424700 ps
CPU time	14.18 seconds
Started	Jul 23 04:39:44 PM PDT 24
Finished	Jul 23 04:40:01 PM PDT 24
Peak memory	261704 kb
Host	smart-8e0ba7f6-d7e8-49ee-885c-34d5b6737adf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447138224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test. 3447138224
Directory	/workspace/18.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2770129458
Short name	T1242
Test name
Test status
Simulation time	331787200 ps
CPU time	15.43 seconds
Started	Jul 23 04:39:42 PM PDT 24
Finished	Jul 23 04:40:00 PM PDT 24
Peak memory	262192 kb
Host	smart-4aa178da-e448-4984-bda4-38b8da257680
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770129458 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.2770129458
Directory	/workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1923449495
Short name	T1221
Test name
Test status
Simulation time	41215100 ps
CPU time	15.86 seconds
Started	Jul 23 04:39:43 PM PDT 24
Finished	Jul 23 04:40:02 PM PDT 24
Peak memory	253672 kb
Host	smart-52b2c089-08c5-4919-903f-6e67527c1a3b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923449495 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.1923449495
Directory	/workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.313626566
Short name	T1240
Test name
Test status
Simulation time	13143400 ps
CPU time	13.05 seconds
Started	Jul 23 04:39:46 PM PDT 24
Finished	Jul 23 04:40:01 PM PDT 24
Peak memory	253428 kb
Host	smart-53249fbc-40c6-4c00-b4ad-f8e0a893fc23
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313626566 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.313626566
Directory	/workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.51153039
Short name	T222
Test name
Test status
Simulation time	210300600 ps
CPU time	19.51 seconds
Started	Jul 23 04:39:47 PM PDT 24
Finished	Jul 23 04:40:08 PM PDT 24
Peak memory	264540 kb
Host	smart-53687fe4-49dc-4a52-af33-1111390c387a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51153039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.51153039
Directory	/workspace/18.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3951378562
Short name	T375
Test name
Test status
Simulation time	813396000 ps
CPU time	902.4 seconds
Started	Jul 23 04:39:45 PM PDT 24
Finished	Jul 23 04:54:50 PM PDT 24
Peak memory	264476 kb
Host	smart-368a2236-7998-44f8-a92f-3add457b43a0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951378562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr l_tl_intg_err.3951378562
Directory	/workspace/18.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.4026333110
Short name	T327
Test name
Test status
Simulation time	210410200 ps
CPU time	17.11 seconds
Started	Jul 23 04:39:57 PM PDT 24
Finished	Jul 23 04:40:17 PM PDT 24
Peak memory	275988 kb
Host	smart-87b6f011-f60d-47b5-b4e9-d74d9c0d491a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026333110 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.4026333110
Directory	/workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3623127710
Short name	T1164
Test name
Test status
Simulation time	67764700 ps
CPU time	16.35 seconds
Started	Jul 23 04:39:57 PM PDT 24
Finished	Jul 23 04:40:17 PM PDT 24
Peak memory	264432 kb
Host	smart-bdcb801d-717c-42e4-807f-cdf35ed07d87
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623127710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 19.flash_ctrl_csr_rw.3623127710
Directory	/workspace/19.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.340779274
Short name	T325
Test name
Test status
Simulation time	572649300 ps
CPU time	19.09 seconds
Started	Jul 23 04:39:57 PM PDT 24
Finished	Jul 23 04:40:19 PM PDT 24
Peak memory	264316 kb
Host	smart-944f7de5-60bf-499a-8df3-a2e8824a2671
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340779274 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.340779274
Directory	/workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2623995874
Short name	T1175
Test name
Test status
Simulation time	10988900 ps
CPU time	15.78 seconds
Started	Jul 23 04:40:03 PM PDT 24
Finished	Jul 23 04:40:20 PM PDT 24
Peak memory	253664 kb
Host	smart-3faa5429-2c74-4d1c-b5da-abea0035f38e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623995874 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.2623995874
Directory	/workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3967341380
Short name	T1165
Test name
Test status
Simulation time	13851900 ps
CPU time	15.81 seconds
Started	Jul 23 04:40:01 PM PDT 24
Finished	Jul 23 04:40:19 PM PDT 24
Peak memory	253548 kb
Host	smart-1d7ef148-cd3e-406b-9ab2-7e178def49e8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967341380 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.3967341380
Directory	/workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1889074756
Short name	T1177
Test name
Test status
Simulation time	29117800 ps
CPU time	16.23 seconds
Started	Jul 23 04:39:54 PM PDT 24
Finished	Jul 23 04:40:11 PM PDT 24
Peak memory	264416 kb
Host	smart-aa163b15-7c70-44ef-a210-461c28c07b81
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889074756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors. 1889074756
Directory	/workspace/19.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2757498417
Short name	T1255
Test name
Test status
Simulation time	2001580900 ps
CPU time	35.14 seconds
Started	Jul 23 04:39:10 PM PDT 24
Finished	Jul 23 04:39:46 PM PDT 24
Peak memory	261972 kb
Host	smart-227c5b7e-25e7-446f-a4b5-447daa05c06c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757498417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_aliasing.2757498417
Directory	/workspace/2.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.313609380
Short name	T1135
Test name
Test status
Simulation time	332944000 ps
CPU time	38.29 seconds
Started	Jul 23 04:39:10 PM PDT 24
Finished	Jul 23 04:39:49 PM PDT 24
Peak memory	262028 kb
Host	smart-3626320e-d4bf-4ccc-aad1-81741ef03904
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313609380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.flash_ctrl_csr_bit_bash.313609380
Directory	/workspace/2.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.803869442
Short name	T1173
Test name
Test status
Simulation time	46034900 ps
CPU time	46.2 seconds
Started	Jul 23 04:39:10 PM PDT 24
Finished	Jul 23 04:39:57 PM PDT 24
Peak memory	264004 kb
Host	smart-755e14ee-9b8b-4e1a-b25a-aa49e08c94e3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803869442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.flash_ctrl_csr_hw_reset.803869442
Directory	/workspace/2.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2291458957
Short name	T103
Test name
Test status
Simulation time	41169200 ps
CPU time	19.73 seconds
Started	Jul 23 04:39:03 PM PDT 24
Finished	Jul 23 04:39:25 PM PDT 24
Peak memory	272808 kb
Host	smart-6a20d4fe-d8b2-48a6-a38a-062885cefba1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291458957 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.2291458957
Directory	/workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3204849044
Short name	T1247
Test name
Test status
Simulation time	56018800 ps
CPU time	16.02 seconds
Started	Jul 23 04:39:10 PM PDT 24
Finished	Jul 23 04:39:27 PM PDT 24
Peak memory	261812 kb
Host	smart-20af2c7b-ee9a-4d1a-8a09-96db40fd3954
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204849044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 2.flash_ctrl_csr_rw.3204849044
Directory	/workspace/2.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.194405241
Short name	T351
Test name
Test status
Simulation time	26162700 ps
CPU time	13.42 seconds
Started	Jul 23 04:39:06 PM PDT 24
Finished	Jul 23 04:39:21 PM PDT 24
Peak memory	261864 kb
Host	smart-a0a54681-9de2-4bdc-8aa9-b37c96640006
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194405241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.194405241
Directory	/workspace/2.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1934411768
Short name	T260
Test name
Test status
Simulation time	25528100 ps
CPU time	13.43 seconds
Started	Jul 23 04:39:05 PM PDT 24
Finished	Jul 23 04:39:20 PM PDT 24
Peak memory	261900 kb
Host	smart-43bdb996-2957-49d3-9888-c201a76c0e66
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934411768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_mem_partial_access.1934411768
Directory	/workspace/2.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3287319268
Short name	T1224
Test name
Test status
Simulation time	16035000 ps
CPU time	13.95 seconds
Started	Jul 23 04:39:09 PM PDT 24
Finished	Jul 23 04:39:24 PM PDT 24
Peak memory	261732 kb
Host	smart-67b77faa-f744-4ef9-b9e8-11e1e2ea1d6b
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287319268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me m_walk.3287319268
Directory	/workspace/2.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2431548822
Short name	T1249
Test name
Test status
Simulation time	415252600 ps
CPU time	35.61 seconds
Started	Jul 23 04:39:02 PM PDT 24
Finished	Jul 23 04:39:40 PM PDT 24
Peak memory	263296 kb
Host	smart-0e1ba0ab-99f7-439e-a7e8-18af2dce0f7f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431548822 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.2431548822
Directory	/workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1449807039
Short name	T1179
Test name
Test status
Simulation time	56129900 ps
CPU time	15.67 seconds
Started	Jul 23 04:39:06 PM PDT 24
Finished	Jul 23 04:39:23 PM PDT 24
Peak memory	253676 kb
Host	smart-1eda67be-ad06-477c-ae57-da84b9680a78
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449807039 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.1449807039
Directory	/workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2652524746
Short name	T1136
Test name
Test status
Simulation time	41837500 ps
CPU time	15.96 seconds
Started	Jul 23 04:39:02 PM PDT 24
Finished	Jul 23 04:39:20 PM PDT 24
Peak memory	253560 kb
Host	smart-5ff8b9de-7e72-4ad4-aab4-896f2bb45833
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652524746 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.2652524746
Directory	/workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2951609055
Short name	T294
Test name
Test status
Simulation time	234577500 ps
CPU time	20.58 seconds
Started	Jul 23 04:39:07 PM PDT 24
Finished	Jul 23 04:39:28 PM PDT 24
Peak memory	264424 kb
Host	smart-7b84e8c8-302e-47b5-9966-89d9a5e69a59
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951609055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.2 951609055
Directory	/workspace/2.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1533755171
Short name	T378
Test name
Test status
Simulation time	1273247700 ps
CPU time	898.64 seconds
Started	Jul 23 04:39:06 PM PDT 24
Finished	Jul 23 04:54:06 PM PDT 24
Peak memory	264400 kb
Host	smart-0be01477-32df-437c-b823-edad4a97a29f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533755171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl _tl_intg_err.1533755171
Directory	/workspace/2.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1973837874
Short name	T1205
Test name
Test status
Simulation time	29404500 ps
CPU time	14.28 seconds
Started	Jul 23 04:39:58 PM PDT 24
Finished	Jul 23 04:40:15 PM PDT 24
Peak memory	261824 kb
Host	smart-c072ac18-c61e-4a5c-abc0-9d8397c1958d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973837874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test. 1973837874
Directory	/workspace/20.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3585644801
Short name	T1181
Test name
Test status
Simulation time	15182000 ps
CPU time	13.32 seconds
Started	Jul 23 04:39:58 PM PDT 24
Finished	Jul 23 04:40:14 PM PDT 24
Peak memory	261916 kb
Host	smart-3409d52d-c9e6-4fd2-88ad-77b1f95a76c9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585644801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test. 3585644801
Directory	/workspace/21.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3118082290
Short name	T1194
Test name
Test status
Simulation time	14770500 ps
CPU time	14.4 seconds
Started	Jul 23 04:39:59 PM PDT 24
Finished	Jul 23 04:40:16 PM PDT 24
Peak memory	261636 kb
Host	smart-2e9822f0-2496-4e9a-b902-40c0ea77e15b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118082290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test. 3118082290
Directory	/workspace/22.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.4035590249
Short name	T1149
Test name
Test status
Simulation time	82145400 ps
CPU time	13.59 seconds
Started	Jul 23 04:39:57 PM PDT 24
Finished	Jul 23 04:40:14 PM PDT 24
Peak memory	261820 kb
Host	smart-471ae339-2e5e-4105-997e-383f4846d252
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035590249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test. 4035590249
Directory	/workspace/23.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3456610512
Short name	T1232
Test name
Test status
Simulation time	55280100 ps
CPU time	13.55 seconds
Started	Jul 23 04:39:58 PM PDT 24
Finished	Jul 23 04:40:14 PM PDT 24
Peak memory	261824 kb
Host	smart-98df1f47-21ba-44d1-a31b-ea16b018a47f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456610512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test. 3456610512
Directory	/workspace/24.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2424441799
Short name	T1210
Test name
Test status
Simulation time	27815700 ps
CPU time	13.92 seconds
Started	Jul 23 04:39:56 PM PDT 24
Finished	Jul 23 04:40:12 PM PDT 24
Peak memory	261760 kb
Host	smart-18017a1c-ba2d-425e-aca6-41590ea59f03
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424441799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test. 2424441799
Directory	/workspace/25.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.4225990044
Short name	T1198
Test name
Test status
Simulation time	25494400 ps
CPU time	14.14 seconds
Started	Jul 23 04:39:58 PM PDT 24
Finished	Jul 23 04:40:15 PM PDT 24
Peak memory	261812 kb
Host	smart-8d41ef7b-79f3-450b-a3d2-9d1f8a50f893
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225990044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test. 4225990044
Directory	/workspace/27.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2198704090
Short name	T1157
Test name
Test status
Simulation time	96065100 ps
CPU time	13.5 seconds
Started	Jul 23 04:40:00 PM PDT 24
Finished	Jul 23 04:40:16 PM PDT 24
Peak memory	261884 kb
Host	smart-4931868a-bc19-4636-90b7-77bc07e3e368
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198704090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test. 2198704090
Directory	/workspace/28.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.872677838
Short name	T1176
Test name
Test status
Simulation time	35549200 ps
CPU time	13.49 seconds
Started	Jul 23 04:39:59 PM PDT 24
Finished	Jul 23 04:40:16 PM PDT 24
Peak memory	261908 kb
Host	smart-400ca4be-7760-4a66-bb29-d32de19959a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872677838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.872677838
Directory	/workspace/29.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3540417456
Short name	T1201
Test name
Test status
Simulation time	214622500 ps
CPU time	34.87 seconds
Started	Jul 23 04:39:28 PM PDT 24
Finished	Jul 23 04:40:05 PM PDT 24
Peak memory	261892 kb
Host	smart-91b040fa-f256-4e06-be4e-22cee88badea
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540417456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_aliasing.3540417456
Directory	/workspace/3.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.323646791
Short name	T1166
Test name
Test status
Simulation time	1331792600 ps
CPU time	39.77 seconds
Started	Jul 23 04:39:28 PM PDT 24
Finished	Jul 23 04:40:10 PM PDT 24
Peak memory	261988 kb
Host	smart-c77b8dcb-22df-44ef-9094-35c00e196b02
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323646791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.flash_ctrl_csr_bit_bash.323646791
Directory	/workspace/3.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2379355786
Short name	T1246
Test name
Test status
Simulation time	159398700 ps
CPU time	45.42 seconds
Started	Jul 23 04:39:18 PM PDT 24
Finished	Jul 23 04:40:06 PM PDT 24
Peak memory	262020 kb
Host	smart-7853b916-2515-4a0c-8c47-f303089f9cd4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379355786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_hw_reset.2379355786
Directory	/workspace/3.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.4271446695
Short name	T1131
Test name
Test status
Simulation time	266157700 ps
CPU time	16.76 seconds
Started	Jul 23 04:39:28 PM PDT 24
Finished	Jul 23 04:39:47 PM PDT 24
Peak memory	276832 kb
Host	smart-f0c141b7-53f0-4240-afe5-56e95dfc7b81
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271446695 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.4271446695
Directory	/workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.107369704
Short name	T1127
Test name
Test status
Simulation time	19982600 ps
CPU time	16.53 seconds
Started	Jul 23 04:39:29 PM PDT 24
Finished	Jul 23 04:39:48 PM PDT 24
Peak memory	264516 kb
Host	smart-46a923ef-f7c8-4d95-a25a-36eeb574f709
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107369704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.flash_ctrl_csr_rw.107369704
Directory	/workspace/3.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.473356829
Short name	T1178
Test name
Test status
Simulation time	16123500 ps
CPU time	13.38 seconds
Started	Jul 23 04:39:25 PM PDT 24
Finished	Jul 23 04:39:40 PM PDT 24
Peak memory	261808 kb
Host	smart-4b93fc14-f321-4035-bc56-f75e44254ae1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473356829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.473356829
Directory	/workspace/3.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2133580296
Short name	T1128
Test name
Test status
Simulation time	23555800 ps
CPU time	13.55 seconds
Started	Jul 23 04:39:19 PM PDT 24
Finished	Jul 23 04:39:34 PM PDT 24
Peak memory	261692 kb
Host	smart-78022b89-7427-4957-b1d5-b16f84b99d55
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133580296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me m_walk.2133580296
Directory	/workspace/3.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2433870539
Short name	T321
Test name
Test status
Simulation time	399295400 ps
CPU time	18.03 seconds
Started	Jul 23 04:39:17 PM PDT 24
Finished	Jul 23 04:39:36 PM PDT 24
Peak memory	263308 kb
Host	smart-bf60c6bd-9f68-4048-a99b-bd046e46a412
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433870539 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.2433870539
Directory	/workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.267099717
Short name	T1211
Test name
Test status
Simulation time	11282700 ps
CPU time	15.58 seconds
Started	Jul 23 04:39:29 PM PDT 24
Finished	Jul 23 04:39:46 PM PDT 24
Peak memory	253684 kb
Host	smart-e782064c-4688-445b-9822-d393d018cf22
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267099717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.267099717
Directory	/workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2218596337
Short name	T1236
Test name
Test status
Simulation time	43545000 ps
CPU time	13.13 seconds
Started	Jul 23 04:39:31 PM PDT 24
Finished	Jul 23 04:39:47 PM PDT 24
Peak memory	253640 kb
Host	smart-d4f4e69c-4103-4980-a666-79efe0a9b9ab
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218596337 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.2218596337
Directory	/workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.4097478926
Short name	T377
Test name
Test status
Simulation time	343097800 ps
CPU time	459.81 seconds
Started	Jul 23 04:39:18 PM PDT 24
Finished	Jul 23 04:46:59 PM PDT 24
Peak memory	264484 kb
Host	smart-f2b76f81-f0ec-498d-a673-79e687a93340
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097478926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl _tl_intg_err.4097478926
Directory	/workspace/3.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2433762000
Short name	T1147
Test name
Test status
Simulation time	32049900 ps
CPU time	13.3 seconds
Started	Jul 23 04:39:58 PM PDT 24
Finished	Jul 23 04:40:14 PM PDT 24
Peak memory	261884 kb
Host	smart-4abffe1e-dd0b-42c6-8f3b-70ac6e8bcc8b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433762000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test. 2433762000
Directory	/workspace/30.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1004917488
Short name	T1229
Test name
Test status
Simulation time	17326300 ps
CPU time	14.28 seconds
Started	Jul 23 04:39:56 PM PDT 24
Finished	Jul 23 04:40:12 PM PDT 24
Peak memory	261988 kb
Host	smart-bfdbdd44-a54b-448f-ab2d-beaddce4be54
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004917488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test. 1004917488
Directory	/workspace/31.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.4160279242
Short name	T1241
Test name
Test status
Simulation time	57540100 ps
CPU time	13.44 seconds
Started	Jul 23 04:39:57 PM PDT 24
Finished	Jul 23 04:40:12 PM PDT 24
Peak memory	261824 kb
Host	smart-5c44d04a-f801-454c-a36d-da9a653aef36
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160279242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test. 4160279242
Directory	/workspace/32.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.752145225
Short name	T1137
Test name
Test status
Simulation time	55573000 ps
CPU time	14.31 seconds
Started	Jul 23 04:39:55 PM PDT 24
Finished	Jul 23 04:40:10 PM PDT 24
Peak memory	261944 kb
Host	smart-de71ad66-d97e-437d-851c-5fb335da81e6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752145225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.752145225
Directory	/workspace/33.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.599643305
Short name	T1151
Test name
Test status
Simulation time	15369800 ps
CPU time	13.49 seconds
Started	Jul 23 04:40:03 PM PDT 24
Finished	Jul 23 04:40:18 PM PDT 24
Peak memory	261856 kb
Host	smart-0c519594-bf76-46a2-95fa-43c1e0d509b8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599643305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.599643305
Directory	/workspace/34.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3605653001
Short name	T1146
Test name
Test status
Simulation time	29531400 ps
CPU time	13.75 seconds
Started	Jul 23 04:39:58 PM PDT 24
Finished	Jul 23 04:40:15 PM PDT 24
Peak memory	261700 kb
Host	smart-6a731d3c-f557-4d6c-b32c-fe8220f1d639
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605653001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test. 3605653001
Directory	/workspace/36.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2455259359
Short name	T371
Test name
Test status
Simulation time	18812000 ps
CPU time	13.26 seconds
Started	Jul 23 04:39:57 PM PDT 24
Finished	Jul 23 04:40:13 PM PDT 24
Peak memory	261764 kb
Host	smart-b5bc591d-c4b1-4998-9c88-77d67f606c3d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455259359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test. 2455259359
Directory	/workspace/37.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1229979684
Short name	T1172
Test name
Test status
Simulation time	28229200 ps
CPU time	14.19 seconds
Started	Jul 23 04:39:57 PM PDT 24
Finished	Jul 23 04:40:14 PM PDT 24
Peak memory	261924 kb
Host	smart-24cb1fa9-6755-4eb9-9276-7067e518ce50
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229979684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test. 1229979684
Directory	/workspace/38.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.4227614
Short name	T1199
Test name
Test status
Simulation time	51100400 ps
CPU time	13.87 seconds
Started	Jul 23 04:39:56 PM PDT 24
Finished	Jul 23 04:40:11 PM PDT 24
Peak memory	261900 kb
Host	smart-e1ce6ee9-ac6d-4810-ad32-d035ae04f09e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.4227614
Directory	/workspace/39.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1026463814
Short name	T1188
Test name
Test status
Simulation time	659236900 ps
CPU time	39.59 seconds
Started	Jul 23 04:39:23 PM PDT 24
Finished	Jul 23 04:40:03 PM PDT 24
Peak memory	262028 kb
Host	smart-8f083b7c-bed7-4b44-81cc-900f1009262b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026463814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_aliasing.1026463814
Directory	/workspace/4.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2374067357
Short name	T1214
Test name
Test status
Simulation time	11886946200 ps
CPU time	92.22 seconds
Started	Jul 23 04:39:19 PM PDT 24
Finished	Jul 23 04:40:53 PM PDT 24
Peak memory	261968 kb
Host	smart-4bfd9c50-a867-44d8-a165-ac5ad33e0285
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374067357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_bit_bash.2374067357
Directory	/workspace/4.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1795997400
Short name	T1160
Test name
Test status
Simulation time	27314900 ps
CPU time	45.9 seconds
Started	Jul 23 04:39:20 PM PDT 24
Finished	Jul 23 04:40:07 PM PDT 24
Peak memory	261972 kb
Host	smart-066f3ea2-383b-4382-a63c-a0970137b01c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795997400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_hw_reset.1795997400
Directory	/workspace/4.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3576784001
Short name	T256
Test name
Test status
Simulation time	467995100 ps
CPU time	20.98 seconds
Started	Jul 23 04:39:21 PM PDT 24
Finished	Jul 23 04:39:43 PM PDT 24
Peak memory	279988 kb
Host	smart-e6e5dd22-9135-4dec-beb3-d526fb19cd15
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576784001 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.3576784001
Directory	/workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3992105747
Short name	T1133
Test name
Test status
Simulation time	27178200 ps
CPU time	17.17 seconds
Started	Jul 23 04:39:19 PM PDT 24
Finished	Jul 23 04:39:38 PM PDT 24
Peak memory	264412 kb
Host	smart-e32cd2fb-b489-454e-ac7e-c3eed2df3d78
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992105747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 4.flash_ctrl_csr_rw.3992105747
Directory	/workspace/4.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3500932436
Short name	T1253
Test name
Test status
Simulation time	36732900 ps
CPU time	14.69 seconds
Started	Jul 23 04:39:30 PM PDT 24
Finished	Jul 23 04:39:47 PM PDT 24
Peak memory	261848 kb
Host	smart-1e844601-f8c5-47b2-8fb3-27c49eab8c0b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500932436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.3 500932436
Directory	/workspace/4.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2915239599
Short name	T258
Test name
Test status
Simulation time	84341500 ps
CPU time	13.68 seconds
Started	Jul 23 04:39:17 PM PDT 24
Finished	Jul 23 04:39:32 PM PDT 24
Peak memory	262776 kb
Host	smart-54f6292b-dc3d-4a04-8698-ef64e80efbf7
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915239599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_mem_partial_access.2915239599
Directory	/workspace/4.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3802413293
Short name	T1120
Test name
Test status
Simulation time	47410000 ps
CPU time	13.87 seconds
Started	Jul 23 04:39:28 PM PDT 24
Finished	Jul 23 04:39:44 PM PDT 24
Peak memory	261804 kb
Host	smart-b645d5f5-38a8-43c5-b0cd-b08a0b758740
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802413293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me m_walk.3802413293
Directory	/workspace/4.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.271483429
Short name	T1227
Test name
Test status
Simulation time	629522100 ps
CPU time	30.15 seconds
Started	Jul 23 04:39:17 PM PDT 24
Finished	Jul 23 04:39:49 PM PDT 24
Peak memory	263360 kb
Host	smart-027d3ffe-d859-4122-94a2-aa1721d0c47c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271483429 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.271483429
Directory	/workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.499316052
Short name	T1250
Test name
Test status
Simulation time	53025200 ps
CPU time	15.8 seconds
Started	Jul 23 04:39:29 PM PDT 24
Finished	Jul 23 04:39:47 PM PDT 24
Peak memory	253632 kb
Host	smart-9611a67a-6ca9-41b1-b78e-0e4285ad01db
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499316052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.499316052
Directory	/workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.891142005
Short name	T1139
Test name
Test status
Simulation time	21044200 ps
CPU time	15.93 seconds
Started	Jul 23 04:39:19 PM PDT 24
Finished	Jul 23 04:39:36 PM PDT 24
Peak memory	253560 kb
Host	smart-4a6478fc-d070-47dd-9c55-54050edd5a2f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891142005 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.891142005
Directory	/workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1747909489
Short name	T288
Test name
Test status
Simulation time	215476700 ps
CPU time	18.25 seconds
Started	Jul 23 04:39:17 PM PDT 24
Finished	Jul 23 04:39:37 PM PDT 24
Peak memory	264392 kb
Host	smart-2f6533e1-a156-41c0-a9d0-76bb91a8729d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747909489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.1 747909489
Directory	/workspace/4.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.514593235
Short name	T1145
Test name
Test status
Simulation time	22672800 ps
CPU time	13.37 seconds
Started	Jul 23 04:39:56 PM PDT 24
Finished	Jul 23 04:40:09 PM PDT 24
Peak memory	261976 kb
Host	smart-225fd88f-9c54-43b6-848c-f8d8ee071cfc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514593235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.514593235
Directory	/workspace/40.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2529517892
Short name	T369
Test name
Test status
Simulation time	114955600 ps
CPU time	13.56 seconds
Started	Jul 23 04:39:59 PM PDT 24
Finished	Jul 23 04:40:16 PM PDT 24
Peak memory	261884 kb
Host	smart-ac021d6e-9c6e-4866-8db2-8c2eafc3753b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529517892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test. 2529517892
Directory	/workspace/41.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2501747400
Short name	T1141
Test name
Test status
Simulation time	23536000 ps
CPU time	13.71 seconds
Started	Jul 23 04:39:56 PM PDT 24
Finished	Jul 23 04:40:11 PM PDT 24
Peak memory	262004 kb
Host	smart-7334dd1e-2890-43ca-a080-30f82f8e66e5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501747400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test. 2501747400
Directory	/workspace/42.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.592582037
Short name	T373
Test name
Test status
Simulation time	15583500 ps
CPU time	14.16 seconds
Started	Jul 23 04:39:59 PM PDT 24
Finished	Jul 23 04:40:16 PM PDT 24
Peak memory	261900 kb
Host	smart-e16e13ec-b36c-4f15-8afd-2b7ef673ebcd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592582037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.592582037
Directory	/workspace/43.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3585007225
Short name	T1186
Test name
Test status
Simulation time	20545800 ps
CPU time	14.18 seconds
Started	Jul 23 04:39:58 PM PDT 24
Finished	Jul 23 04:40:15 PM PDT 24
Peak memory	261752 kb
Host	smart-101d0404-0bee-47ec-8ea9-547a11bd97a9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585007225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test. 3585007225
Directory	/workspace/44.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3727577323
Short name	T1162
Test name
Test status
Simulation time	52814600 ps
CPU time	13.33 seconds
Started	Jul 23 04:39:59 PM PDT 24
Finished	Jul 23 04:40:16 PM PDT 24
Peak memory	261912 kb
Host	smart-6c8797fc-29d4-4d31-acca-886c4356cfb4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727577323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test. 3727577323
Directory	/workspace/45.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1797223416
Short name	T1171
Test name
Test status
Simulation time	46534000 ps
CPU time	13.39 seconds
Started	Jul 23 04:39:58 PM PDT 24
Finished	Jul 23 04:40:14 PM PDT 24
Peak memory	261868 kb
Host	smart-c0986bd4-04ec-43f8-a65a-9b7eadea4cc9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797223416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test. 1797223416
Directory	/workspace/46.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3201527177
Short name	T350
Test name
Test status
Simulation time	15301400 ps
CPU time	13.8 seconds
Started	Jul 23 04:39:57 PM PDT 24
Finished	Jul 23 04:40:13 PM PDT 24
Peak memory	261896 kb
Host	smart-22bf52f1-c408-4401-bec3-8a4a921ff039
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201527177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test. 3201527177
Directory	/workspace/47.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2326081425
Short name	T1215
Test name
Test status
Simulation time	18726200 ps
CPU time	14.33 seconds
Started	Jul 23 04:39:57 PM PDT 24
Finished	Jul 23 04:40:14 PM PDT 24
Peak memory	261812 kb
Host	smart-18222ede-5492-483f-93a9-db0b420cc177
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326081425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test. 2326081425
Directory	/workspace/48.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2117348890
Short name	T1254
Test name
Test status
Simulation time	16341500 ps
CPU time	13.37 seconds
Started	Jul 23 04:40:00 PM PDT 24
Finished	Jul 23 04:40:16 PM PDT 24
Peak memory	261900 kb
Host	smart-31eb5afe-a34c-4325-a9f2-1c6a41fb3548
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117348890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test. 2117348890
Directory	/workspace/49.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1644698971
Short name	T253
Test name
Test status
Simulation time	48714100 ps
CPU time	16.69 seconds
Started	Jul 23 04:39:25 PM PDT 24
Finished	Jul 23 04:39:43 PM PDT 24
Peak memory	272616 kb
Host	smart-3e19072b-6f4a-4279-91e1-a5d47419b8ed
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644698971 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.1644698971
Directory	/workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2119356421
Short name	T1233
Test name
Test status
Simulation time	18267500 ps
CPU time	14.45 seconds
Started	Jul 23 04:39:25 PM PDT 24
Finished	Jul 23 04:39:40 PM PDT 24
Peak memory	262044 kb
Host	smart-8bd2bc08-86c0-45f2-b1e9-156c8308f231
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119356421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 5.flash_ctrl_csr_rw.2119356421
Directory	/workspace/5.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.284799917
Short name	T1235
Test name
Test status
Simulation time	54552500 ps
CPU time	13.85 seconds
Started	Jul 23 04:39:30 PM PDT 24
Finished	Jul 23 04:39:45 PM PDT 24
Peak memory	262136 kb
Host	smart-23256f31-e711-4aed-bf1a-f0651c570fe1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284799917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.284799917
Directory	/workspace/5.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3744604855
Short name	T328
Test name
Test status
Simulation time	463581600 ps
CPU time	16.34 seconds
Started	Jul 23 04:39:18 PM PDT 24
Finished	Jul 23 04:39:37 PM PDT 24
Peak memory	264056 kb
Host	smart-476d0c89-d706-4b9d-b763-7a40cf2a0f3a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744604855 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.3744604855
Directory	/workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.593621707
Short name	T1144
Test name
Test status
Simulation time	37319100 ps
CPU time	15.39 seconds
Started	Jul 23 04:39:17 PM PDT 24
Finished	Jul 23 04:39:34 PM PDT 24
Peak memory	253768 kb
Host	smart-bab5a480-72f7-498a-9201-a6fbc71bc7a1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593621707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.593621707
Directory	/workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2447723739
Short name	T1174
Test name
Test status
Simulation time	42715900 ps
CPU time	15.59 seconds
Started	Jul 23 04:39:23 PM PDT 24
Finished	Jul 23 04:39:40 PM PDT 24
Peak memory	253528 kb
Host	smart-dc5d7876-e3e1-405d-b7f0-4d9fb9c701b0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447723739 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.2447723739
Directory	/workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3686993228
Short name	T257
Test name
Test status
Simulation time	68643300 ps
CPU time	16.2 seconds
Started	Jul 23 04:39:29 PM PDT 24
Finished	Jul 23 04:39:47 PM PDT 24
Peak memory	263632 kb
Host	smart-bcb01d7e-151a-4255-b187-bb9494999925
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686993228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.3 686993228
Directory	/workspace/5.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1206017878
Short name	T295
Test name
Test status
Simulation time	897532300 ps
CPU time	461.66 seconds
Started	Jul 23 04:39:16 PM PDT 24
Finished	Jul 23 04:46:59 PM PDT 24
Peak memory	264480 kb
Host	smart-493fe354-d26f-407c-bc86-b18d8eab591c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206017878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl _tl_intg_err.1206017878
Directory	/workspace/5.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3412781273
Short name	T221
Test name
Test status
Simulation time	50925700 ps
CPU time	17.39 seconds
Started	Jul 23 04:39:17 PM PDT 24
Finished	Jul 23 04:39:36 PM PDT 24
Peak memory	272728 kb
Host	smart-8550c03e-800a-4638-8fcb-77132648ae15
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412781273 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.3412781273
Directory	/workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2963092460
Short name	T1161
Test name
Test status
Simulation time	53455500 ps
CPU time	14.34 seconds
Started	Jul 23 04:39:28 PM PDT 24
Finished	Jul 23 04:39:44 PM PDT 24
Peak memory	264420 kb
Host	smart-98b1e4de-c2b1-4be3-b044-58ded6d480b9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963092460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 6.flash_ctrl_csr_rw.2963092460
Directory	/workspace/6.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1483518504
Short name	T372
Test name
Test status
Simulation time	17004100 ps
CPU time	13.65 seconds
Started	Jul 23 04:39:18 PM PDT 24
Finished	Jul 23 04:39:34 PM PDT 24
Peak memory	261888 kb
Host	smart-81a7327b-cdc8-4897-9700-142cc2af33a7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483518504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.1 483518504
Directory	/workspace/6.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1294381153
Short name	T332
Test name
Test status
Simulation time	441100500 ps
CPU time	31.16 seconds
Started	Jul 23 04:39:21 PM PDT 24
Finished	Jul 23 04:39:53 PM PDT 24
Peak memory	263100 kb
Host	smart-43ff8920-223f-4738-930e-8b709f713544
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294381153 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.1294381153
Directory	/workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.4264696057
Short name	T1121
Test name
Test status
Simulation time	23792500 ps
CPU time	15.89 seconds
Started	Jul 23 04:39:27 PM PDT 24
Finished	Jul 23 04:39:45 PM PDT 24
Peak memory	253612 kb
Host	smart-e259eace-c069-4d7e-8806-e7b9f56e15ed
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264696057 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.4264696057
Directory	/workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.752687457
Short name	T1195
Test name
Test status
Simulation time	20636200 ps
CPU time	15.64 seconds
Started	Jul 23 04:39:18 PM PDT 24
Finished	Jul 23 04:39:36 PM PDT 24
Peak memory	253612 kb
Host	smart-1953beac-c8c6-47f9-b2d0-7ccb5104060c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752687457 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.752687457
Directory	/workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.811115617
Short name	T277
Test name
Test status
Simulation time	144940900 ps
CPU time	16.49 seconds
Started	Jul 23 04:39:32 PM PDT 24
Finished	Jul 23 04:39:51 PM PDT 24
Peak memory	264420 kb
Host	smart-1908b81e-54e0-406e-a69c-681e303b9235
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811115617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.811115617
Directory	/workspace/6.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.892750672
Short name	T379
Test name
Test status
Simulation time	569734300 ps
CPU time	458.55 seconds
Started	Jul 23 04:39:27 PM PDT 24
Finished	Jul 23 04:47:07 PM PDT 24
Peak memory	264400 kb
Host	smart-64e047f7-2d16-4ad3-b82c-1fd917ce68d0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892750672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ tl_intg_err.892750672
Directory	/workspace/6.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2613156534
Short name	T289
Test name
Test status
Simulation time	91003400 ps
CPU time	20.12 seconds
Started	Jul 23 04:39:44 PM PDT 24
Finished	Jul 23 04:40:06 PM PDT 24
Peak memory	279716 kb
Host	smart-baab6424-a3bb-4047-b6f8-f5f30571b45f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613156534 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.2613156534
Directory	/workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2767228092
Short name	T61
Test name
Test status
Simulation time	22952100 ps
CPU time	13.97 seconds
Started	Jul 23 04:39:32 PM PDT 24
Finished	Jul 23 04:39:49 PM PDT 24
Peak memory	264392 kb
Host	smart-a3261699-9f30-4250-aef7-0ae78aff2136
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767228092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 7.flash_ctrl_csr_rw.2767228092
Directory	/workspace/7.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3410542483
Short name	T1222
Test name
Test status
Simulation time	26499900 ps
CPU time	13.79 seconds
Started	Jul 23 04:39:30 PM PDT 24
Finished	Jul 23 04:39:46 PM PDT 24
Peak memory	261988 kb
Host	smart-1f72d647-bff1-4e7a-bb8a-c2f8b8c8274a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410542483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.3 410542483
Directory	/workspace/7.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.605573523
Short name	T1189
Test name
Test status
Simulation time	312915100 ps
CPU time	18.06 seconds
Started	Jul 23 04:39:32 PM PDT 24
Finished	Jul 23 04:39:53 PM PDT 24
Peak memory	262000 kb
Host	smart-4655255e-e6e0-4b38-9cf0-4b048931e6f8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605573523 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.605573523
Directory	/workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2833359160
Short name	T1150
Test name
Test status
Simulation time	42399100 ps
CPU time	13.34 seconds
Started	Jul 23 04:39:17 PM PDT 24
Finished	Jul 23 04:39:32 PM PDT 24
Peak memory	253680 kb
Host	smart-2649abc9-fa89-40b9-b711-6fb55f9a7739
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833359160 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2833359160
Directory	/workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3433090479
Short name	T1123
Test name
Test status
Simulation time	31808400 ps
CPU time	15.95 seconds
Started	Jul 23 04:39:35 PM PDT 24
Finished	Jul 23 04:39:53 PM PDT 24
Peak memory	253684 kb
Host	smart-4d64c626-98d6-4bf9-8cd8-e79575859100
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433090479 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.3433090479
Directory	/workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1490619858
Short name	T279
Test name
Test status
Simulation time	79829700 ps
CPU time	17.08 seconds
Started	Jul 23 04:39:29 PM PDT 24
Finished	Jul 23 04:39:48 PM PDT 24
Peak memory	264672 kb
Host	smart-9d118363-ccec-4540-a6e3-161482341a09
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490619858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.1 490619858
Directory	/workspace/7.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.29968227
Short name	T326
Test name
Test status
Simulation time	438267200 ps
CPU time	19.27 seconds
Started	Jul 23 04:39:32 PM PDT 24
Finished	Jul 23 04:39:54 PM PDT 24
Peak memory	272300 kb
Host	smart-01a47827-2652-4076-aec9-7cd90ce189d0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29968227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.29968227
Directory	/workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2813869523
Short name	T1219
Test name
Test status
Simulation time	366691200 ps
CPU time	17.02 seconds
Started	Jul 23 04:39:31 PM PDT 24
Finished	Jul 23 04:39:50 PM PDT 24
Peak memory	262016 kb
Host	smart-8b741269-5845-4437-bda9-1b6e5e5cfb83
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813869523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 8.flash_ctrl_csr_rw.2813869523
Directory	/workspace/8.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1121409446
Short name	T1152
Test name
Test status
Simulation time	20030000 ps
CPU time	13.6 seconds
Started	Jul 23 04:39:41 PM PDT 24
Finished	Jul 23 04:39:57 PM PDT 24
Peak memory	261760 kb
Host	smart-7d532360-4060-44e8-8bf0-314420408b6d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121409446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.1 121409446
Directory	/workspace/8.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2668116570
Short name	T1228
Test name
Test status
Simulation time	64176900 ps
CPU time	19.82 seconds
Started	Jul 23 04:39:35 PM PDT 24
Finished	Jul 23 04:39:56 PM PDT 24
Peak memory	261980 kb
Host	smart-cb64f1d4-984c-488e-8a72-685ea91dfec9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668116570 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.2668116570
Directory	/workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3428844997
Short name	T1126
Test name
Test status
Simulation time	32595900 ps
CPU time	13.83 seconds
Started	Jul 23 04:39:42 PM PDT 24
Finished	Jul 23 04:39:57 PM PDT 24
Peak memory	253496 kb
Host	smart-33b42b5e-99bc-43cb-9ff6-12c422cfa1db
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428844997 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.3428844997
Directory	/workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1286953365
Short name	T1225
Test name
Test status
Simulation time	57737900 ps
CPU time	15.52 seconds
Started	Jul 23 04:39:36 PM PDT 24
Finished	Jul 23 04:39:52 PM PDT 24
Peak memory	253668 kb
Host	smart-dba89127-c81c-4a6d-8ca2-8ff7e4d699a3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286953365 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.1286953365
Directory	/workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3458285636
Short name	T284
Test name
Test status
Simulation time	131027900 ps
CPU time	16.51 seconds
Started	Jul 23 04:39:35 PM PDT 24
Finished	Jul 23 04:39:53 PM PDT 24
Peak memory	264524 kb
Host	smart-59d967eb-4e6b-4375-b6fa-f3cc65c40b6a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458285636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.3 458285636
Directory	/workspace/8.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1169198849
Short name	T1185
Test name
Test status
Simulation time	89411900 ps
CPU time	17.14 seconds
Started	Jul 23 04:39:39 PM PDT 24
Finished	Jul 23 04:39:57 PM PDT 24
Peak memory	272580 kb
Host	smart-63c7f964-4f45-40ce-9e00-5926f9efbe0d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169198849 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.1169198849
Directory	/workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1757137261
Short name	T1200
Test name
Test status
Simulation time	141691000 ps
CPU time	15.18 seconds
Started	Jul 23 04:39:43 PM PDT 24
Finished	Jul 23 04:40:00 PM PDT 24
Peak memory	261968 kb
Host	smart-3c57b348-46bc-4dab-9056-fd8a774dcc5a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757137261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 9.flash_ctrl_csr_rw.1757137261
Directory	/workspace/9.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2058753773
Short name	T283
Test name
Test status
Simulation time	43069700 ps
CPU time	13.33 seconds
Started	Jul 23 04:39:40 PM PDT 24
Finished	Jul 23 04:39:54 PM PDT 24
Peak memory	261748 kb
Host	smart-07170671-d6b6-4eb1-a601-c7307e3d4c9f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058753773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.2 058753773
Directory	/workspace/9.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.4110461208
Short name	T1197
Test name
Test status
Simulation time	624783700 ps
CPU time	35.23 seconds
Started	Jul 23 04:39:31 PM PDT 24
Finished	Jul 23 04:40:09 PM PDT 24
Peak memory	264400 kb
Host	smart-d1cb3022-25d1-4a49-bc4a-3343c8fe7e27
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110461208 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.4110461208
Directory	/workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1132127411
Short name	T1220
Test name
Test status
Simulation time	38193000 ps
CPU time	15.45 seconds
Started	Jul 23 04:39:30 PM PDT 24
Finished	Jul 23 04:39:47 PM PDT 24
Peak memory	253680 kb
Host	smart-d70ad782-d514-457b-9512-9b2ad2f35d36
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132127411 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.1132127411
Directory	/workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2042009538
Short name	T1218
Test name
Test status
Simulation time	12782000 ps
CPU time	13.35 seconds
Started	Jul 23 04:39:41 PM PDT 24
Finished	Jul 23 04:39:55 PM PDT 24
Peak memory	253548 kb
Host	smart-66c1523d-032c-4538-b340-792e25291e72
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042009538 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.2042009538
Directory	/workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.300874827
Short name	T1129
Test name
Test status
Simulation time	187840100 ps
CPU time	17.69 seconds
Started	Jul 23 04:39:36 PM PDT 24
Finished	Jul 23 04:39:55 PM PDT 24
Peak memory	264536 kb
Host	smart-3ec5998a-fd71-495a-a366-4c866958762c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300874827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.300874827
Directory	/workspace/9.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1330558216
Short name	T104
Test name
Test status
Simulation time	705670800 ps
CPU time	764.2 seconds
Started	Jul 23 04:39:45 PM PDT 24
Finished	Jul 23 04:52:32 PM PDT 24
Peak memory	264508 kb
Host	smart-0fc2f4d4-2b2e-4e62-8fc9-412aa69a3de2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330558216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl _tl_intg_err.1330558216
Directory	/workspace/9.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_access_after_disable.2751944894
Short name	T38
Test name
Test status
Simulation time	13573200 ps
CPU time	14.02 seconds
Started	Jul 23 04:43:40 PM PDT 24
Finished	Jul 23 04:44:09 PM PDT 24
Peak memory	261160 kb
Host	smart-862d022a-aa61-476c-83c9-5acc267da964
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751944894 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.2751944894
Directory	/workspace/0.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/0.flash_ctrl_alert_test.3789712259
Short name	T622
Test name
Test status
Simulation time	115230600 ps
CPU time	13.87 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 04:44:09 PM PDT 24
Peak memory	258272 kb
Host	smart-f808a9ec-58ac-4d2d-9cdc-ff8cdb76c76a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789712259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.3 789712259
Directory	/workspace/0.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.flash_ctrl_connect.3967428818
Short name	T778
Test name
Test status
Simulation time	13927900 ps
CPU time	16.03 seconds
Started	Jul 23 04:43:40 PM PDT 24
Finished	Jul 23 04:44:11 PM PDT 24
Peak memory	284232 kb
Host	smart-b09cf648-65fe-48be-b58c-35f3341075fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3967428818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.3967428818
Directory	/workspace/0.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/0.flash_ctrl_disable.151081430
Short name	T401
Test name
Test status
Simulation time	27881100 ps
CPU time	21.44 seconds
Started	Jul 23 04:43:40 PM PDT 24
Finished	Jul 23 04:44:16 PM PDT 24
Peak memory	273516 kb
Host	smart-9d8491ec-3f02-4015-a179-4505403cc80d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151081430 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_disable.151081430
Directory	/workspace/0.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/0.flash_ctrl_erase_suspend.3185905543
Short name	T1053
Test name
Test status
Simulation time	2395948300 ps
CPU time	344.57 seconds
Started	Jul 23 04:43:17 PM PDT 24
Finished	Jul 23 04:49:31 PM PDT 24
Peak memory	263512 kb
Host	smart-21c35d1b-5a5e-4dca-b983-8d5d975ece8a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3185905543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.3185905543
Directory	/workspace/0.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_type.4129398069
Short name	T841
Test name
Test status
Simulation time	487308400 ps
CPU time	2230.27 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 05:21:51 PM PDT 24
Peak memory	264432 kb
Host	smart-ad66c4ca-41b3-47d4-9a8d-6fe0a57d7390
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129398069 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.4129398069
Directory	/workspace/0.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/0.flash_ctrl_fs_sup.3338044561
Short name	T528
Test name
Test status
Simulation time	726806000 ps
CPU time	41.56 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 04:44:37 PM PDT 24
Peak memory	265236 kb
Host	smart-9fd4014a-9075-48e9-a4ef-50d9e51fa845
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338044561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.flash_ctrl_fs_sup.3338044561
Directory	/workspace/0.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/0.flash_ctrl_full_mem_access.2030828841
Short name	T148
Test name
Test status
Simulation time	81417812400 ps
CPU time	2889.48 seconds
Started	Jul 23 04:43:19 PM PDT 24
Finished	Jul 23 05:31:57 PM PDT 24
Peak memory	265084 kb
Host	smart-e7553938-50e4-49fc-b97e-32461fcc0290
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030828841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c trl_full_mem_access.2030828841
Directory	/workspace/0.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_addr_infection.1326222562
Short name	T44
Test name
Test status
Simulation time	40239300 ps
CPU time	27.51 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 04:44:23 PM PDT 24
Peak memory	275804 kb
Host	smart-cb26a375-e0a9-4b76-a1fd-7b0622d37219
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326222562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_host_addr_infection.1326222562
Directory	/workspace/0.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_dir_rd.505879024
Short name	T712
Test name
Test status
Simulation time	34316100 ps
CPU time	45.62 seconds
Started	Jul 23 04:44:25 PM PDT 24
Finished	Jul 23 04:45:16 PM PDT 24
Peak memory	261728 kb
Host	smart-fecd0c4a-ba1f-4404-a93e-4a4d7a2371cc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=505879024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.505879024
Directory	/workspace/0.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.2556507573
Short name	T876
Test name
Test status
Simulation time	10065584100 ps
CPU time	50.75 seconds
Started	Jul 23 04:43:40 PM PDT 24
Finished	Jul 23 04:44:46 PM PDT 24
Peak memory	274564 kb
Host	smart-55896c2c-868e-4a37-92a9-b91b774a6400
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556507573 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.2556507573
Directory	/workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_rma_reset.553960572
Short name	T108
Test name
Test status
Simulation time	40126161900 ps
CPU time	779.77 seconds
Started	Jul 23 04:44:36 PM PDT 24
Finished	Jul 23 04:57:41 PM PDT 24
Peak memory	264548 kb
Host	smart-1d500425-a442-4e80-9f88-b6cf12ccc3cb
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553960572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_hw_rma_reset.553960572
Directory	/workspace/0.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_sec_otp.3773660331
Short name	T334
Test name
Test status
Simulation time	4134277200 ps
CPU time	119.9 seconds
Started	Jul 23 04:43:18 PM PDT 24
Finished	Jul 23 04:45:47 PM PDT 24
Peak memory	262932 kb
Host	smart-d9768884-5971-41b0-a51c-a3ff94dedfd0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773660331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h w_sec_otp.3773660331
Directory	/workspace/0.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd.2763794456
Short name	T30
Test name
Test status
Simulation time	1394152500 ps
CPU time	134.75 seconds
Started	Jul 23 04:43:29 PM PDT 24
Finished	Jul 23 04:46:05 PM PDT 24
Peak memory	295236 kb
Host	smart-03b40d80-d8b6-495c-8759-23f5ba858f6f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763794456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_intr_rd.2763794456
Directory	/workspace/0.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.3135589977
Short name	T728
Test name
Test status
Simulation time	45098130000 ps
CPU time	329.43 seconds
Started	Jul 23 04:43:30 PM PDT 24
Finished	Jul 23 04:49:20 PM PDT 24
Peak memory	290984 kb
Host	smart-3d3d5b00-93ac-4cc0-9261-2651a87af129
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135589977 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.3135589977
Directory	/workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr.2508814388
Short name	T1108
Test name
Test status
Simulation time	2188661400 ps
CPU time	68.49 seconds
Started	Jul 23 04:43:31 PM PDT 24
Finished	Jul 23 04:44:59 PM PDT 24
Peak memory	265264 kb
Host	smart-fb33938b-7b03-491c-b4e6-3c0a693b02d0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508814388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.flash_ctrl_intr_wr.2508814388
Directory	/workspace/0.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.1068641868
Short name	T923
Test name
Test status
Simulation time	64664846600 ps
CPU time	172.73 seconds
Started	Jul 23 04:43:31 PM PDT 24
Finished	Jul 23 04:46:43 PM PDT 24
Peak memory	265272 kb
Host	smart-c266e4c3-9f90-405b-8e7b-b082c410248a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106 8641868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.1068641868
Directory	/workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_invalid_op.1775360818
Short name	T961
Test name
Test status
Simulation time	7463196400 ps
CPU time	84.3 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 04:46:05 PM PDT 24
Peak memory	260268 kb
Host	smart-3e98cb37-335d-435d-8752-cf526f8dbfeb
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775360818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.1775360818
Directory	/workspace/0.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_lcmgr_intg.2711170346
Short name	T517
Test name
Test status
Simulation time	39982100 ps
CPU time	13.32 seconds
Started	Jul 23 04:43:40 PM PDT 24
Finished	Jul 23 04:44:08 PM PDT 24
Peak memory	264632 kb
Host	smart-37b1102e-cb3f-4aad-a293-619d956da859
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711170346 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.2711170346
Directory	/workspace/0.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_oversize_error.2506849921
Short name	T264
Test name
Test status
Simulation time	1735443200 ps
CPU time	145.69 seconds
Started	Jul 23 04:43:29 PM PDT 24
Finished	Jul 23 04:46:16 PM PDT 24
Peak memory	281696 kb
Host	smart-f8012b51-3784-4453-9423-4c9776be0700
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506849921 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.2506849921
Directory	/workspace/0.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb.2314574764
Short name	T442
Test name
Test status
Simulation time	101171800 ps
CPU time	234.23 seconds
Started	Jul 23 04:43:22 PM PDT 24
Finished	Jul 23 04:47:42 PM PDT 24
Peak memory	263252 kb
Host	smart-93d3a10e-5553-41b0-9902-9981acc36518
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2314574764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.2314574764
Directory	/workspace/0.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/0.flash_ctrl_prog_reset.3616084502
Short name	T459
Test name
Test status
Simulation time	20665600 ps
CPU time	13.32 seconds
Started	Jul 23 04:43:35 PM PDT 24
Finished	Jul 23 04:44:05 PM PDT 24
Peak memory	259180 kb
Host	smart-d906858e-86e3-47ef-9dec-c023d22c01d2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616084502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.flash_ctrl_prog_reset.3616084502
Directory	/workspace/0.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rand_ops.3212461710
Short name	T1111
Test name
Test status
Simulation time	476803500 ps
CPU time	250.41 seconds
Started	Jul 23 04:43:18 PM PDT 24
Finished	Jul 23 04:47:57 PM PDT 24
Peak memory	281568 kb
Host	smart-9f55da2c-24af-43a4-af14-e2c90619de14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3212461710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.3212461710
Directory	/workspace/0.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.573543828
Short name	T603
Test name
Test status
Simulation time	90793500 ps
CPU time	97.75 seconds
Started	Jul 23 04:44:36 PM PDT 24
Finished	Jul 23 04:46:20 PM PDT 24
Peak memory	262484 kb
Host	smart-32faeb2b-f5e5-479b-985c-15baec7603ee
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=573543828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.573543828
Directory	/workspace/0.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_intg.3848974375
Short name	T553
Test name
Test status
Simulation time	63155600 ps
CPU time	31.94 seconds
Started	Jul 23 04:43:40 PM PDT 24
Finished	Jul 23 04:44:27 PM PDT 24
Peak memory	275580 kb
Host	smart-4d3c578e-36b4-42a1-a68e-38d62842abe4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848974375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.flash_ctrl_rd_intg.3848974375
Directory	/workspace/0.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_ooo.1909093876
Short name	T1103
Test name
Test status
Simulation time	63232800 ps
CPU time	42.95 seconds
Started	Jul 23 04:43:38 PM PDT 24
Finished	Jul 23 04:44:37 PM PDT 24
Peak memory	275772 kb
Host	smart-113fb3f5-a769-4598-866e-392031f47913
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909093876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_rd_ooo.1909093876
Directory	/workspace/0.flash_ctrl_rd_ooo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_re_evict.2953127950
Short name	T643
Test name
Test status
Simulation time	261633100 ps
CPU time	33.83 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 04:44:29 PM PDT 24
Peak memory	270664 kb
Host	smart-d8f4dd30-114c-45d3-94b9-27dc246f27b6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953127950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_re_evict.2953127950
Directory	/workspace/0.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep.923764094
Short name	T799
Test name
Test status
Simulation time	25608400 ps
CPU time	14.01 seconds
Started	Jul 23 04:43:37 PM PDT 24
Finished	Jul 23 04:44:07 PM PDT 24
Peak memory	265336 kb
Host	smart-8be6c993-562f-47f4-8f07-6a21f03918b9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=923764094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep. 923764094
Directory	/workspace/0.flash_ctrl_read_word_sweep/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.4266975579
Short name	T116
Test name
Test status
Simulation time	31822400 ps
CPU time	21.26 seconds
Started	Jul 23 04:43:30 PM PDT 24
Finished	Jul 23 04:44:12 PM PDT 24
Peak memory	265256 kb
Host	smart-9b91d322-86b9-49f4-918c-e1c370776a6d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266975579 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.4266975579
Directory	/workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.3585049002
Short name	T17
Test name
Test status
Simulation time	121521600 ps
CPU time	20.83 seconds
Started	Jul 23 04:43:31 PM PDT 24
Finished	Jul 23 04:44:12 PM PDT 24
Peak memory	265320 kb
Host	smart-55ab5130-7612-40bd-ab3e-5c303830ed27
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585049002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl ash_ctrl_read_word_sweep_serr.3585049002
Directory	/workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro.1454030964
Short name	T803
Test name
Test status
Simulation time	1220580700 ps
CPU time	120.85 seconds
Started	Jul 23 04:43:31 PM PDT 24
Finished	Jul 23 04:45:52 PM PDT 24
Peak memory	291668 kb
Host	smart-344caac0-1924-4c45-bbf6-f85afb7145c7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454030964 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.flash_ctrl_ro.1454030964
Directory	/workspace/0.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_derr.2541455210
Short name	T1066
Test name
Test status
Simulation time	2417157300 ps
CPU time	120.04 seconds
Started	Jul 23 04:43:31 PM PDT 24
Finished	Jul 23 04:45:51 PM PDT 24
Peak memory	281732 kb
Host	smart-d8846c00-6f75-454f-bfa5-70d8f8587740
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2541455210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.2541455210
Directory	/workspace/0.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_serr.155414202
Short name	T605
Test name
Test status
Simulation time	2494227200 ps
CPU time	126 seconds
Started	Jul 23 04:43:32 PM PDT 24
Finished	Jul 23 04:45:57 PM PDT 24
Peak memory	290336 kb
Host	smart-2f91f793-cd50-4130-abef-6b9d99b8fee8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155414202 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.155414202
Directory	/workspace/0.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw.3212823720
Short name	T519
Test name
Test status
Simulation time	8464766200 ps
CPU time	476.07 seconds
Started	Jul 23 04:43:32 PM PDT 24
Finished	Jul 23 04:51:47 PM PDT 24
Peak memory	314504 kb
Host	smart-2767c4e3-bf36-4477-ac2d-ace329b45e37
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212823720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.flash_ctrl_rw.3212823720
Directory	/workspace/0.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.1601557014
Short name	T483
Test name
Test status
Simulation time	69679500 ps
CPU time	30.5 seconds
Started	Jul 23 04:43:32 PM PDT 24
Finished	Jul 23 04:44:21 PM PDT 24
Peak memory	275684 kb
Host	smart-4252fdf7-1853-4d9c-bf6f-5c46236aca29
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601557014 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.1601557014
Directory	/workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_serr.3760322884
Short name	T539
Test name
Test status
Simulation time	6919456000 ps
CPU time	562.99 seconds
Started	Jul 23 04:43:30 PM PDT 24
Finished	Jul 23 04:53:13 PM PDT 24
Peak memory	313988 kb
Host	smart-3ebe4e39-63f3-49c6-b480-49dfa15ca85c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760322884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_s err.3760322884
Directory	/workspace/0.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_address.3192769970
Short name	T582
Test name
Test status
Simulation time	1844471900 ps
CPU time	96.32 seconds
Started	Jul 23 04:43:31 PM PDT 24
Finished	Jul 23 04:45:27 PM PDT 24
Peak memory	264976 kb
Host	smart-5573180d-1e3e-481b-926c-568471cbeac1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192769970 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.flash_ctrl_serr_address.3192769970
Directory	/workspace/0.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_counter.4254180799
Short name	T516
Test name
Test status
Simulation time	3170620300 ps
CPU time	69.97 seconds
Started	Jul 23 04:43:32 PM PDT 24
Finished	Jul 23 04:45:01 PM PDT 24
Peak memory	276324 kb
Host	smart-1536ed53-9849-40fb-be0c-f4be4ad71e62
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254180799 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_serr_counter.4254180799
Directory	/workspace/0.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke.1396249325
Short name	T1091
Test name
Test status
Simulation time	198639200 ps
CPU time	120.16 seconds
Started	Jul 23 04:43:18 PM PDT 24
Finished	Jul 23 04:45:47 PM PDT 24
Peak memory	278028 kb
Host	smart-1fa4662b-6513-4b5e-8b12-59cdd4324249
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1396249325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.1396249325
Directory	/workspace/0.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke_hw.2896372921
Short name	T897
Test name
Test status
Simulation time	104789400 ps
CPU time	25.54 seconds
Started	Jul 23 04:44:36 PM PDT 24
Finished	Jul 23 04:45:07 PM PDT 24
Peak memory	259328 kb
Host	smart-00d88ac1-206d-49f5-bd0f-fb9c9d94687e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896372921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.2896372921
Directory	/workspace/0.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_stress_all.1211980128
Short name	T556
Test name
Test status
Simulation time	72291200 ps
CPU time	64.09 seconds
Started	Jul 23 04:43:39 PM PDT 24
Finished	Jul 23 04:44:59 PM PDT 24
Peak memory	261328 kb
Host	smart-254d1f6d-3bc1-4506-8b66-d54d4fb19e25
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211980128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres s_all.1211980128
Directory	/workspace/0.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sw_op.1430993062
Short name	T458
Test name
Test status
Simulation time	77302300 ps
CPU time	24.17 seconds
Started	Jul 23 04:43:11 PM PDT 24
Finished	Jul 23 04:44:08 PM PDT 24
Peak memory	262492 kb
Host	smart-c4ecab7f-ef9b-47c6-8ef5-9698cb7cc257
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1430993062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.1430993062
Directory	/workspace/0.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_wo.2135190874
Short name	T810
Test name
Test status
Simulation time	10524777300 ps
CPU time	182.98 seconds
Started	Jul 23 04:44:34 PM PDT 24
Finished	Jul 23 04:47:42 PM PDT 24
Peak memory	259140 kb
Host	smart-97fc75a9-587a-4048-83b0-b71ecad4288a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135190874 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.flash_ctrl_wo.2135190874
Directory	/workspace/0.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_write_word_sweep.486352200
Short name	T1007
Test name
Test status
Simulation time	38274200 ps
CPU time	15.49 seconds
Started	Jul 23 04:43:30 PM PDT 24
Finished	Jul 23 04:44:06 PM PDT 24
Peak memory	258636 kb
Host	smart-d061271b-614d-4077-a71f-26727dcc1ef2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=486352200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swee p.486352200
Directory	/workspace/0.flash_ctrl_write_word_sweep/latest

Test location	/workspace/coverage/default/1.flash_ctrl_alert_test.3597267490
Short name	T607
Test name
Test status
Simulation time	29809900 ps
CPU time	13.74 seconds
Started	Jul 23 04:43:58 PM PDT 24
Finished	Jul 23 04:44:15 PM PDT 24
Peak memory	258336 kb
Host	smart-ad859589-f2a9-437e-bee5-212ee511a025
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597267490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.3 597267490
Directory	/workspace/1.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.flash_ctrl_config_regwen.1281529316
Short name	T385
Test name
Test status
Simulation time	68591200 ps
CPU time	13.63 seconds
Started	Jul 23 04:43:58 PM PDT 24
Finished	Jul 23 04:44:16 PM PDT 24
Peak memory	261468 kb
Host	smart-6bb3b885-9c5b-4f7d-86d6-c4ec1356fc8d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281529316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .flash_ctrl_config_regwen.1281529316
Directory	/workspace/1.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/1.flash_ctrl_connect.741717517
Short name	T1107
Test name
Test status
Simulation time	22652900 ps
CPU time	13.47 seconds
Started	Jul 23 04:43:51 PM PDT 24
Finished	Jul 23 04:44:13 PM PDT 24
Peak memory	284212 kb
Host	smart-d81fbc7a-9a89-4702-95dd-0a7e0fd12837
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=741717517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.741717517
Directory	/workspace/1.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/1.flash_ctrl_erase_suspend.2479183784
Short name	T209
Test name
Test status
Simulation time	12662400000 ps
CPU time	371.15 seconds
Started	Jul 23 04:43:38 PM PDT 24
Finished	Jul 23 04:50:05 PM PDT 24
Peak memory	263500 kb
Host	smart-838c1269-d3e0-4066-9284-a4da0578a419
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2479183784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.2479183784
Directory	/workspace/1.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_mp.1375266050
Short name	T161
Test name
Test status
Simulation time	8618331100 ps
CPU time	2088.57 seconds
Started	Jul 23 04:43:42 PM PDT 24
Finished	Jul 23 05:18:44 PM PDT 24
Peak memory	264324 kb
Host	smart-80ca9286-9ea6-46be-96f3-7cd5b00ab558
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1375266050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.1375266050
Directory	/workspace/1.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_type.1319414621
Short name	T83
Test name
Test status
Simulation time	14761263200 ps
CPU time	1952.09 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 05:16:28 PM PDT 24
Peak memory	264492 kb
Host	smart-8d9743a2-8e8c-4534-8438-ccd6824f98bb
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319414621 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.1319414621
Directory	/workspace/1.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_win.3740987442
Short name	T550
Test name
Test status
Simulation time	2852684300 ps
CPU time	991.03 seconds
Started	Jul 23 04:43:42 PM PDT 24
Finished	Jul 23 05:00:27 PM PDT 24
Peak memory	272532 kb
Host	smart-bded1f71-b32d-4b41-95b8-c20f85cbdef6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3740987442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.3740987442
Directory	/workspace/1.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fetch_code.1599977920
Short name	T40
Test name
Test status
Simulation time	1513993800 ps
CPU time	27.17 seconds
Started	Jul 23 04:43:40 PM PDT 24
Finished	Jul 23 04:44:22 PM PDT 24
Peak memory	262500 kb
Host	smart-64200735-145a-4651-acda-a0302e78e4ba
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599977920 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.1599977920
Directory	/workspace/1.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fs_sup.3095097896
Short name	T538
Test name
Test status
Simulation time	314447200 ps
CPU time	40.28 seconds
Started	Jul 23 04:43:47 PM PDT 24
Finished	Jul 23 04:44:37 PM PDT 24
Peak memory	265196 kb
Host	smart-ec08191c-017d-4347-a81a-3622789b8fe1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095097896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.flash_ctrl_fs_sup.3095097896
Directory	/workspace/1.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/1.flash_ctrl_full_mem_access.3807878530
Short name	T920
Test name
Test status
Simulation time	382151806500 ps
CPU time	2850.97 seconds
Started	Jul 23 04:43:40 PM PDT 24
Finished	Jul 23 05:31:26 PM PDT 24
Peak memory	265180 kb
Host	smart-f3616c5e-dd0a-49d3-9db7-a734b4bfe49a
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807878530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c trl_full_mem_access.3807878530
Directory	/workspace/1.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_addr_infection.1066298600
Short name	T861
Test name
Test status
Simulation time	26820600 ps
CPU time	27.5 seconds
Started	Jul 23 04:43:56 PM PDT 24
Finished	Jul 23 04:44:28 PM PDT 24
Peak memory	268356 kb
Host	smart-b40b0be8-ccc8-4e1f-b6b5-b02f8dd29873
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066298600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_host_addr_infection.1066298600
Directory	/workspace/1.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.906172346
Short name	T76
Test name
Test status
Simulation time	237833460900 ps
CPU time	2824.7 seconds
Started	Jul 23 04:43:39 PM PDT 24
Finished	Jul 23 05:31:00 PM PDT 24
Peak memory	264104 kb
Host	smart-9ebc765a-c86d-4075-991f-e551644c60d9
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906172346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.flash_ctrl_host_ctrl_arb.906172346
Directory	/workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_dir_rd.181911192
Short name	T78
Test name
Test status
Simulation time	119810000 ps
CPU time	56.93 seconds
Started	Jul 23 04:43:40 PM PDT 24
Finished	Jul 23 04:44:52 PM PDT 24
Peak memory	265128 kb
Host	smart-0fa20474-fe69-48cf-a0e2-11400396d2ad
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=181911192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.181911192
Directory	/workspace/1.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2688986222
Short name	T84
Test name
Test status
Simulation time	10019821800 ps
CPU time	198.32 seconds
Started	Jul 23 04:44:00 PM PDT 24
Finished	Jul 23 04:47:22 PM PDT 24
Peak memory	297148 kb
Host	smart-e2b522d4-0a8e-4dde-bd34-1ff0dec848da
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688986222 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.2688986222
Directory	/workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.3876333536
Short name	T309
Test name
Test status
Simulation time	48547900 ps
CPU time	13.61 seconds
Started	Jul 23 04:44:01 PM PDT 24
Finished	Jul 23 04:44:17 PM PDT 24
Peak memory	258900 kb
Host	smart-cb1d3138-0f43-423a-bb1c-7e8cdc50bf29
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876333536 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.3876333536
Directory	/workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma.4045756713
Short name	T851
Test name
Test status
Simulation time	275187379600 ps
CPU time	1984.49 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 05:17:00 PM PDT 24
Peak memory	260692 kb
Host	smart-a9a70e5f-1dfd-4572-b69f-bdab4e4fa251
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045756713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.flash_ctrl_hw_rma.4045756713
Directory	/workspace/1.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma_reset.3079313649
Short name	T1070
Test name
Test status
Simulation time	80148988000 ps
CPU time	866.13 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 04:58:22 PM PDT 24
Peak memory	265024 kb
Host	smart-dbf4aeac-ab68-4c82-9ce9-b7e6fe1207f8
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079313649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.flash_ctrl_hw_rma_reset.3079313649
Directory	/workspace/1.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_sec_otp.4025362151
Short name	T747
Test name
Test status
Simulation time	7866144200 ps
CPU time	205.92 seconds
Started	Jul 23 04:43:39 PM PDT 24
Finished	Jul 23 04:47:21 PM PDT 24
Peak memory	261080 kb
Host	smart-465a000c-f63d-4c66-a02e-cf11af8f0e41
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025362151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h w_sec_otp.4025362151
Directory	/workspace/1.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd.498708370
Short name	T53
Test name
Test status
Simulation time	4429018400 ps
CPU time	194.71 seconds
Started	Jul 23 04:43:49 PM PDT 24
Finished	Jul 23 04:47:13 PM PDT 24
Peak memory	284724 kb
Host	smart-175e8dca-76e1-4b47-ba27-8c0ca5e8714f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498708370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash _ctrl_intr_rd.498708370
Directory	/workspace/1.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.3832555019
Short name	T363
Test name
Test status
Simulation time	28026344100 ps
CPU time	277.11 seconds
Started	Jul 23 04:43:48 PM PDT 24
Finished	Jul 23 04:48:35 PM PDT 24
Peak memory	290984 kb
Host	smart-94e6f8f2-0287-4cab-87fe-475abf26140f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832555019 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.3832555019
Directory	/workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr.3220663380
Short name	T1110
Test name
Test status
Simulation time	33784196000 ps
CPU time	70.28 seconds
Started	Jul 23 04:43:48 PM PDT 24
Finished	Jul 23 04:45:07 PM PDT 24
Peak memory	265560 kb
Host	smart-4d49d7bd-2262-43bc-91ee-320174471a35
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220663380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.flash_ctrl_intr_wr.3220663380
Directory	/workspace/1.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.2114785847
Short name	T864
Test name
Test status
Simulation time	97753284100 ps
CPU time	236.91 seconds
Started	Jul 23 04:43:49 PM PDT 24
Finished	Jul 23 04:47:55 PM PDT 24
Peak memory	260376 kb
Host	smart-5f8e6da1-f929-4486-a8ac-f50f8c665304
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211 4785847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.2114785847
Directory	/workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_invalid_op.3435359960
Short name	T823
Test name
Test status
Simulation time	983746600 ps
CPU time	73.73 seconds
Started	Jul 23 04:43:40 PM PDT 24
Finished	Jul 23 04:45:09 PM PDT 24
Peak memory	260704 kb
Host	smart-0d84a7f1-5247-4faf-b3df-465f534db560
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435359960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.3435359960
Directory	/workspace/1.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_lcmgr_intg.1246728282
Short name	T466
Test name
Test status
Simulation time	18930900 ps
CPU time	13.46 seconds
Started	Jul 23 04:44:00 PM PDT 24
Finished	Jul 23 04:44:17 PM PDT 24
Peak memory	260028 kb
Host	smart-d0630a86-9ac6-4df5-8472-2a4ce26615ab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246728282 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.1246728282
Directory	/workspace/1.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mp_regions.461897645
Short name	T121
Test name
Test status
Simulation time	7009012900 ps
CPU time	500.26 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 04:52:16 PM PDT 24
Peak memory	274788 kb
Host	smart-ec0e6429-3aa0-4216-829f-5ee078a3309c
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461897645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.461897645
Directory	/workspace/1.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/1.flash_ctrl_otp_reset.2561600504
Short name	T348
Test name
Test status
Simulation time	35896800 ps
CPU time	110.45 seconds
Started	Jul 23 04:43:38 PM PDT 24
Finished	Jul 23 04:45:44 PM PDT 24
Peak memory	265292 kb
Host	smart-e526855d-dfcf-41f5-b7f9-4c60e5fc90ea
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561600504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot p_reset.2561600504
Directory	/workspace/1.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb.1869525436
Short name	T718
Test name
Test status
Simulation time	1393335000 ps
CPU time	172.03 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 04:46:47 PM PDT 24
Peak memory	263076 kb
Host	smart-530c5892-e01b-4fef-86e8-d5d80b6fea81
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1869525436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.1869525436
Directory	/workspace/1.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.3067142136
Short name	T234
Test name
Test status
Simulation time	16791300 ps
CPU time	14.15 seconds
Started	Jul 23 04:43:48 PM PDT 24
Finished	Jul 23 04:44:11 PM PDT 24
Peak memory	263032 kb
Host	smart-4540b777-51ce-4cb3-adf1-74742d96d2e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067142136 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3067142136
Directory	/workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_prog_reset.1710707520
Short name	T564
Test name
Test status
Simulation time	22156900 ps
CPU time	13.44 seconds
Started	Jul 23 04:43:52 PM PDT 24
Finished	Jul 23 04:44:13 PM PDT 24
Peak memory	265180 kb
Host	smart-b0dd3b87-3c6e-4282-8277-f5ba5ddbe775
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710707520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.flash_ctrl_prog_reset.1710707520
Directory	/workspace/1.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rand_ops.2070745189
Short name	T146
Test name
Test status
Simulation time	4271948500 ps
CPU time	934.36 seconds
Started	Jul 23 04:43:40 PM PDT 24
Finished	Jul 23 04:59:29 PM PDT 24
Peak memory	285468 kb
Host	smart-e671b55e-aafc-4d24-a8d5-a8c925475cb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2070745189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.2070745189
Directory	/workspace/1.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_buff_evict.460452175
Short name	T648
Test name
Test status
Simulation time	1384673200 ps
CPU time	178.3 seconds
Started	Jul 23 04:43:39 PM PDT 24
Finished	Jul 23 04:46:53 PM PDT 24
Peak memory	262636 kb
Host	smart-c4c4eaa9-e83c-4f5f-a409-951ae68d222c
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=460452175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.460452175
Directory	/workspace/1.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_intg.4454758
Short name	T596
Test name
Test status
Simulation time	112768300 ps
CPU time	31.69 seconds
Started	Jul 23 04:43:51 PM PDT 24
Finished	Jul 23 04:44:31 PM PDT 24
Peak memory	275680 kb
Host	smart-53480104-b899-4fea-9e61-cce5abfc0d7a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4454758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_rd_intg.4454758
Directory	/workspace/1.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.4049694426
Short name	T932
Test name
Test status
Simulation time	64523900 ps
CPU time	22.66 seconds
Started	Jul 23 04:43:50 PM PDT 24
Finished	Jul 23 04:44:21 PM PDT 24
Peak memory	264916 kb
Host	smart-533eda7b-3d75-434f-9bee-f6f0758f543d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049694426 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.4049694426
Directory	/workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.3028082881
Short name	T880
Test name
Test status
Simulation time	215993900 ps
CPU time	22.74 seconds
Started	Jul 23 04:43:49 PM PDT 24
Finished	Jul 23 04:44:21 PM PDT 24
Peak memory	265412 kb
Host	smart-7891eb48-da6b-47db-89f1-3565c915050b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028082881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl ash_ctrl_read_word_sweep_serr.3028082881
Directory	/workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rma_err.1519239160
Short name	T189
Test name
Test status
Simulation time	41783368200 ps
CPU time	923.8 seconds
Started	Jul 23 04:43:59 PM PDT 24
Finished	Jul 23 04:59:27 PM PDT 24
Peak memory	265004 kb
Host	smart-3fbd2ca1-cb80-49bb-96db-fcdbe310c742
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519239160 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.1519239160
Directory	/workspace/1.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro.2607288307
Short name	T624
Test name
Test status
Simulation time	1115935700 ps
CPU time	117.84 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 04:45:53 PM PDT 24
Peak memory	291280 kb
Host	smart-e556643c-0ec6-4e42-9f6e-6ff9ad2a05d1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607288307 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.flash_ctrl_ro.2607288307
Directory	/workspace/1.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_derr.603867677
Short name	T988
Test name
Test status
Simulation time	687056800 ps
CPU time	148.34 seconds
Started	Jul 23 04:43:51 PM PDT 24
Finished	Jul 23 04:46:28 PM PDT 24
Peak memory	281732 kb
Host	smart-ac4eb6f5-a81a-42b8-baa0-260ddf53bbc2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 603867677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.603867677
Directory	/workspace/1.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_serr.3030973503
Short name	T705
Test name
Test status
Simulation time	1246832800 ps
CPU time	127.47 seconds
Started	Jul 23 04:43:49 PM PDT 24
Finished	Jul 23 04:46:06 PM PDT 24
Peak memory	281804 kb
Host	smart-3a1b4c70-94dd-4d94-9fad-8dfc79f2b46b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030973503 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.3030973503
Directory	/workspace/1.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw.3105571105
Short name	T821
Test name
Test status
Simulation time	17231063400 ps
CPU time	703.35 seconds
Started	Jul 23 04:43:48 PM PDT 24
Finished	Jul 23 04:55:41 PM PDT 24
Peak memory	319244 kb
Host	smart-c9952ca8-2d5c-4518-9985-bdedfb17d532
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105571105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.flash_ctrl_rw.3105571105
Directory	/workspace/1.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_derr.4199651941
Short name	T241
Test name
Test status
Simulation time	16271415200 ps
CPU time	477.86 seconds
Started	Jul 23 04:43:49 PM PDT 24
Finished	Jul 23 04:51:56 PM PDT 24
Peak memory	315600 kb
Host	smart-68b61a16-b963-4e1d-9d34-544279f2867f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199651941 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.flash_ctrl_rw_derr.4199651941
Directory	/workspace/1.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_evict.3542227571
Short name	T646
Test name
Test status
Simulation time	30289500 ps
CPU time	31.56 seconds
Started	Jul 23 04:43:49 PM PDT 24
Finished	Jul 23 04:44:30 PM PDT 24
Peak memory	275724 kb
Host	smart-d751169b-f5f8-440f-b0d1-762e91aea401
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542227571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_rw_evict.3542227571
Directory	/workspace/1.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.3934503040
Short name	T579
Test name
Test status
Simulation time	66295100 ps
CPU time	31.24 seconds
Started	Jul 23 04:43:47 PM PDT 24
Finished	Jul 23 04:44:28 PM PDT 24
Peak memory	273564 kb
Host	smart-b5ad0c6a-2696-453b-b2e3-068e920c3e97
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934503040 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.3934503040
Directory	/workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_serr.1702444027
Short name	T935
Test name
Test status
Simulation time	60907944600 ps
CPU time	644.44 seconds
Started	Jul 23 04:43:53 PM PDT 24
Finished	Jul 23 04:54:44 PM PDT 24
Peak memory	320956 kb
Host	smart-d5fc3fcc-540e-468a-b529-f2f7500b75be
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702444027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s err.1702444027
Directory	/workspace/1.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_info_access.2063456347
Short name	T511
Test name
Test status
Simulation time	1481830500 ps
CPU time	66.56 seconds
Started	Jul 23 04:43:49 PM PDT 24
Finished	Jul 23 04:45:05 PM PDT 24
Peak memory	262632 kb
Host	smart-7967ed1f-27f4-4770-9be3-9d9c90b80e7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2063456347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.2063456347
Directory	/workspace/1.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_serr_address.3790918020
Short name	T590
Test name
Test status
Simulation time	1636143000 ps
CPU time	52.25 seconds
Started	Jul 23 04:43:49 PM PDT 24
Finished	Jul 23 04:44:50 PM PDT 24
Peak memory	265420 kb
Host	smart-c1e9e009-4ecd-45e7-9b09-f08f9b310530
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790918020 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_serr_address.3790918020
Directory	/workspace/1.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/1.flash_ctrl_serr_counter.3295220742
Short name	T849
Test name
Test status
Simulation time	3123442300 ps
CPU time	96.13 seconds
Started	Jul 23 04:43:50 PM PDT 24
Finished	Jul 23 04:45:35 PM PDT 24
Peak memory	274260 kb
Host	smart-e21a63b6-fb0e-44b4-b7a1-cff83adecc11
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295220742 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_serr_counter.3295220742
Directory	/workspace/1.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke.1770348292
Short name	T143
Test name
Test status
Simulation time	31820700 ps
CPU time	145.44 seconds
Started	Jul 23 04:43:40 PM PDT 24
Finished	Jul 23 04:46:21 PM PDT 24
Peak memory	276884 kb
Host	smart-a11c4e99-a6fc-4f9e-a631-dee19382037c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770348292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.1770348292
Directory	/workspace/1.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke_hw.4099687806
Short name	T800
Test name
Test status
Simulation time	16881000 ps
CPU time	26.65 seconds
Started	Jul 23 04:43:41 PM PDT 24
Finished	Jul 23 04:44:22 PM PDT 24
Peak memory	259536 kb
Host	smart-6171caf7-ba81-4d76-a468-6420057d02d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4099687806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.4099687806
Directory	/workspace/1.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_stress_all.1137530501
Short name	T532
Test name
Test status
Simulation time	453023900 ps
CPU time	1549.73 seconds
Started	Jul 23 04:43:51 PM PDT 24
Finished	Jul 23 05:09:49 PM PDT 24
Peak memory	289728 kb
Host	smart-dca12e74-065f-4dfb-8c51-f3bfae9b1f15
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137530501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres s_all.1137530501
Directory	/workspace/1.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sw_op.3484233271
Short name	T1035
Test name
Test status
Simulation time	86383300 ps
CPU time	26.72 seconds
Started	Jul 23 04:43:42 PM PDT 24
Finished	Jul 23 04:44:22 PM PDT 24
Peak memory	259896 kb
Host	smart-eaca39ce-1364-4968-a188-25e26b921be8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3484233271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.3484233271
Directory	/workspace/1.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_wo.3284753420
Short name	T937
Test name
Test status
Simulation time	2257670900 ps
CPU time	191.35 seconds
Started	Jul 23 04:43:40 PM PDT 24
Finished	Jul 23 04:47:07 PM PDT 24
Peak memory	265272 kb
Host	smart-ca0db6a8-ddc1-475c-90a2-2edfb55186c7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284753420 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.flash_ctrl_wo.3284753420
Directory	/workspace/1.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/1.flash_ctrl_wr_intg.2225943999
Short name	T249
Test name
Test status
Simulation time	45162200 ps
CPU time	15.19 seconds
Started	Jul 23 04:43:50 PM PDT 24
Finished	Jul 23 04:44:14 PM PDT 24
Peak memory	260768 kb
Host	smart-3f6af243-7838-4c23-b0a7-85367a8c8871
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225943999 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.2225943999
Directory	/workspace/1.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/10.flash_ctrl_alert_test.2954996212
Short name	T545
Test name
Test status
Simulation time	39040200 ps
CPU time	13.96 seconds
Started	Jul 23 04:45:15 PM PDT 24
Finished	Jul 23 04:45:30 PM PDT 24
Peak memory	258236 kb
Host	smart-76634942-d5f3-461d-9204-f31ce5b7f86c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954996212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test. 2954996212
Directory	/workspace/10.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.flash_ctrl_connect.763828807
Short name	T1012
Test name
Test status
Simulation time	117566500 ps
CPU time	13.27 seconds
Started	Jul 23 04:45:15 PM PDT 24
Finished	Jul 23 04:45:30 PM PDT 24
Peak memory	274836 kb
Host	smart-1d51cb79-0347-45ea-bbde-654054c04b8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=763828807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.763828807
Directory	/workspace/10.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/10.flash_ctrl_disable.350688265
Short name	T193
Test name
Test status
Simulation time	11935200 ps
CPU time	21.48 seconds
Started	Jul 23 04:45:14 PM PDT 24
Finished	Jul 23 04:45:37 PM PDT 24
Peak memory	273576 kb
Host	smart-c714d851-579b-473f-90e9-72785243a188
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350688265 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_disable.350688265
Directory	/workspace/10.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.3499140223
Short name	T743
Test name
Test status
Simulation time	10033168900 ps
CPU time	53.16 seconds
Started	Jul 23 04:45:15 PM PDT 24
Finished	Jul 23 04:46:10 PM PDT 24
Peak memory	282472 kb
Host	smart-cdb69dba-9ade-478f-a932-874b036b4846
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499140223 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.3499140223
Directory	/workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_rma_reset.2907085994
Short name	T192
Test name
Test status
Simulation time	40125531500 ps
CPU time	885.89 seconds
Started	Jul 23 04:45:07 PM PDT 24
Finished	Jul 23 04:59:55 PM PDT 24
Peak memory	264328 kb
Host	smart-81256060-aa91-45cf-b062-f6a53312dbc9
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907085994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 10.flash_ctrl_hw_rma_reset.2907085994
Directory	/workspace/10.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_sec_otp.204220049
Short name	T561
Test name
Test status
Simulation time	16101416000 ps
CPU time	102.54 seconds
Started	Jul 23 04:45:08 PM PDT 24
Finished	Jul 23 04:46:52 PM PDT 24
Peak memory	260752 kb
Host	smart-240f40b1-f4f1-4d71-ac0f-b1e78fe47ff2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204220049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_h w_sec_otp.204220049
Directory	/workspace/10.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd.2964808826
Short name	T301
Test name
Test status
Simulation time	20123390900 ps
CPU time	231.69 seconds
Started	Jul 23 04:45:07 PM PDT 24
Finished	Jul 23 04:49:00 PM PDT 24
Peak memory	284756 kb
Host	smart-5d975769-a587-4659-a8e2-c775a1df28d5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964808826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla sh_ctrl_intr_rd.2964808826
Directory	/workspace/10.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.144726624
Short name	T362
Test name
Test status
Simulation time	23236234600 ps
CPU time	271.37 seconds
Started	Jul 23 04:45:07 PM PDT 24
Finished	Jul 23 04:49:41 PM PDT 24
Peak memory	289976 kb
Host	smart-142cc4b1-5ec8-481e-a2ad-fde873767343
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144726624 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.144726624
Directory	/workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/10.flash_ctrl_invalid_op.3088224767
Short name	T124
Test name
Test status
Simulation time	2963712100 ps
CPU time	89.86 seconds
Started	Jul 23 04:45:05 PM PDT 24
Finished	Jul 23 04:46:36 PM PDT 24
Peak memory	263216 kb
Host	smart-e422f170-aa8d-4cb9-b8c6-2ff76151e000
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088224767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.3 088224767
Directory	/workspace/10.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/10.flash_ctrl_lcmgr_intg.3826431485
Short name	T649
Test name
Test status
Simulation time	24738600 ps
CPU time	13.44 seconds
Started	Jul 23 04:45:17 PM PDT 24
Finished	Jul 23 04:45:32 PM PDT 24
Peak memory	265048 kb
Host	smart-db365735-913f-4a86-aa61-da61606eb9da
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826431485 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.3826431485
Directory	/workspace/10.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/10.flash_ctrl_mp_regions.261397524
Short name	T150
Test name
Test status
Simulation time	11686158000 ps
CPU time	271.37 seconds
Started	Jul 23 04:45:08 PM PDT 24
Finished	Jul 23 04:49:42 PM PDT 24
Peak memory	274652 kb
Host	smart-db55dcf7-b973-47fb-b24d-b46e878f8cf0
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261397524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.261397524
Directory	/workspace/10.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/10.flash_ctrl_otp_reset.1488647630
Short name	T8
Test name
Test status
Simulation time	38359700 ps
CPU time	132.26 seconds
Started	Jul 23 04:45:06 PM PDT 24
Finished	Jul 23 04:47:20 PM PDT 24
Peak memory	261208 kb
Host	smart-694b7a3e-cc16-4cc0-967f-d4a323eb2294
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488647630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o tp_reset.1488647630
Directory	/workspace/10.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_phy_arb.2478645827
Short name	T635
Test name
Test status
Simulation time	113535100 ps
CPU time	396 seconds
Started	Jul 23 04:45:06 PM PDT 24
Finished	Jul 23 04:51:44 PM PDT 24
Peak memory	263096 kb
Host	smart-efa0fd98-521b-43c1-86fc-a1dbd5b18d7d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2478645827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.2478645827
Directory	/workspace/10.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/10.flash_ctrl_prog_reset.150168715
Short name	T822
Test name
Test status
Simulation time	23932600 ps
CPU time	13.57 seconds
Started	Jul 23 04:45:06 PM PDT 24
Finished	Jul 23 04:45:21 PM PDT 24
Peak memory	265280 kb
Host	smart-c022b6bb-083c-4c53-9b51-1ae8aba93fb0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150168715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.flash_ctrl_prog_reset.150168715
Directory	/workspace/10.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rand_ops.1356167827
Short name	T1080
Test name
Test status
Simulation time	754731700 ps
CPU time	933.49 seconds
Started	Jul 23 04:45:08 PM PDT 24
Finished	Jul 23 05:00:44 PM PDT 24
Peak memory	284716 kb
Host	smart-9df1724b-57a9-4423-a782-cdd1a9fdc647
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356167827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.1356167827
Directory	/workspace/10.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/10.flash_ctrl_re_evict.2163658582
Short name	T426
Test name
Test status
Simulation time	301057800 ps
CPU time	34.36 seconds
Started	Jul 23 04:45:15 PM PDT 24
Finished	Jul 23 04:45:51 PM PDT 24
Peak memory	275632 kb
Host	smart-6655a9bf-dc64-4c18-b04f-fc766cfbc8a9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163658582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl ash_ctrl_re_evict.2163658582
Directory	/workspace/10.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/10.flash_ctrl_ro.1556256885
Short name	T914
Test name
Test status
Simulation time	454327200 ps
CPU time	97.24 seconds
Started	Jul 23 04:45:07 PM PDT 24
Finished	Jul 23 04:46:46 PM PDT 24
Peak memory	281756 kb
Host	smart-927c9440-d99a-4f0a-8522-f6843be18ae2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556256885 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 10.flash_ctrl_ro.1556256885
Directory	/workspace/10.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw.3827773600
Short name	T725
Test name
Test status
Simulation time	5092592600 ps
CPU time	568.5 seconds
Started	Jul 23 04:45:07 PM PDT 24
Finished	Jul 23 04:54:37 PM PDT 24
Peak memory	314244 kb
Host	smart-58419b84-f833-496d-9899-aa5a42f29cca
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827773600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.flash_ctrl_rw.3827773600
Directory	/workspace/10.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict.515523236
Short name	T993
Test name
Test status
Simulation time	32909200 ps
CPU time	29.06 seconds
Started	Jul 23 04:45:07 PM PDT 24
Finished	Jul 23 04:45:38 PM PDT 24
Peak memory	268584 kb
Host	smart-a05e79f1-2d21-4135-9a98-48ff2680ea31
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515523236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla sh_ctrl_rw_evict.515523236
Directory	/workspace/10.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.752481129
Short name	T1095
Test name
Test status
Simulation time	44738200 ps
CPU time	28.81 seconds
Started	Jul 23 04:45:18 PM PDT 24
Finished	Jul 23 04:45:49 PM PDT 24
Peak memory	268472 kb
Host	smart-59f5f2f9-6a9a-454c-b9fa-1e3b6458ce57
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752481129 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.752481129
Directory	/workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/10.flash_ctrl_sec_info_access.2688691173
Short name	T964
Test name
Test status
Simulation time	2181146100 ps
CPU time	51.38 seconds
Started	Jul 23 04:45:17 PM PDT 24
Finished	Jul 23 04:46:10 PM PDT 24
Peak memory	263732 kb
Host	smart-6d5a1b51-9ae7-45f5-8c66-f33142b4580b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2688691173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.2688691173
Directory	/workspace/10.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/10.flash_ctrl_smoke.1685051112
Short name	T479
Test name
Test status
Simulation time	256797600 ps
CPU time	170.64 seconds
Started	Jul 23 04:45:07 PM PDT 24
Finished	Jul 23 04:48:00 PM PDT 24
Peak memory	277544 kb
Host	smart-7f2ed3c6-2492-4340-91ca-cbda262708c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685051112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.1685051112
Directory	/workspace/10.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.flash_ctrl_wo.1143348150
Short name	T574
Test name
Test status
Simulation time	7700259300 ps
CPU time	165.09 seconds
Started	Jul 23 04:45:07 PM PDT 24
Finished	Jul 23 04:47:54 PM PDT 24
Peak memory	259956 kb
Host	smart-f40b5a5d-f521-4843-8cac-ccb8bdaad217
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143348150 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.flash_ctrl_wo.1143348150
Directory	/workspace/10.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/11.flash_ctrl_alert_test.1067451074
Short name	T454
Test name
Test status
Simulation time	32799800 ps
CPU time	13.4 seconds
Started	Jul 23 04:45:35 PM PDT 24
Finished	Jul 23 04:45:50 PM PDT 24
Peak memory	265000 kb
Host	smart-fb62a62a-3a42-46db-a3cb-2ec7a67c30e6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067451074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test. 1067451074
Directory	/workspace/11.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.flash_ctrl_connect.195296740
Short name	T543
Test name
Test status
Simulation time	29909400 ps
CPU time	16.15 seconds
Started	Jul 23 04:45:15 PM PDT 24
Finished	Jul 23 04:45:33 PM PDT 24
Peak memory	284412 kb
Host	smart-b6afc4f7-d89b-4d40-989b-438410c5f49f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=195296740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.195296740
Directory	/workspace/11.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/11.flash_ctrl_disable.2477513263
Short name	T655
Test name
Test status
Simulation time	33343300 ps
CPU time	20.69 seconds
Started	Jul 23 04:45:15 PM PDT 24
Finished	Jul 23 04:45:37 PM PDT 24
Peak memory	274760 kb
Host	smart-e83eb9d8-f910-40f8-a32f-4df86d4c2469
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477513263 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_disable.2477513263
Directory	/workspace/11.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2003365897
Short name	T570
Test name
Test status
Simulation time	10018940400 ps
CPU time	93.98 seconds
Started	Jul 23 04:45:18 PM PDT 24
Finished	Jul 23 04:46:53 PM PDT 24
Peak memory	332224 kb
Host	smart-4aaab36e-ed9a-4a93-8282-b07e60c76155
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003365897 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.2003365897
Directory	/workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.1738416305
Short name	T858
Test name
Test status
Simulation time	21722900 ps
CPU time	13.71 seconds
Started	Jul 23 04:45:18 PM PDT 24
Finished	Jul 23 04:45:33 PM PDT 24
Peak memory	258772 kb
Host	smart-180c2e62-fde6-4c9d-bd61-f27274069081
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738416305 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.1738416305
Directory	/workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_rma_reset.2581909059
Short name	T201
Test name
Test status
Simulation time	240227162300 ps
CPU time	1044.86 seconds
Started	Jul 23 04:45:18 PM PDT 24
Finished	Jul 23 05:02:45 PM PDT 24
Peak memory	265100 kb
Host	smart-42635f28-d03f-4a94-b7f6-c1e93f000226
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581909059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 11.flash_ctrl_hw_rma_reset.2581909059
Directory	/workspace/11.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_sec_otp.204692308
Short name	T333
Test name
Test status
Simulation time	9928846500 ps
CPU time	62.7 seconds
Started	Jul 23 04:45:13 PM PDT 24
Finished	Jul 23 04:46:17 PM PDT 24
Peak memory	261044 kb
Host	smart-24076333-1c0a-40f2-ac45-434f76f7d0c5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204692308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_h w_sec_otp.204692308
Directory	/workspace/11.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd.2179401599
Short name	T578
Test name
Test status
Simulation time	964193100 ps
CPU time	128.19 seconds
Started	Jul 23 04:45:16 PM PDT 24
Finished	Jul 23 04:47:26 PM PDT 24
Peak memory	291444 kb
Host	smart-c4446237-131b-4288-b7a1-2f8d4f5e922b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179401599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla sh_ctrl_intr_rd.2179401599
Directory	/workspace/11.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3171757033
Short name	T491
Test name
Test status
Simulation time	57995002600 ps
CPU time	256.8 seconds
Started	Jul 23 04:45:17 PM PDT 24
Finished	Jul 23 04:49:36 PM PDT 24
Peak memory	290048 kb
Host	smart-779415f9-e666-41ba-aa8b-46ccc9c741b6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171757033 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.3171757033
Directory	/workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/11.flash_ctrl_invalid_op.3908471469
Short name	T587
Test name
Test status
Simulation time	1961126300 ps
CPU time	88.52 seconds
Started	Jul 23 04:45:13 PM PDT 24
Finished	Jul 23 04:46:43 PM PDT 24
Peak memory	262564 kb
Host	smart-999fd5dd-a5ba-4b4f-9c5b-a5b96c0b84a5
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908471469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.3 908471469
Directory	/workspace/11.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/11.flash_ctrl_mp_regions.2136138368
Short name	T787
Test name
Test status
Simulation time	49471913900 ps
CPU time	328.47 seconds
Started	Jul 23 04:45:15 PM PDT 24
Finished	Jul 23 04:50:45 PM PDT 24
Peak memory	274684 kb
Host	smart-0619a3a1-237a-4a57-97e4-0991b9bfe9d3
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136138368 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.2136138368
Directory	/workspace/11.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/11.flash_ctrl_otp_reset.2674807176
Short name	T107
Test name
Test status
Simulation time	53641300 ps
CPU time	129.39 seconds
Started	Jul 23 04:45:18 PM PDT 24
Finished	Jul 23 04:47:29 PM PDT 24
Peak memory	261272 kb
Host	smart-a5c036a1-466f-4d3c-9bc6-a6fdb42ee42a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674807176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o tp_reset.2674807176
Directory	/workspace/11.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_phy_arb.3219479444
Short name	T464
Test name
Test status
Simulation time	55186100 ps
CPU time	186.14 seconds
Started	Jul 23 04:45:15 PM PDT 24
Finished	Jul 23 04:48:22 PM PDT 24
Peak memory	263096 kb
Host	smart-10a86bae-8079-4573-860d-13a2161399e1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3219479444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.3219479444
Directory	/workspace/11.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/11.flash_ctrl_prog_reset.4017664992
Short name	T967
Test name
Test status
Simulation time	63975600 ps
CPU time	14.21 seconds
Started	Jul 23 04:45:17 PM PDT 24
Finished	Jul 23 04:45:33 PM PDT 24
Peak memory	259132 kb
Host	smart-827e5738-1f23-4158-9bec-75a3c9cb0dba
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017664992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.flash_ctrl_prog_reset.4017664992
Directory	/workspace/11.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rand_ops.998967628
Short name	T133
Test name
Test status
Simulation time	41275300 ps
CPU time	221.76 seconds
Started	Jul 23 04:45:16 PM PDT 24
Finished	Jul 23 04:48:59 PM PDT 24
Peak memory	271648 kb
Host	smart-30150ff0-e224-44d7-b527-e340ceee8c8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=998967628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.998967628
Directory	/workspace/11.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/11.flash_ctrl_re_evict.1707816300
Short name	T955
Test name
Test status
Simulation time	118769400 ps
CPU time	35.04 seconds
Started	Jul 23 04:45:16 PM PDT 24
Finished	Jul 23 04:45:53 PM PDT 24
Peak memory	275620 kb
Host	smart-7aee9856-8663-40bf-b9bf-2d3f0c791a47
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707816300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl ash_ctrl_re_evict.1707816300
Directory	/workspace/11.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/11.flash_ctrl_ro.2948132399
Short name	T842
Test name
Test status
Simulation time	1135961800 ps
CPU time	127.74 seconds
Started	Jul 23 04:45:15 PM PDT 24
Finished	Jul 23 04:47:25 PM PDT 24
Peak memory	281724 kb
Host	smart-c047ef5f-8633-47e0-a371-2bff9eae5344
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948132399 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 11.flash_ctrl_ro.2948132399
Directory	/workspace/11.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict.3008771499
Short name	T433
Test name
Test status
Simulation time	53027600 ps
CPU time	28.3 seconds
Started	Jul 23 04:45:17 PM PDT 24
Finished	Jul 23 04:45:47 PM PDT 24
Peak memory	275632 kb
Host	smart-50a882ea-7fcd-4efd-9935-b0dedb9a64c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008771499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl ash_ctrl_rw_evict.3008771499
Directory	/workspace/11.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/11.flash_ctrl_sec_info_access.1146252989
Short name	T1112
Test name
Test status
Simulation time	21644033300 ps
CPU time	73.64 seconds
Started	Jul 23 04:45:17 PM PDT 24
Finished	Jul 23 04:46:33 PM PDT 24
Peak memory	264672 kb
Host	smart-c95bb190-e194-4ef6-a195-abdeae7a6667
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1146252989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.1146252989
Directory	/workspace/11.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/11.flash_ctrl_smoke.3783824282
Short name	T526
Test name
Test status
Simulation time	41794700 ps
CPU time	73.68 seconds
Started	Jul 23 04:45:14 PM PDT 24
Finished	Jul 23 04:46:30 PM PDT 24
Peak memory	275396 kb
Host	smart-73960116-9bae-4a21-a87f-ad124096e376
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3783824282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.3783824282
Directory	/workspace/11.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.flash_ctrl_wo.973881883
Short name	T968
Test name
Test status
Simulation time	7599648200 ps
CPU time	162.31 seconds
Started	Jul 23 04:45:14 PM PDT 24
Finished	Jul 23 04:47:58 PM PDT 24
Peak memory	260000 kb
Host	smart-bf898a16-2bd4-4fea-a93e-9ce6ae171d19
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973881883 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 11.flash_ctrl_wo.973881883
Directory	/workspace/11.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/12.flash_ctrl_alert_test.2913409769
Short name	T749
Test name
Test status
Simulation time	326523700 ps
CPU time	13.82 seconds
Started	Jul 23 04:45:24 PM PDT 24
Finished	Jul 23 04:45:40 PM PDT 24
Peak memory	258340 kb
Host	smart-8301147a-81ef-415f-9c21-6e64122d9ff9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913409769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test. 2913409769
Directory	/workspace/12.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.flash_ctrl_connect.494660345
Short name	T487
Test name
Test status
Simulation time	55087200 ps
CPU time	15.65 seconds
Started	Jul 23 04:45:23 PM PDT 24
Finished	Jul 23 04:45:40 PM PDT 24
Peak memory	274996 kb
Host	smart-bbe7349f-2505-4c0b-9928-f52c8495d7c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=494660345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.494660345
Directory	/workspace/12.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.1419081772
Short name	T181
Test name
Test status
Simulation time	10018123000 ps
CPU time	99.34 seconds
Started	Jul 23 04:45:24 PM PDT 24
Finished	Jul 23 04:47:06 PM PDT 24
Peak memory	341088 kb
Host	smart-8c4781f7-2104-4eb1-b08b-a9f7307a289b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419081772 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.1419081772
Directory	/workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.2689289348
Short name	T235
Test name
Test status
Simulation time	47435400 ps
CPU time	13.44 seconds
Started	Jul 23 04:45:27 PM PDT 24
Finished	Jul 23 04:45:43 PM PDT 24
Peak memory	264920 kb
Host	smart-08f9b0d2-492b-4780-93d2-b1db62caa4d6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689289348 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.2689289348
Directory	/workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_rma_reset.716984493
Short name	T687
Test name
Test status
Simulation time	40129039300 ps
CPU time	889.88 seconds
Started	Jul 23 04:45:23 PM PDT 24
Finished	Jul 23 05:00:15 PM PDT 24
Peak memory	264168 kb
Host	smart-bc8ba8b3-a61c-4da0-8b35-619621b19cf8
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716984493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.flash_ctrl_hw_rma_reset.716984493
Directory	/workspace/12.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_sec_otp.2263521797
Short name	T1031
Test name
Test status
Simulation time	1510917600 ps
CPU time	70.09 seconds
Started	Jul 23 04:45:24 PM PDT 24
Finished	Jul 23 04:46:36 PM PDT 24
Peak memory	263256 kb
Host	smart-fb264b72-15f6-46e2-aa8a-35ace56bc5ae
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263521797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ hw_sec_otp.2263521797
Directory	/workspace/12.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd.1102709803
Short name	T824
Test name
Test status
Simulation time	2291897200 ps
CPU time	133.57 seconds
Started	Jul 23 04:45:25 PM PDT 24
Finished	Jul 23 04:47:41 PM PDT 24
Peak memory	293652 kb
Host	smart-ef0737d7-a8cd-415e-bf72-8a3100b22964
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102709803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla sh_ctrl_intr_rd.1102709803
Directory	/workspace/12.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.2809269190
Short name	T419
Test name
Test status
Simulation time	93327224200 ps
CPU time	241.01 seconds
Started	Jul 23 04:45:24 PM PDT 24
Finished	Jul 23 04:49:27 PM PDT 24
Peak memory	292828 kb
Host	smart-5a178920-1cd5-432b-90bc-393057fc8570
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809269190 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.2809269190
Directory	/workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/12.flash_ctrl_invalid_op.1318599747
Short name	T662
Test name
Test status
Simulation time	1509013700 ps
CPU time	82.7 seconds
Started	Jul 23 04:45:27 PM PDT 24
Finished	Jul 23 04:46:52 PM PDT 24
Peak memory	260484 kb
Host	smart-f307bc5a-d111-4d33-8864-896365b4def6
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318599747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.1 318599747
Directory	/workspace/12.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.2815198996
Short name	T723
Test name
Test status
Simulation time	15038400 ps
CPU time	13.38 seconds
Started	Jul 23 04:45:25 PM PDT 24
Finished	Jul 23 04:45:40 PM PDT 24
Peak memory	260868 kb
Host	smart-26718ca3-1975-47c1-b874-e42ea95fde55
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815198996 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.2815198996
Directory	/workspace/12.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/12.flash_ctrl_mp_regions.100386778
Short name	T123
Test name
Test status
Simulation time	20481284500 ps
CPU time	223.77 seconds
Started	Jul 23 04:45:27 PM PDT 24
Finished	Jul 23 04:49:13 PM PDT 24
Peak memory	274420 kb
Host	smart-061022ae-c6c9-4488-a0f2-f9e018d737af
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100386778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.100386778
Directory	/workspace/12.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/12.flash_ctrl_otp_reset.1141164822
Short name	T1069
Test name
Test status
Simulation time	148107300 ps
CPU time	129.78 seconds
Started	Jul 23 04:45:23 PM PDT 24
Finished	Jul 23 04:47:34 PM PDT 24
Peak memory	259928 kb
Host	smart-e7a69ffd-5c91-4f2e-a16d-c06c3b6ff215
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141164822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o tp_reset.1141164822
Directory	/workspace/12.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_phy_arb.2931121422
Short name	T773
Test name
Test status
Simulation time	2125258600 ps
CPU time	557.42 seconds
Started	Jul 23 04:45:17 PM PDT 24
Finished	Jul 23 04:54:36 PM PDT 24
Peak memory	262868 kb
Host	smart-d45e5901-dc21-4699-b48a-e8d2748e6183
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2931121422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.2931121422
Directory	/workspace/12.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/12.flash_ctrl_prog_reset.2467720569
Short name	T906
Test name
Test status
Simulation time	20734500 ps
CPU time	13.49 seconds
Started	Jul 23 04:45:23 PM PDT 24
Finished	Jul 23 04:45:37 PM PDT 24
Peak memory	259316 kb
Host	smart-e869c5bd-dfa4-472d-b4b9-d3efaa8e20e2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467720569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.flash_ctrl_prog_reset.2467720569
Directory	/workspace/12.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_re_evict.1452986650
Short name	T135
Test name
Test status
Simulation time	251438000 ps
CPU time	35.58 seconds
Started	Jul 23 04:45:26 PM PDT 24
Finished	Jul 23 04:46:04 PM PDT 24
Peak memory	273552 kb
Host	smart-30381223-a13d-42f7-be58-a8ee69658a91
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452986650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl ash_ctrl_re_evict.1452986650
Directory	/workspace/12.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/12.flash_ctrl_ro.2369184378
Short name	T730
Test name
Test status
Simulation time	638043200 ps
CPU time	104.63 seconds
Started	Jul 23 04:45:23 PM PDT 24
Finished	Jul 23 04:47:10 PM PDT 24
Peak memory	281784 kb
Host	smart-46a0e60e-e9f2-4376-971e-3f14a09b0156
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369184378 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 12.flash_ctrl_ro.2369184378
Directory	/workspace/12.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw.596589028
Short name	T958
Test name
Test status
Simulation time	14089958000 ps
CPU time	555.63 seconds
Started	Jul 23 04:45:26 PM PDT 24
Finished	Jul 23 04:54:44 PM PDT 24
Peak memory	309788 kb
Host	smart-0be082e3-82a3-403d-8115-77319f26cf1e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596589028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.596589028
Directory	/workspace/12.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw_evict.3875448435
Short name	T481
Test name
Test status
Simulation time	136231700 ps
CPU time	30.88 seconds
Started	Jul 23 04:45:24 PM PDT 24
Finished	Jul 23 04:45:57 PM PDT 24
Peak memory	275632 kb
Host	smart-72a0e77e-1cf9-45ed-a80e-c47869cf1f64
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875448435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl ash_ctrl_rw_evict.3875448435
Directory	/workspace/12.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.1814519582
Short name	T520
Test name
Test status
Simulation time	98427500 ps
CPU time	30.75 seconds
Started	Jul 23 04:45:25 PM PDT 24
Finished	Jul 23 04:45:58 PM PDT 24
Peak memory	268464 kb
Host	smart-d8201e03-53c8-4162-95dc-d06bc2b2ac03
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814519582 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.1814519582
Directory	/workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/12.flash_ctrl_smoke.2340043500
Short name	T462
Test name
Test status
Simulation time	46624500 ps
CPU time	169.41 seconds
Started	Jul 23 04:45:18 PM PDT 24
Finished	Jul 23 04:48:09 PM PDT 24
Peak memory	279196 kb
Host	smart-020da4e7-63e0-461c-b70c-c271377d5021
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2340043500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2340043500
Directory	/workspace/12.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.flash_ctrl_alert_test.2783949235
Short name	T939
Test name
Test status
Simulation time	123051300 ps
CPU time	14.11 seconds
Started	Jul 23 04:45:37 PM PDT 24
Finished	Jul 23 04:45:53 PM PDT 24
Peak memory	258364 kb
Host	smart-e7220286-101c-43b4-a8dc-dee06681a630
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783949235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test. 2783949235
Directory	/workspace/13.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.flash_ctrl_connect.4116434100
Short name	T536
Test name
Test status
Simulation time	15481000 ps
CPU time	16.35 seconds
Started	Jul 23 04:45:38 PM PDT 24
Finished	Jul 23 04:45:56 PM PDT 24
Peak memory	284264 kb
Host	smart-0540caca-28af-44de-aff1-963a3e9099ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4116434100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.4116434100
Directory	/workspace/13.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/13.flash_ctrl_disable.4231384676
Short name	T195
Test name
Test status
Simulation time	15957600 ps
CPU time	21.79 seconds
Started	Jul 23 04:45:38 PM PDT 24
Finished	Jul 23 04:46:02 PM PDT 24
Peak memory	273520 kb
Host	smart-3e5f727a-3221-4412-9cf9-b6c157671330
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231384676 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_disable.4231384676
Directory	/workspace/13.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.1399338408
Short name	T1061
Test name
Test status
Simulation time	10011992100 ps
CPU time	142.93 seconds
Started	Jul 23 04:45:36 PM PDT 24
Finished	Jul 23 04:48:00 PM PDT 24
Peak memory	385664 kb
Host	smart-26f4568e-36c4-454a-a5f5-6f3ef75bd097
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399338408 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.1399338408
Directory	/workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.3907345003
Short name	T310
Test name
Test status
Simulation time	15896700 ps
CPU time	13.37 seconds
Started	Jul 23 04:45:37 PM PDT 24
Finished	Jul 23 04:45:53 PM PDT 24
Peak memory	258732 kb
Host	smart-95fff8c4-fc20-4494-b48c-1e1be3b6308c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907345003 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3907345003
Directory	/workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_rma_reset.171184650
Short name	T949
Test name
Test status
Simulation time	40123573100 ps
CPU time	861.2 seconds
Started	Jul 23 04:45:26 PM PDT 24
Finished	Jul 23 04:59:49 PM PDT 24
Peak memory	264548 kb
Host	smart-3ff27624-8ef5-448e-b1bb-2654384252a3
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171184650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.flash_ctrl_hw_rma_reset.171184650
Directory	/workspace/13.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_sec_otp.112399882
Short name	T755
Test name
Test status
Simulation time	7024014200 ps
CPU time	122.04 seconds
Started	Jul 23 04:45:26 PM PDT 24
Finished	Jul 23 04:47:30 PM PDT 24
Peak memory	262776 kb
Host	smart-9b597d81-d4ac-4562-a67b-1ba9c5234078
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112399882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_h w_sec_otp.112399882
Directory	/workspace/13.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd.2788730294
Short name	T862
Test name
Test status
Simulation time	702455800 ps
CPU time	108.42 seconds
Started	Jul 23 04:45:37 PM PDT 24
Finished	Jul 23 04:47:27 PM PDT 24
Peak memory	294204 kb
Host	smart-f88acd5c-2925-47a2-b3fe-b1b37154b58d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788730294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla sh_ctrl_intr_rd.2788730294
Directory	/workspace/13.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.2392264911
Short name	T1044
Test name
Test status
Simulation time	15854347100 ps
CPU time	267.94 seconds
Started	Jul 23 04:45:35 PM PDT 24
Finished	Jul 23 04:50:05 PM PDT 24
Peak memory	293136 kb
Host	smart-2455d181-2843-4fb0-90c5-eca1ce757e80
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392264911 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.2392264911
Directory	/workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/13.flash_ctrl_mp_regions.3878157690
Short name	T1030
Test name
Test status
Simulation time	83634808300 ps
CPU time	317.24 seconds
Started	Jul 23 04:45:37 PM PDT 24
Finished	Jul 23 04:50:57 PM PDT 24
Peak memory	275372 kb
Host	smart-e8f5dfe9-3063-450d-ab15-d4bc4d7d3431
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878157690 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.3878157690
Directory	/workspace/13.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/13.flash_ctrl_otp_reset.1329470652
Short name	T853
Test name
Test status
Simulation time	157603000 ps
CPU time	110.57 seconds
Started	Jul 23 04:45:38 PM PDT 24
Finished	Jul 23 04:47:31 PM PDT 24
Peak memory	261236 kb
Host	smart-d96dde65-2f2e-4325-890c-fd066b82350d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329470652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o tp_reset.1329470652
Directory	/workspace/13.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_phy_arb.959484578
Short name	T670
Test name
Test status
Simulation time	4374883900 ps
CPU time	293.69 seconds
Started	Jul 23 04:45:24 PM PDT 24
Finished	Jul 23 04:50:20 PM PDT 24
Peak memory	263004 kb
Host	smart-3ff2a73a-561e-45df-a859-223e4b40cf3e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=959484578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.959484578
Directory	/workspace/13.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/13.flash_ctrl_prog_reset.3839392875
Short name	T640
Test name
Test status
Simulation time	45567300 ps
CPU time	15.43 seconds
Started	Jul 23 04:45:37 PM PDT 24
Finished	Jul 23 04:45:55 PM PDT 24
Peak memory	259512 kb
Host	smart-27d6c378-e67f-4282-99eb-417d914c061d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839392875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.flash_ctrl_prog_reset.3839392875
Directory	/workspace/13.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rand_ops.2557221313
Short name	T1102
Test name
Test status
Simulation time	245012200 ps
CPU time	252.33 seconds
Started	Jul 23 04:45:24 PM PDT 24
Finished	Jul 23 04:49:39 PM PDT 24
Peak memory	275628 kb
Host	smart-a671b8ef-d005-4757-b0ec-9d46260f9fed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2557221313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.2557221313
Directory	/workspace/13.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/13.flash_ctrl_re_evict.4041150654
Short name	T424
Test name
Test status
Simulation time	115323500 ps
CPU time	33.9 seconds
Started	Jul 23 04:45:38 PM PDT 24
Finished	Jul 23 04:46:14 PM PDT 24
Peak memory	275548 kb
Host	smart-168b2437-6414-4caa-a70a-8c85762e37e7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041150654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl ash_ctrl_re_evict.4041150654
Directory	/workspace/13.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/13.flash_ctrl_ro.1131589014
Short name	T1075
Test name
Test status
Simulation time	2311796800 ps
CPU time	124.54 seconds
Started	Jul 23 04:45:36 PM PDT 24
Finished	Jul 23 04:47:43 PM PDT 24
Peak memory	281704 kb
Host	smart-35f186aa-8506-4ed7-a79f-99c4f86a710f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131589014 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 13.flash_ctrl_ro.1131589014
Directory	/workspace/13.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw.1587113588
Short name	T874
Test name
Test status
Simulation time	3583314700 ps
CPU time	496.89 seconds
Started	Jul 23 04:45:38 PM PDT 24
Finished	Jul 23 04:53:58 PM PDT 24
Peak memory	314228 kb
Host	smart-29c911df-41c0-48fa-a750-247723141c67
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587113588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.flash_ctrl_rw.1587113588
Directory	/workspace/13.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.4065092597
Short name	T339
Test name
Test status
Simulation time	35094700 ps
CPU time	30.93 seconds
Started	Jul 23 04:45:34 PM PDT 24
Finished	Jul 23 04:46:06 PM PDT 24
Peak memory	275628 kb
Host	smart-66c668db-8166-41c8-94b1-399d599755f8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065092597 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.4065092597
Directory	/workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/13.flash_ctrl_sec_info_access.902734012
Short name	T140
Test name
Test status
Simulation time	454024200 ps
CPU time	60.01 seconds
Started	Jul 23 04:45:36 PM PDT 24
Finished	Jul 23 04:46:37 PM PDT 24
Peak memory	263688 kb
Host	smart-676b8acc-0228-4e81-acf1-a43f8b3d65df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=902734012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.902734012
Directory	/workspace/13.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/13.flash_ctrl_smoke.2856347459
Short name	T859
Test name
Test status
Simulation time	173743900 ps
CPU time	98.57 seconds
Started	Jul 23 04:45:24 PM PDT 24
Finished	Jul 23 04:47:05 PM PDT 24
Peak memory	277004 kb
Host	smart-73d144ef-2370-406b-992c-69c3fea487c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2856347459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.2856347459
Directory	/workspace/13.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.flash_ctrl_wo.23834814
Short name	T941
Test name
Test status
Simulation time	2302067300 ps
CPU time	193.41 seconds
Started	Jul 23 04:45:36 PM PDT 24
Finished	Jul 23 04:48:51 PM PDT 24
Peak memory	260020 kb
Host	smart-a0e781b9-6bdb-48f1-b3b0-57ddf3b72974
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23834814 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 13.flash_ctrl_wo.23834814
Directory	/workspace/13.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/14.flash_ctrl_alert_test.15711645
Short name	T595
Test name
Test status
Simulation time	27764400 ps
CPU time	13.51 seconds
Started	Jul 23 04:45:47 PM PDT 24
Finished	Jul 23 04:46:02 PM PDT 24
Peak memory	258160 kb
Host	smart-74aeaa0f-502a-44c9-b93c-42c159222e39
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15711645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.15711645
Directory	/workspace/14.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.flash_ctrl_connect.749392189
Short name	T775
Test name
Test status
Simulation time	219799700 ps
CPU time	13.47 seconds
Started	Jul 23 04:45:42 PM PDT 24
Finished	Jul 23 04:45:57 PM PDT 24
Peak memory	284460 kb
Host	smart-ec7e4e4e-2f2a-4dea-9bb3-839f3d00730d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=749392189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.749392189
Directory	/workspace/14.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/14.flash_ctrl_disable.290386633
Short name	T966
Test name
Test status
Simulation time	70682700 ps
CPU time	22.23 seconds
Started	Jul 23 04:45:50 PM PDT 24
Finished	Jul 23 04:46:14 PM PDT 24
Peak memory	273612 kb
Host	smart-af354f0d-fab0-46cb-9398-e24b710239bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290386633 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_disable.290386633
Directory	/workspace/14.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.1880879802
Short name	T368
Test name
Test status
Simulation time	49502000 ps
CPU time	13.48 seconds
Started	Jul 23 04:45:47 PM PDT 24
Finished	Jul 23 04:46:02 PM PDT 24
Peak memory	260156 kb
Host	smart-74b30890-2cf8-4916-ac5d-e235d3859caf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880879802 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.1880879802
Directory	/workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_rma_reset.1823681015
Short name	T911
Test name
Test status
Simulation time	290278349600 ps
CPU time	907.76 seconds
Started	Jul 23 04:45:38 PM PDT 24
Finished	Jul 23 05:00:48 PM PDT 24
Peak memory	264540 kb
Host	smart-b7236b3c-83bf-4369-bf99-232d120b87b2
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823681015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 14.flash_ctrl_hw_rma_reset.1823681015
Directory	/workspace/14.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_sec_otp.4285373007
Short name	T833
Test name
Test status
Simulation time	95835518700 ps
CPU time	188.96 seconds
Started	Jul 23 04:45:37 PM PDT 24
Finished	Jul 23 04:48:48 PM PDT 24
Peak memory	263352 kb
Host	smart-190d679f-98e0-4c35-a5d0-738604353a36
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285373007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ hw_sec_otp.4285373007
Directory	/workspace/14.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd.3322555477
Short name	T307
Test name
Test status
Simulation time	746834700 ps
CPU time	139.83 seconds
Started	Jul 23 04:45:44 PM PDT 24
Finished	Jul 23 04:48:06 PM PDT 24
Peak memory	294124 kb
Host	smart-bfd609bd-6095-4474-9836-e574b701f69c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322555477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla sh_ctrl_intr_rd.3322555477
Directory	/workspace/14.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1239651682
Short name	T1023
Test name
Test status
Simulation time	11407082400 ps
CPU time	139.76 seconds
Started	Jul 23 04:45:44 PM PDT 24
Finished	Jul 23 04:48:06 PM PDT 24
Peak memory	292712 kb
Host	smart-99a1c125-f8e6-468b-a2cf-dc457a1c615a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239651682 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.1239651682
Directory	/workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/14.flash_ctrl_invalid_op.360624447
Short name	T796
Test name
Test status
Simulation time	1976584300 ps
CPU time	65.21 seconds
Started	Jul 23 04:45:46 PM PDT 24
Finished	Jul 23 04:46:53 PM PDT 24
Peak memory	260840 kb
Host	smart-a1eacf74-42d8-426d-aec7-8702cd93f46c
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360624447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.360624447
Directory	/workspace/14.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/14.flash_ctrl_lcmgr_intg.3556186225
Short name	T503
Test name
Test status
Simulation time	20242000 ps
CPU time	13.87 seconds
Started	Jul 23 04:45:45 PM PDT 24
Finished	Jul 23 04:46:01 PM PDT 24
Peak memory	264960 kb
Host	smart-8b49e92c-9043-41ec-89ee-406324cb2ff0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556186225 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.3556186225
Directory	/workspace/14.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/14.flash_ctrl_mp_regions.3681977802
Short name	T921
Test name
Test status
Simulation time	18790283400 ps
CPU time	296.74 seconds
Started	Jul 23 04:45:37 PM PDT 24
Finished	Jul 23 04:50:36 PM PDT 24
Peak memory	275280 kb
Host	smart-565b2939-f84d-4ba8-9669-48e959a83047
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681977802 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.3681977802
Directory	/workspace/14.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/14.flash_ctrl_otp_reset.853185281
Short name	T176
Test name
Test status
Simulation time	33890300 ps
CPU time	111.53 seconds
Started	Jul 23 04:45:37 PM PDT 24
Finished	Jul 23 04:47:31 PM PDT 24
Peak memory	260032 kb
Host	smart-ad0ff2d9-51d4-448d-a387-5114c18ddad1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853185281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ot p_reset.853185281
Directory	/workspace/14.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_phy_arb.3456790187
Short name	T1028
Test name
Test status
Simulation time	8670217000 ps
CPU time	240.98 seconds
Started	Jul 23 04:45:37 PM PDT 24
Finished	Jul 23 04:49:40 PM PDT 24
Peak memory	263056 kb
Host	smart-facb9ebd-18b5-463f-9b58-a94c36199f8a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3456790187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.3456790187
Directory	/workspace/14.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/14.flash_ctrl_prog_reset.1094459416
Short name	T1056
Test name
Test status
Simulation time	2520486500 ps
CPU time	197.42 seconds
Started	Jul 23 04:45:43 PM PDT 24
Finished	Jul 23 04:49:02 PM PDT 24
Peak memory	265316 kb
Host	smart-74aae386-2453-4f1b-b6b9-282523c2b02b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094459416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.flash_ctrl_prog_reset.1094459416
Directory	/workspace/14.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rand_ops.349557861
Short name	T131
Test name
Test status
Simulation time	276671400 ps
CPU time	525.31 seconds
Started	Jul 23 04:45:37 PM PDT 24
Finished	Jul 23 04:54:25 PM PDT 24
Peak memory	283876 kb
Host	smart-1d3501f7-ef21-46c9-98dc-0a9d291933bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=349557861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.349557861
Directory	/workspace/14.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/14.flash_ctrl_re_evict.1611195871
Short name	T494
Test name
Test status
Simulation time	567649600 ps
CPU time	34.2 seconds
Started	Jul 23 04:45:43 PM PDT 24
Finished	Jul 23 04:46:20 PM PDT 24
Peak memory	270652 kb
Host	smart-9039bfe4-c892-48c5-9af4-3ff74c49a1ff
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611195871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl ash_ctrl_re_evict.1611195871
Directory	/workspace/14.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/14.flash_ctrl_ro.833788214
Short name	T724
Test name
Test status
Simulation time	645731500 ps
CPU time	125.65 seconds
Started	Jul 23 04:45:46 PM PDT 24
Finished	Jul 23 04:47:54 PM PDT 24
Peak memory	281740 kb
Host	smart-54411a80-5d16-44f6-b6a1-d4326e65726e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833788214 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.flash_ctrl_ro.833788214
Directory	/workspace/14.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw.2054267669
Short name	T242
Test name
Test status
Simulation time	7160831800 ps
CPU time	558.35 seconds
Started	Jul 23 04:45:44 PM PDT 24
Finished	Jul 23 04:55:05 PM PDT 24
Peak memory	309796 kb
Host	smart-3dd029e4-4e7d-4b22-b8ef-3a50eb2d0518
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054267669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.flash_ctrl_rw.2054267669
Directory	/workspace/14.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw_evict.1020176970
Short name	T136
Test name
Test status
Simulation time	49908600 ps
CPU time	31.48 seconds
Started	Jul 23 04:45:48 PM PDT 24
Finished	Jul 23 04:46:21 PM PDT 24
Peak memory	275680 kb
Host	smart-c124ab7e-30b6-4733-b597-c476417ed53d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020176970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl ash_ctrl_rw_evict.1020176970
Directory	/workspace/14.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.1952459606
Short name	T714
Test name
Test status
Simulation time	29863400 ps
CPU time	28.35 seconds
Started	Jul 23 04:45:43 PM PDT 24
Finished	Jul 23 04:46:13 PM PDT 24
Peak memory	275684 kb
Host	smart-1a449668-532c-45ec-9143-9bbc73955d24
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952459606 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.1952459606
Directory	/workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/14.flash_ctrl_sec_info_access.3973109269
Short name	T157
Test name
Test status
Simulation time	447257800 ps
CPU time	62.64 seconds
Started	Jul 23 04:45:45 PM PDT 24
Finished	Jul 23 04:46:50 PM PDT 24
Peak memory	263676 kb
Host	smart-9f82b10c-acd2-4104-abe0-be11c256a990
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3973109269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.3973109269
Directory	/workspace/14.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/14.flash_ctrl_smoke.3534998673
Short name	T794
Test name
Test status
Simulation time	43515100 ps
CPU time	219.49 seconds
Started	Jul 23 04:45:37 PM PDT 24
Finished	Jul 23 04:49:19 PM PDT 24
Peak memory	278204 kb
Host	smart-86acfecc-49cb-453d-82cd-39fcc839721b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3534998673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.3534998673
Directory	/workspace/14.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.flash_ctrl_wo.3676971624
Short name	T498
Test name
Test status
Simulation time	5195287700 ps
CPU time	209.34 seconds
Started	Jul 23 04:45:45 PM PDT 24
Finished	Jul 23 04:49:16 PM PDT 24
Peak memory	265316 kb
Host	smart-6b3e7c47-84ec-4597-b0d9-e86f11abfdbb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676971624 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.flash_ctrl_wo.3676971624
Directory	/workspace/14.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/15.flash_ctrl_alert_test.1206044178
Short name	T715
Test name
Test status
Simulation time	432330200 ps
CPU time	14.28 seconds
Started	Jul 23 04:45:50 PM PDT 24
Finished	Jul 23 04:46:06 PM PDT 24
Peak memory	265332 kb
Host	smart-c5deb2c8-2858-4263-9bb4-18e4b88865d4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206044178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test. 1206044178
Directory	/workspace/15.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.flash_ctrl_connect.3806624910
Short name	T1081
Test name
Test status
Simulation time	24454500 ps
CPU time	15.77 seconds
Started	Jul 23 04:45:46 PM PDT 24
Finished	Jul 23 04:46:04 PM PDT 24
Peak memory	274940 kb
Host	smart-7b7830ce-c002-485c-b0ec-9221365da7bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3806624910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.3806624910
Directory	/workspace/15.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/15.flash_ctrl_disable.985075441
Short name	T196
Test name
Test status
Simulation time	24019100 ps
CPU time	21.97 seconds
Started	Jul 23 04:45:48 PM PDT 24
Finished	Jul 23 04:46:12 PM PDT 24
Peak memory	265432 kb
Host	smart-7145f7ce-006b-406a-9d6f-774e86930a0d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985075441 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_disable.985075441
Directory	/workspace/15.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.1609868818
Short name	T182
Test name
Test status
Simulation time	10036534600 ps
CPU time	45.33 seconds
Started	Jul 23 04:45:52 PM PDT 24
Finished	Jul 23 04:46:39 PM PDT 24
Peak memory	267040 kb
Host	smart-4931983b-2a39-467c-ac0f-2c7270550ea7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609868818 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.1609868818
Directory	/workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.3402472481
Short name	T565
Test name
Test status
Simulation time	15638300 ps
CPU time	13.42 seconds
Started	Jul 23 04:45:47 PM PDT 24
Finished	Jul 23 04:46:02 PM PDT 24
Peak memory	264772 kb
Host	smart-3ddcf2cc-2958-421d-a534-014d9ebf2611
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402472481 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.3402472481
Directory	/workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_sec_otp.2541923578
Short name	T542
Test name
Test status
Simulation time	2647364800 ps
CPU time	102.2 seconds
Started	Jul 23 04:45:44 PM PDT 24
Finished	Jul 23 04:47:28 PM PDT 24
Peak memory	262872 kb
Host	smart-bbfc8404-21e9-4133-a403-80b1c9facabc
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541923578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ hw_sec_otp.2541923578
Directory	/workspace/15.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd.1327664552
Short name	T963
Test name
Test status
Simulation time	2807481100 ps
CPU time	234.47 seconds
Started	Jul 23 04:45:44 PM PDT 24
Finished	Jul 23 04:49:41 PM PDT 24
Peak memory	284812 kb
Host	smart-6ce3ec77-afd9-447a-9cd3-14aa96c10ec0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327664552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla sh_ctrl_intr_rd.1327664552
Directory	/workspace/15.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.4175666458
Short name	T1047
Test name
Test status
Simulation time	5854433200 ps
CPU time	142.85 seconds
Started	Jul 23 04:45:44 PM PDT 24
Finished	Jul 23 04:48:09 PM PDT 24
Peak memory	293884 kb
Host	smart-f25d499d-835d-4521-acea-5a77d643a7ba
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175666458 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.4175666458
Directory	/workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/15.flash_ctrl_invalid_op.3483969547
Short name	T422
Test name
Test status
Simulation time	2054033700 ps
CPU time	74.69 seconds
Started	Jul 23 04:45:48 PM PDT 24
Finished	Jul 23 04:47:05 PM PDT 24
Peak memory	260908 kb
Host	smart-c60132da-0ec4-44df-9967-cf6b3efc91ff
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483969547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.3 483969547
Directory	/workspace/15.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/15.flash_ctrl_lcmgr_intg.1665202528
Short name	T638
Test name
Test status
Simulation time	26452900 ps
CPU time	13.69 seconds
Started	Jul 23 04:45:45 PM PDT 24
Finished	Jul 23 04:46:01 PM PDT 24
Peak memory	264908 kb
Host	smart-137772ac-119c-470d-a605-63b425f3f357
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665202528 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.1665202528
Directory	/workspace/15.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/15.flash_ctrl_mp_regions.2775133801
Short name	T127
Test name
Test status
Simulation time	62538713400 ps
CPU time	1155.68 seconds
Started	Jul 23 04:45:47 PM PDT 24
Finished	Jul 23 05:05:04 PM PDT 24
Peak memory	274792 kb
Host	smart-bf59d3cb-b733-4b46-a042-00471646755d
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775133801 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.2775133801
Directory	/workspace/15.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/15.flash_ctrl_otp_reset.948933588
Short name	T759
Test name
Test status
Simulation time	80258700 ps
CPU time	131.73 seconds
Started	Jul 23 04:45:46 PM PDT 24
Finished	Jul 23 04:48:00 PM PDT 24
Peak memory	260164 kb
Host	smart-8ad6d58b-9bcd-4fbc-9879-02c7eab3c52c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948933588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ot p_reset.948933588
Directory	/workspace/15.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_phy_arb.1591512534
Short name	T1009
Test name
Test status
Simulation time	1432929200 ps
CPU time	465.7 seconds
Started	Jul 23 04:45:45 PM PDT 24
Finished	Jul 23 04:53:33 PM PDT 24
Peak memory	263168 kb
Host	smart-f85498d2-1856-4155-b701-c9c2f2fcbea7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1591512534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.1591512534
Directory	/workspace/15.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/15.flash_ctrl_prog_reset.3037556923
Short name	T974
Test name
Test status
Simulation time	137470100 ps
CPU time	13.51 seconds
Started	Jul 23 04:45:44 PM PDT 24
Finished	Jul 23 04:46:00 PM PDT 24
Peak memory	259160 kb
Host	smart-56051924-ea6c-40cb-a248-e9d09a8d0089
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037556923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.flash_ctrl_prog_reset.3037556923
Directory	/workspace/15.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rand_ops.2950681333
Short name	T130
Test name
Test status
Simulation time	602598000 ps
CPU time	934.03 seconds
Started	Jul 23 04:45:42 PM PDT 24
Finished	Jul 23 05:01:17 PM PDT 24
Peak memory	284164 kb
Host	smart-03ecf159-894c-4532-bba5-69dcac24b987
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2950681333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.2950681333
Directory	/workspace/15.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/15.flash_ctrl_ro.300450431
Short name	T1020
Test name
Test status
Simulation time	1039695700 ps
CPU time	117.43 seconds
Started	Jul 23 04:45:46 PM PDT 24
Finished	Jul 23 04:47:46 PM PDT 24
Peak memory	289172 kb
Host	smart-617183fc-0fa8-4ca2-b1c9-f833a2904b8f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300450431 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.flash_ctrl_ro.300450431
Directory	/workspace/15.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw.1143866286
Short name	T959
Test name
Test status
Simulation time	3942402400 ps
CPU time	613.64 seconds
Started	Jul 23 04:45:43 PM PDT 24
Finished	Jul 23 04:55:59 PM PDT 24
Peak memory	314564 kb
Host	smart-57655f82-f358-4b0f-a2a0-09f073cdf46b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143866286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.flash_ctrl_rw.1143866286
Directory	/workspace/15.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.726561990
Short name	T501
Test name
Test status
Simulation time	73511600 ps
CPU time	28.16 seconds
Started	Jul 23 04:45:45 PM PDT 24
Finished	Jul 23 04:46:16 PM PDT 24
Peak memory	275540 kb
Host	smart-ef3cde34-3ae5-4eff-82c7-68691e306694
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726561990 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.726561990
Directory	/workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/15.flash_ctrl_smoke.2883182920
Short name	T248
Test name
Test status
Simulation time	26398700 ps
CPU time	193.68 seconds
Started	Jul 23 04:45:46 PM PDT 24
Finished	Jul 23 04:49:02 PM PDT 24
Peak memory	281444 kb
Host	smart-68adf000-c35c-4a12-9c8d-d1a2525cd403
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2883182920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.2883182920
Directory	/workspace/15.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.flash_ctrl_wo.4054580125
Short name	T523
Test name
Test status
Simulation time	7837306500 ps
CPU time	165.21 seconds
Started	Jul 23 04:45:43 PM PDT 24
Finished	Jul 23 04:48:31 PM PDT 24
Peak memory	259948 kb
Host	smart-333479c5-14a5-45d8-aa3c-f2ffc25da594
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054580125 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.flash_ctrl_wo.4054580125
Directory	/workspace/15.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/16.flash_ctrl_alert_test.2132871101
Short name	T1017
Test name
Test status
Simulation time	63665000 ps
CPU time	13.54 seconds
Started	Jul 23 04:45:55 PM PDT 24
Finished	Jul 23 04:46:10 PM PDT 24
Peak memory	265236 kb
Host	smart-6d5d9e46-4a71-4024-91fb-5021ab70ddcf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132871101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test. 2132871101
Directory	/workspace/16.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.flash_ctrl_connect.3772799328
Short name	T676
Test name
Test status
Simulation time	120018300 ps
CPU time	15.63 seconds
Started	Jul 23 04:45:51 PM PDT 24
Finished	Jul 23 04:46:09 PM PDT 24
Peak memory	284372 kb
Host	smart-314f6e68-044e-4a10-b375-aadb87298308
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3772799328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.3772799328
Directory	/workspace/16.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/16.flash_ctrl_disable.3856760421
Short name	T387
Test name
Test status
Simulation time	18307300 ps
CPU time	22.06 seconds
Started	Jul 23 04:45:51 PM PDT 24
Finished	Jul 23 04:46:16 PM PDT 24
Peak memory	273504 kb
Host	smart-10ebb601-02f2-4257-9eee-fc100d929b31
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856760421 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_disable.3856760421
Directory	/workspace/16.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.1760586220
Short name	T873
Test name
Test status
Simulation time	94702900 ps
CPU time	13.62 seconds
Started	Jul 23 04:45:52 PM PDT 24
Finished	Jul 23 04:46:08 PM PDT 24
Peak memory	258764 kb
Host	smart-ec58bdcf-c912-4c15-a8cb-96b7bd14b668
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760586220 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.1760586220
Directory	/workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_rma_reset.35992829
Short name	T1029
Test name
Test status
Simulation time	160174074800 ps
CPU time	872.3 seconds
Started	Jul 23 04:45:51 PM PDT 24
Finished	Jul 23 05:00:25 PM PDT 24
Peak memory	261104 kb
Host	smart-0866dafd-fbb3-4373-bd9a-77604dadb9c9
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35992829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 16.flash_ctrl_hw_rma_reset.35992829
Directory	/workspace/16.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_sec_otp.1339994689
Short name	T335
Test name
Test status
Simulation time	3219686300 ps
CPU time	218.15 seconds
Started	Jul 23 04:45:52 PM PDT 24
Finished	Jul 23 04:49:32 PM PDT 24
Peak memory	262868 kb
Host	smart-aaa77876-90c1-497b-9180-69a4232ca1cc
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339994689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ hw_sec_otp.1339994689
Directory	/workspace/16.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd.4188821198
Short name	T642
Test name
Test status
Simulation time	2759663900 ps
CPU time	148.2 seconds
Started	Jul 23 04:45:51 PM PDT 24
Finished	Jul 23 04:48:21 PM PDT 24
Peak memory	297560 kb
Host	smart-05c4ff97-165c-42b9-84c3-76d68db0ee9d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188821198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_intr_rd.4188821198
Directory	/workspace/16.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.210749189
Short name	T31
Test name
Test status
Simulation time	13690448100 ps
CPU time	172.02 seconds
Started	Jul 23 04:45:54 PM PDT 24
Finished	Jul 23 04:48:48 PM PDT 24
Peak memory	291868 kb
Host	smart-3bc960b7-cb0b-4c45-9fad-1b36e4ec7a8c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210749189 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.210749189
Directory	/workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/16.flash_ctrl_invalid_op.2688273087
Short name	T80
Test name
Test status
Simulation time	2029818800 ps
CPU time	87.84 seconds
Started	Jul 23 04:45:51 PM PDT 24
Finished	Jul 23 04:47:20 PM PDT 24
Peak memory	260796 kb
Host	smart-a4ed9fe1-e401-488a-8b35-6e1f1f1912e1
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688273087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.2 688273087
Directory	/workspace/16.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/16.flash_ctrl_lcmgr_intg.2094633417
Short name	T317
Test name
Test status
Simulation time	15834900 ps
CPU time	13.55 seconds
Started	Jul 23 04:45:50 PM PDT 24
Finished	Jul 23 04:46:05 PM PDT 24
Peak memory	259960 kb
Host	smart-bf66a327-ace0-45e5-968c-d9fc77b82454
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094633417 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.2094633417
Directory	/workspace/16.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/16.flash_ctrl_mp_regions.4293827408
Short name	T946
Test name
Test status
Simulation time	63036189800 ps
CPU time	385.81 seconds
Started	Jul 23 04:45:52 PM PDT 24
Finished	Jul 23 04:52:20 PM PDT 24
Peak memory	274888 kb
Host	smart-8b2a58d9-8a4d-4fee-952a-ef7d7d5f8ee7
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293827408 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.4293827408
Directory	/workspace/16.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/16.flash_ctrl_otp_reset.2094308469
Short name	T154
Test name
Test status
Simulation time	132873800 ps
CPU time	131.43 seconds
Started	Jul 23 04:45:51 PM PDT 24
Finished	Jul 23 04:48:05 PM PDT 24
Peak memory	265132 kb
Host	smart-5fe4ff17-0641-4550-bcff-cc5431897828
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094308469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o tp_reset.2094308469
Directory	/workspace/16.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_phy_arb.3464794885
Short name	T751
Test name
Test status
Simulation time	5998667000 ps
CPU time	467.98 seconds
Started	Jul 23 04:45:51 PM PDT 24
Finished	Jul 23 04:53:41 PM PDT 24
Peak memory	263172 kb
Host	smart-121deaf3-0f65-495f-9998-2f164efe3c96
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3464794885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.3464794885
Directory	/workspace/16.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/16.flash_ctrl_prog_reset.3857460686
Short name	T978
Test name
Test status
Simulation time	90628400 ps
CPU time	13.63 seconds
Started	Jul 23 04:45:52 PM PDT 24
Finished	Jul 23 04:46:08 PM PDT 24
Peak memory	265192 kb
Host	smart-f176785a-4df3-40fd-9b9f-fff11b8cdf78
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857460686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.flash_ctrl_prog_reset.3857460686
Directory	/workspace/16.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rand_ops.2900273109
Short name	T890
Test name
Test status
Simulation time	789418600 ps
CPU time	1002.05 seconds
Started	Jul 23 04:45:56 PM PDT 24
Finished	Jul 23 05:02:39 PM PDT 24
Peak memory	287612 kb
Host	smart-170409c2-2509-4fc6-9f12-ad3901a416b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900273109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2900273109
Directory	/workspace/16.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/16.flash_ctrl_re_evict.1910104257
Short name	T977
Test name
Test status
Simulation time	262402000 ps
CPU time	33.53 seconds
Started	Jul 23 04:45:52 PM PDT 24
Finished	Jul 23 04:46:28 PM PDT 24
Peak memory	275548 kb
Host	smart-71106ec9-d5dc-4c0f-9c8a-9c1767d37f0b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910104257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl ash_ctrl_re_evict.1910104257
Directory	/workspace/16.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/16.flash_ctrl_ro.1374592644
Short name	T396
Test name
Test status
Simulation time	516748100 ps
CPU time	129.48 seconds
Started	Jul 23 04:45:49 PM PDT 24
Finished	Jul 23 04:48:01 PM PDT 24
Peak memory	289984 kb
Host	smart-bb633757-73f0-4571-979b-3b4fe5ef9527
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374592644 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 16.flash_ctrl_ro.1374592644
Directory	/workspace/16.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw.3684249594
Short name	T756
Test name
Test status
Simulation time	6592008700 ps
CPU time	596 seconds
Started	Jul 23 04:45:51 PM PDT 24
Finished	Jul 23 04:55:49 PM PDT 24
Peak memory	309836 kb
Host	smart-9b1c5f77-aad0-4fd8-87df-eb91e3e30549
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684249594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.flash_ctrl_rw.3684249594
Directory	/workspace/16.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw_evict.850336261
Short name	T707
Test name
Test status
Simulation time	41146800 ps
CPU time	31.32 seconds
Started	Jul 23 04:45:51 PM PDT 24
Finished	Jul 23 04:46:25 PM PDT 24
Peak memory	274756 kb
Host	smart-862917b8-8d5d-4305-8196-87d1d1297594
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850336261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_rw_evict.850336261
Directory	/workspace/16.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.428574931
Short name	T432
Test name
Test status
Simulation time	28843900 ps
CPU time	31.34 seconds
Started	Jul 23 04:45:50 PM PDT 24
Finished	Jul 23 04:46:23 PM PDT 24
Peak memory	268500 kb
Host	smart-09fbf653-a261-4ead-8287-ec049b358c04
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428574931 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.428574931
Directory	/workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/16.flash_ctrl_smoke.3293431736
Short name	T394
Test name
Test status
Simulation time	44609400 ps
CPU time	124.43 seconds
Started	Jul 23 04:45:50 PM PDT 24
Finished	Jul 23 04:47:56 PM PDT 24
Peak memory	276348 kb
Host	smart-048ddaca-80c1-48a2-9560-17b9af1c9392
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3293431736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.3293431736
Directory	/workspace/16.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.flash_ctrl_wo.3816404552
Short name	T1010
Test name
Test status
Simulation time	2177002600 ps
CPU time	180.47 seconds
Started	Jul 23 04:45:51 PM PDT 24
Finished	Jul 23 04:48:52 PM PDT 24
Peak memory	265336 kb
Host	smart-25fdd400-1f2e-4d06-ada7-a0b035df94f3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816404552 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.flash_ctrl_wo.3816404552
Directory	/workspace/16.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/17.flash_ctrl_alert_test.2247528705
Short name	T940
Test name
Test status
Simulation time	22357800 ps
CPU time	13.49 seconds
Started	Jul 23 04:45:57 PM PDT 24
Finished	Jul 23 04:46:11 PM PDT 24
Peak memory	258420 kb
Host	smart-444c347f-d564-4cac-bd06-232971b56027
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247528705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test. 2247528705
Directory	/workspace/17.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.flash_ctrl_connect.2789593599
Short name	T934
Test name
Test status
Simulation time	46323400 ps
CPU time	15.1 seconds
Started	Jul 23 04:46:01 PM PDT 24
Finished	Jul 23 04:46:18 PM PDT 24
Peak memory	284412 kb
Host	smart-000d87a9-a919-4d66-9675-ec062d9ad354
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789593599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.2789593599
Directory	/workspace/17.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.2339969865
Short name	T1037
Test name
Test status
Simulation time	10021939500 ps
CPU time	79.41 seconds
Started	Jul 23 04:45:58 PM PDT 24
Finished	Jul 23 04:47:19 PM PDT 24
Peak memory	314864 kb
Host	smart-7380be40-e22f-4c9d-8afa-a242051e8c38
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339969865 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.2339969865
Directory	/workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.639055780
Short name	T736
Test name
Test status
Simulation time	18278700 ps
CPU time	13.01 seconds
Started	Jul 23 04:46:01 PM PDT 24
Finished	Jul 23 04:46:16 PM PDT 24
Peak memory	260140 kb
Host	smart-410431b8-638e-4583-93bf-af96de09b738
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639055780 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.639055780
Directory	/workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.1990666728
Short name	T769
Test name
Test status
Simulation time	80139115300 ps
CPU time	806.88 seconds
Started	Jul 23 04:45:55 PM PDT 24
Finished	Jul 23 04:59:23 PM PDT 24
Peak memory	264948 kb
Host	smart-795475d6-f775-419d-a3ec-89f79b156aa3
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990666728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 17.flash_ctrl_hw_rma_reset.1990666728
Directory	/workspace/17.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_sec_otp.4226701590
Short name	T36
Test name
Test status
Simulation time	3708669300 ps
CPU time	37.08 seconds
Started	Jul 23 04:45:51 PM PDT 24
Finished	Jul 23 04:46:31 PM PDT 24
Peak memory	263116 kb
Host	smart-aabf62a4-c034-428d-b8cb-a8b6990c0520
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226701590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ hw_sec_otp.4226701590
Directory	/workspace/17.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd.1136278753
Short name	T1068
Test name
Test status
Simulation time	843358200 ps
CPU time	134.38 seconds
Started	Jul 23 04:45:58 PM PDT 24
Finished	Jul 23 04:48:14 PM PDT 24
Peak memory	294088 kb
Host	smart-b175de85-8fee-49f8-935f-70a34279398c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136278753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla sh_ctrl_intr_rd.1136278753
Directory	/workspace/17.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2398798217
Short name	T168
Test name
Test status
Simulation time	49245774900 ps
CPU time	304.39 seconds
Started	Jul 23 04:45:58 PM PDT 24
Finished	Jul 23 04:51:04 PM PDT 24
Peak memory	284972 kb
Host	smart-91d8288e-dcc9-442b-be7f-bbf436f70726
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398798217 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.2398798217
Directory	/workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/17.flash_ctrl_invalid_op.1646900808
Short name	T318
Test name
Test status
Simulation time	3891899300 ps
CPU time	80.01 seconds
Started	Jul 23 04:45:58 PM PDT 24
Finished	Jul 23 04:47:20 PM PDT 24
Peak memory	263456 kb
Host	smart-39a39309-6331-4d6d-9dba-99161d104aec
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646900808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.1 646900808
Directory	/workspace/17.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/17.flash_ctrl_lcmgr_intg.4172311478
Short name	T745
Test name
Test status
Simulation time	15527100 ps
CPU time	13.38 seconds
Started	Jul 23 04:45:59 PM PDT 24
Finished	Jul 23 04:46:14 PM PDT 24
Peak memory	264908 kb
Host	smart-af7b7160-2370-4dca-a029-114bad15084d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172311478 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.4172311478
Directory	/workspace/17.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/17.flash_ctrl_mp_regions.3971645490
Short name	T125
Test name
Test status
Simulation time	10008575100 ps
CPU time	778.58 seconds
Started	Jul 23 04:45:58 PM PDT 24
Finished	Jul 23 04:58:58 PM PDT 24
Peak memory	274800 kb
Host	smart-bee427ab-ef21-4556-9be7-5ad6465d6f71
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971645490 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.3971645490
Directory	/workspace/17.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/17.flash_ctrl_otp_reset.1329033489
Short name	T681
Test name
Test status
Simulation time	92512700 ps
CPU time	132.11 seconds
Started	Jul 23 04:45:52 PM PDT 24
Finished	Jul 23 04:48:07 PM PDT 24
Peak memory	261328 kb
Host	smart-7a9e2488-5bc9-4b03-a84e-18452119616b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329033489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o tp_reset.1329033489
Directory	/workspace/17.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_phy_arb.617043643
Short name	T985
Test name
Test status
Simulation time	243126400 ps
CPU time	321.13 seconds
Started	Jul 23 04:45:53 PM PDT 24
Finished	Jul 23 04:51:16 PM PDT 24
Peak memory	263376 kb
Host	smart-026a8ef9-f4be-4963-ae54-ee26dff9c313
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=617043643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.617043643
Directory	/workspace/17.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/17.flash_ctrl_prog_reset.2072437456
Short name	T165
Test name
Test status
Simulation time	38858900 ps
CPU time	13.54 seconds
Started	Jul 23 04:45:58 PM PDT 24
Finished	Jul 23 04:46:13 PM PDT 24
Peak memory	265280 kb
Host	smart-5cec32c0-1119-4caa-9d8c-6beee733d29e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072437456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.flash_ctrl_prog_reset.2072437456
Directory	/workspace/17.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rand_ops.447129915
Short name	T656
Test name
Test status
Simulation time	92375000 ps
CPU time	375.77 seconds
Started	Jul 23 04:45:56 PM PDT 24
Finished	Jul 23 04:52:13 PM PDT 24
Peak memory	281992 kb
Host	smart-0b852573-1c91-4b18-9a23-ba0f2f7f63a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=447129915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.447129915
Directory	/workspace/17.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/17.flash_ctrl_ro.2641893625
Short name	T788
Test name
Test status
Simulation time	534713200 ps
CPU time	116.65 seconds
Started	Jul 23 04:45:59 PM PDT 24
Finished	Jul 23 04:47:57 PM PDT 24
Peak memory	281848 kb
Host	smart-4b78de71-aadf-4f45-99a8-bebe94f8dba6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641893625 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 17.flash_ctrl_ro.2641893625
Directory	/workspace/17.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw.26699130
Short name	T671
Test name
Test status
Simulation time	8385727100 ps
CPU time	567.18 seconds
Started	Jul 23 04:45:59 PM PDT 24
Finished	Jul 23 04:55:28 PM PDT 24
Peak memory	314488 kb
Host	smart-9b34a555-8cbb-49c2-8578-89e84aa727b1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26699130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw.26699130
Directory	/workspace/17.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw_evict.2032342491
Short name	T563
Test name
Test status
Simulation time	75096900 ps
CPU time	30.65 seconds
Started	Jul 23 04:46:00 PM PDT 24
Finished	Jul 23 04:46:32 PM PDT 24
Peak memory	275560 kb
Host	smart-6f243d7a-f509-417e-930e-2b3dabc8c34b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032342491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl ash_ctrl_rw_evict.2032342491
Directory	/workspace/17.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.1076637030
Short name	T767
Test name
Test status
Simulation time	52345300 ps
CPU time	31.18 seconds
Started	Jul 23 04:45:58 PM PDT 24
Finished	Jul 23 04:46:31 PM PDT 24
Peak memory	267540 kb
Host	smart-5a6827f5-0ae8-430b-bb28-43be4f9de0da
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076637030 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.1076637030
Directory	/workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/17.flash_ctrl_sec_info_access.2335935185
Short name	T48
Test name
Test status
Simulation time	7619509400 ps
CPU time	65.24 seconds
Started	Jul 23 04:46:01 PM PDT 24
Finished	Jul 23 04:47:08 PM PDT 24
Peak memory	264648 kb
Host	smart-ebeb0cd0-1868-404c-9391-6069610dc9f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335935185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.2335935185
Directory	/workspace/17.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/17.flash_ctrl_smoke.2725591854
Short name	T238
Test name
Test status
Simulation time	66195600 ps
CPU time	99.88 seconds
Started	Jul 23 04:45:53 PM PDT 24
Finished	Jul 23 04:47:35 PM PDT 24
Peak memory	277052 kb
Host	smart-1e909cd1-626e-432a-bd1c-2b2fbc96a7bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725591854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.2725591854
Directory	/workspace/17.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.flash_ctrl_wo.2247972111
Short name	T785
Test name
Test status
Simulation time	37883214900 ps
CPU time	213.33 seconds
Started	Jul 23 04:45:57 PM PDT 24
Finished	Jul 23 04:49:31 PM PDT 24
Peak memory	260440 kb
Host	smart-b5dbcf72-646f-4373-b0ff-f76bd5ff3237
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247972111 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.flash_ctrl_wo.2247972111
Directory	/workspace/17.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/18.flash_ctrl_alert_test.2343292752
Short name	T981
Test name
Test status
Simulation time	75039600 ps
CPU time	14.01 seconds
Started	Jul 23 04:46:15 PM PDT 24
Finished	Jul 23 04:46:31 PM PDT 24
Peak memory	258392 kb
Host	smart-6afa04d6-cf3e-43b3-8843-327612581e69
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343292752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test. 2343292752
Directory	/workspace/18.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.flash_ctrl_connect.3399454706
Short name	T267
Test name
Test status
Simulation time	15567400 ps
CPU time	13.99 seconds
Started	Jul 23 04:46:07 PM PDT 24
Finished	Jul 23 04:46:23 PM PDT 24
Peak memory	284304 kb
Host	smart-9cbab1ef-094a-463e-8e35-29804618f0e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3399454706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.3399454706
Directory	/workspace/18.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.2028775432
Short name	T314
Test name
Test status
Simulation time	10024427600 ps
CPU time	141.11 seconds
Started	Jul 23 04:46:14 PM PDT 24
Finished	Jul 23 04:48:37 PM PDT 24
Peak memory	277820 kb
Host	smart-2d130dd6-57bd-4f82-91bd-4c4ede232103
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028775432 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.2028775432
Directory	/workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.4104452897
Short name	T211
Test name
Test status
Simulation time	47148500 ps
CPU time	13.66 seconds
Started	Jul 23 04:46:15 PM PDT 24
Finished	Jul 23 04:46:31 PM PDT 24
Peak memory	258456 kb
Host	smart-a0ac1bf0-6276-4d0e-bd31-c27e194cba91
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104452897 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.4104452897
Directory	/workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_rma_reset.3400460205
Short name	T200
Test name
Test status
Simulation time	120147223000 ps
CPU time	844.69 seconds
Started	Jul 23 04:46:06 PM PDT 24
Finished	Jul 23 05:00:13 PM PDT 24
Peak memory	264104 kb
Host	smart-049d5d4e-3326-4130-b691-4c08808d8b2c
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400460205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 18.flash_ctrl_hw_rma_reset.3400460205
Directory	/workspace/18.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_sec_otp.3716748042
Short name	T341
Test name
Test status
Simulation time	5936493700 ps
CPU time	243.71 seconds
Started	Jul 23 04:45:58 PM PDT 24
Finished	Jul 23 04:50:02 PM PDT 24
Peak memory	263392 kb
Host	smart-648db8ea-7205-4873-85c6-eaebe398cedb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716748042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ hw_sec_otp.3716748042
Directory	/workspace/18.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/18.flash_ctrl_intr_rd.3631262431
Short name	T651
Test name
Test status
Simulation time	7762397300 ps
CPU time	219.65 seconds
Started	Jul 23 04:46:04 PM PDT 24
Finished	Jul 23 04:49:46 PM PDT 24
Peak memory	284852 kb
Host	smart-c4251d8a-f999-44dd-9a20-77bc9ec7fe91
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631262431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla sh_ctrl_intr_rd.3631262431
Directory	/workspace/18.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.2551268806
Short name	T554
Test name
Test status
Simulation time	12216037100 ps
CPU time	371.36 seconds
Started	Jul 23 04:46:07 PM PDT 24
Finished	Jul 23 04:52:20 PM PDT 24
Peak memory	292060 kb
Host	smart-b8bb8ac4-f758-439c-9cc1-da317bfe0fd8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551268806 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.2551268806
Directory	/workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/18.flash_ctrl_invalid_op.451244594
Short name	T423
Test name
Test status
Simulation time	2057446300 ps
CPU time	61.99 seconds
Started	Jul 23 04:46:07 PM PDT 24
Finished	Jul 23 04:47:11 PM PDT 24
Peak memory	260584 kb
Host	smart-f15d11c0-b7bf-4958-af20-bf5f2256837d
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451244594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.451244594
Directory	/workspace/18.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/18.flash_ctrl_lcmgr_intg.2120366564
Short name	T847
Test name
Test status
Simulation time	26559800 ps
CPU time	13.19 seconds
Started	Jul 23 04:46:05 PM PDT 24
Finished	Jul 23 04:46:21 PM PDT 24
Peak memory	259888 kb
Host	smart-9b37b469-b858-4a06-a333-e49324675c17
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120366564 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.2120366564
Directory	/workspace/18.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/18.flash_ctrl_otp_reset.3906230545
Short name	T345
Test name
Test status
Simulation time	70271300 ps
CPU time	110.86 seconds
Started	Jul 23 04:46:07 PM PDT 24
Finished	Jul 23 04:48:00 PM PDT 24
Peak memory	261144 kb
Host	smart-3f0c185e-1f83-43b1-b4fa-638f083dc82c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906230545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o tp_reset.3906230545
Directory	/workspace/18.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_phy_arb.3087275454
Short name	T1072
Test name
Test status
Simulation time	71036300 ps
CPU time	382.39 seconds
Started	Jul 23 04:45:58 PM PDT 24
Finished	Jul 23 04:52:22 PM PDT 24
Peak memory	263272 kb
Host	smart-a84629ea-cd6f-48da-a325-7c358ff9f693
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3087275454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.3087275454
Directory	/workspace/18.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/18.flash_ctrl_prog_reset.210438724
Short name	T735
Test name
Test status
Simulation time	18265500 ps
CPU time	13.32 seconds
Started	Jul 23 04:46:08 PM PDT 24
Finished	Jul 23 04:46:23 PM PDT 24
Peak memory	259164 kb
Host	smart-32223fd9-f1ec-4277-bf19-28fe05b68de4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210438724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.flash_ctrl_prog_reset.210438724
Directory	/workspace/18.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rand_ops.740043470
Short name	T159
Test name
Test status
Simulation time	328183500 ps
CPU time	353.59 seconds
Started	Jul 23 04:45:58 PM PDT 24
Finished	Jul 23 04:51:54 PM PDT 24
Peak memory	277644 kb
Host	smart-79f5bdbb-2a66-49a0-9127-abd966d7e1fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=740043470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.740043470
Directory	/workspace/18.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/18.flash_ctrl_re_evict.2737064250
Short name	T629
Test name
Test status
Simulation time	123028300 ps
CPU time	33.73 seconds
Started	Jul 23 04:46:07 PM PDT 24
Finished	Jul 23 04:46:43 PM PDT 24
Peak memory	275576 kb
Host	smart-2592d5a9-1d62-4ce0-825e-899a7ec6716c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737064250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl ash_ctrl_re_evict.2737064250
Directory	/workspace/18.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/18.flash_ctrl_ro.3058125912
Short name	T726
Test name
Test status
Simulation time	3264925600 ps
CPU time	112.49 seconds
Started	Jul 23 04:46:07 PM PDT 24
Finished	Jul 23 04:48:02 PM PDT 24
Peak memory	291504 kb
Host	smart-9107b796-f0cc-408e-a2a2-ca6e5b6628d3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058125912 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 18.flash_ctrl_ro.3058125912
Directory	/workspace/18.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw.2265566408
Short name	T855
Test name
Test status
Simulation time	16363079100 ps
CPU time	618.47 seconds
Started	Jul 23 04:46:05 PM PDT 24
Finished	Jul 23 04:56:25 PM PDT 24
Peak memory	310520 kb
Host	smart-ac82a5bd-d3be-4fb4-a982-c7e39d6ab858
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265566408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.flash_ctrl_rw.2265566408
Directory	/workspace/18.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw_evict.4118268332
Short name	T711
Test name
Test status
Simulation time	67938800 ps
CPU time	31.5 seconds
Started	Jul 23 04:46:06 PM PDT 24
Finished	Jul 23 04:46:40 PM PDT 24
Peak memory	275576 kb
Host	smart-a4f3f279-3f0d-471f-8a4a-6b95e81c3345
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118268332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl ash_ctrl_rw_evict.4118268332
Directory	/workspace/18.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.572735289
Short name	T856
Test name
Test status
Simulation time	226658400 ps
CPU time	28.87 seconds
Started	Jul 23 04:46:06 PM PDT 24
Finished	Jul 23 04:46:38 PM PDT 24
Peak memory	275584 kb
Host	smart-37bd3ead-4f33-425e-b312-0077f225d2bf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572735289 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.572735289
Directory	/workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/18.flash_ctrl_smoke.2389410321
Short name	T633
Test name
Test status
Simulation time	244852300 ps
CPU time	171.5 seconds
Started	Jul 23 04:45:58 PM PDT 24
Finished	Jul 23 04:48:52 PM PDT 24
Peak memory	280160 kb
Host	smart-e2db1f57-7d2f-4647-99ee-ac29d0f10c5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2389410321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2389410321
Directory	/workspace/18.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.flash_ctrl_wo.2261063611
Short name	T857
Test name
Test status
Simulation time	33285327200 ps
CPU time	228.83 seconds
Started	Jul 23 04:46:08 PM PDT 24
Finished	Jul 23 04:49:59 PM PDT 24
Peak memory	261088 kb
Host	smart-f4ca0149-d1cc-4d70-bfa5-61a5e9ca091b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261063611 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.flash_ctrl_wo.2261063611
Directory	/workspace/18.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/19.flash_ctrl_alert_test.2709093234
Short name	T92
Test name
Test status
Simulation time	63648000 ps
CPU time	13.74 seconds
Started	Jul 23 04:46:17 PM PDT 24
Finished	Jul 23 04:46:32 PM PDT 24
Peak memory	258368 kb
Host	smart-4fb7beac-4f7e-4374-8d91-64a2937c430f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709093234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test. 2709093234
Directory	/workspace/19.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.flash_ctrl_connect.3131604442
Short name	T783
Test name
Test status
Simulation time	52003600 ps
CPU time	13.29 seconds
Started	Jul 23 04:46:15 PM PDT 24
Finished	Jul 23 04:46:30 PM PDT 24
Peak memory	274948 kb
Host	smart-87aea233-cedc-4de6-8888-e34e87a3bf1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3131604442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.3131604442
Directory	/workspace/19.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/19.flash_ctrl_disable.2014254591
Short name	T1098
Test name
Test status
Simulation time	59204300 ps
CPU time	21.7 seconds
Started	Jul 23 04:46:15 PM PDT 24
Finished	Jul 23 04:46:38 PM PDT 24
Peak memory	273596 kb
Host	smart-32e4aa51-f32d-4d01-bed2-99f46ce17890
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014254591 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_disable.2014254591
Directory	/workspace/19.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.2707212467
Short name	T674
Test name
Test status
Simulation time	10019519300 ps
CPU time	70.42 seconds
Started	Jul 23 04:46:14 PM PDT 24
Finished	Jul 23 04:47:27 PM PDT 24
Peak memory	297988 kb
Host	smart-0e156e5a-7c77-4c74-82d1-055c4289341d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707212467 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.2707212467
Directory	/workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.3316375265
Short name	T1025
Test name
Test status
Simulation time	49639000 ps
CPU time	13.48 seconds
Started	Jul 23 04:46:15 PM PDT 24
Finished	Jul 23 04:46:30 PM PDT 24
Peak memory	258648 kb
Host	smart-083880f8-5135-4838-a8e7-132be0443885
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316375265 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.3316375265
Directory	/workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_rma_reset.3895791533
Short name	T839
Test name
Test status
Simulation time	80139763500 ps
CPU time	827.36 seconds
Started	Jul 23 04:46:16 PM PDT 24
Finished	Jul 23 05:00:05 PM PDT 24
Peak memory	260964 kb
Host	smart-169429e0-8963-45c0-a7c3-c82ffa5631dc
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895791533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 19.flash_ctrl_hw_rma_reset.3895791533
Directory	/workspace/19.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_sec_otp.2018508314
Short name	T774
Test name
Test status
Simulation time	4175722000 ps
CPU time	149.17 seconds
Started	Jul 23 04:46:14 PM PDT 24
Finished	Jul 23 04:48:45 PM PDT 24
Peak memory	260960 kb
Host	smart-ce9b1a7d-804e-495c-9493-af6106690237
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018508314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ hw_sec_otp.2018508314
Directory	/workspace/19.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.715720752
Short name	T693
Test name
Test status
Simulation time	48385944900 ps
CPU time	291.95 seconds
Started	Jul 23 04:46:14 PM PDT 24
Finished	Jul 23 04:51:07 PM PDT 24
Peak memory	292092 kb
Host	smart-5d3ec031-47cc-490b-adf2-ebebf5e6778f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715720752 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.715720752
Directory	/workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/19.flash_ctrl_invalid_op.816166395
Short name	T752
Test name
Test status
Simulation time	3907419700 ps
CPU time	78.35 seconds
Started	Jul 23 04:46:15 PM PDT 24
Finished	Jul 23 04:47:35 PM PDT 24
Peak memory	263460 kb
Host	smart-956cd8e4-4f32-424d-9b58-b3d8744ffdc7
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816166395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.816166395
Directory	/workspace/19.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/19.flash_ctrl_lcmgr_intg.2999923043
Short name	T316
Test name
Test status
Simulation time	25844900 ps
CPU time	13.57 seconds
Started	Jul 23 04:46:15 PM PDT 24
Finished	Jul 23 04:46:31 PM PDT 24
Peak memory	259872 kb
Host	smart-d755ca2f-46ac-428e-b2a4-3fad1905bd70
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999923043 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.2999923043
Directory	/workspace/19.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/19.flash_ctrl_mp_regions.3629817060
Short name	T69
Test name
Test status
Simulation time	5199567600 ps
CPU time	412.91 seconds
Started	Jul 23 04:46:14 PM PDT 24
Finished	Jul 23 04:53:09 PM PDT 24
Peak memory	273968 kb
Host	smart-dddc7a31-5984-4153-a18b-bc629ce69e3c
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629817060 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_mp_regions.3629817060
Directory	/workspace/19.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/19.flash_ctrl_otp_reset.46924454
Short name	T573
Test name
Test status
Simulation time	226232300 ps
CPU time	130.67 seconds
Started	Jul 23 04:46:13 PM PDT 24
Finished	Jul 23 04:48:25 PM PDT 24
Peak memory	260244 kb
Host	smart-61125695-bb4e-4cb6-abb5-81a63e4802ef
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46924454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_otp _reset.46924454
Directory	/workspace/19.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_phy_arb.99891614
Short name	T797
Test name
Test status
Simulation time	1437092700 ps
CPU time	473.79 seconds
Started	Jul 23 04:46:18 PM PDT 24
Finished	Jul 23 04:54:13 PM PDT 24
Peak memory	263100 kb
Host	smart-d79e31a9-b841-4ec0-a3f3-bb752a608965
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=99891614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.99891614
Directory	/workspace/19.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/19.flash_ctrl_prog_reset.4257634840
Short name	T572
Test name
Test status
Simulation time	40907100 ps
CPU time	13.72 seconds
Started	Jul 23 04:46:19 PM PDT 24
Finished	Jul 23 04:46:33 PM PDT 24
Peak memory	265364 kb
Host	smart-a27e494e-99d6-4c1c-89e8-3170aced00b8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257634840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.flash_ctrl_prog_reset.4257634840
Directory	/workspace/19.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rand_ops.176993414
Short name	T546
Test name
Test status
Simulation time	356793900 ps
CPU time	658.97 seconds
Started	Jul 23 04:46:16 PM PDT 24
Finished	Jul 23 04:57:17 PM PDT 24
Peak memory	282496 kb
Host	smart-967ff067-aa9e-4f55-864d-0ee36e0a7d56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=176993414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.176993414
Directory	/workspace/19.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/19.flash_ctrl_re_evict.2011211707
Short name	T425
Test name
Test status
Simulation time	129844600 ps
CPU time	32.37 seconds
Started	Jul 23 04:46:16 PM PDT 24
Finished	Jul 23 04:46:50 PM PDT 24
Peak memory	275728 kb
Host	smart-f237ad54-6f68-401c-97e5-61370adc677d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011211707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl ash_ctrl_re_evict.2011211707
Directory	/workspace/19.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/19.flash_ctrl_ro.2071795668
Short name	T600
Test name
Test status
Simulation time	600963400 ps
CPU time	115.13 seconds
Started	Jul 23 04:46:16 PM PDT 24
Finished	Jul 23 04:48:13 PM PDT 24
Peak memory	291432 kb
Host	smart-8b0247e4-9452-4d59-be66-691d904ca0d6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071795668 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 19.flash_ctrl_ro.2071795668
Directory	/workspace/19.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw.1202272697
Short name	T2
Test name
Test status
Simulation time	4079359300 ps
CPU time	603.33 seconds
Started	Jul 23 04:46:14 PM PDT 24
Finished	Jul 23 04:56:18 PM PDT 24
Peak memory	314236 kb
Host	smart-d62a47c6-cddd-4d2a-8d10-5d07b1064cea
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202272697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.flash_ctrl_rw.1202272697
Directory	/workspace/19.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict.3492208041
Short name	T614
Test name
Test status
Simulation time	108047100 ps
CPU time	30.4 seconds
Started	Jul 23 04:46:18 PM PDT 24
Finished	Jul 23 04:46:49 PM PDT 24
Peak memory	268556 kb
Host	smart-354a47ea-9454-47bb-98e5-b09d45abf038
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492208041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl ash_ctrl_rw_evict.3492208041
Directory	/workspace/19.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.1910779405
Short name	T583
Test name
Test status
Simulation time	97385600 ps
CPU time	31.34 seconds
Started	Jul 23 04:46:14 PM PDT 24
Finished	Jul 23 04:46:47 PM PDT 24
Peak memory	275540 kb
Host	smart-a9493970-cd77-41cb-92a9-41831194eb49
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910779405 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.1910779405
Directory	/workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/19.flash_ctrl_smoke.3363839380
Short name	T59
Test name
Test status
Simulation time	29841500 ps
CPU time	148.95 seconds
Started	Jul 23 04:46:17 PM PDT 24
Finished	Jul 23 04:48:47 PM PDT 24
Peak memory	278100 kb
Host	smart-eb6a6198-9a1f-4b7a-9777-4febc1c1e114
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363839380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.3363839380
Directory	/workspace/19.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.flash_ctrl_wo.3794024415
Short name	T118
Test name
Test status
Simulation time	8726911200 ps
CPU time	134.45 seconds
Started	Jul 23 04:46:13 PM PDT 24
Finished	Jul 23 04:48:29 PM PDT 24
Peak memory	259892 kb
Host	smart-95cfbd4d-5166-4373-b959-7a82f7601cd8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794024415 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.flash_ctrl_wo.3794024415
Directory	/workspace/19.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/2.flash_ctrl_alert_test.729050368
Short name	T912
Test name
Test status
Simulation time	95465400 ps
CPU time	13.86 seconds
Started	Jul 23 04:44:13 PM PDT 24
Finished	Jul 23 04:44:30 PM PDT 24
Peak memory	265284 kb
Host	smart-93e2fb96-44ca-4d2e-8c42-6add3cd99f2c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729050368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.729050368
Directory	/workspace/2.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.flash_ctrl_config_regwen.4253653211
Short name	T919
Test name
Test status
Simulation time	73772800 ps
CPU time	13.88 seconds
Started	Jul 23 04:44:10 PM PDT 24
Finished	Jul 23 04:44:28 PM PDT 24
Peak memory	265008 kb
Host	smart-b4d6d473-2201-4cc8-87c2-a5e806799149
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253653211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .flash_ctrl_config_regwen.4253653211
Directory	/workspace/2.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/2.flash_ctrl_connect.2877633204
Short name	T447
Test name
Test status
Simulation time	25129000 ps
CPU time	13.32 seconds
Started	Jul 23 04:44:08 PM PDT 24
Finished	Jul 23 04:44:24 PM PDT 24
Peak memory	284168 kb
Host	smart-8ef6c1d6-391e-4bd2-bb6f-ced843105e10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877633204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.2877633204
Directory	/workspace/2.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/2.flash_ctrl_erase_suspend.843101216
Short name	T208
Test name
Test status
Simulation time	5562730400 ps
CPU time	373.49 seconds
Started	Jul 23 04:44:00 PM PDT 24
Finished	Jul 23 04:50:17 PM PDT 24
Peak memory	263332 kb
Host	smart-ff61497a-7f4b-42cc-90a5-de7627dc5f5a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=843101216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.843101216
Directory	/workspace/2.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_mp.2621536098
Short name	T1073
Test name
Test status
Simulation time	3664610700 ps
CPU time	2284.63 seconds
Started	Jul 23 04:43:57 PM PDT 24
Finished	Jul 23 05:22:06 PM PDT 24
Peak memory	264984 kb
Host	smart-3bf173f7-1a0c-4db3-953f-ebcca54a3b79
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2621536098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.2621536098
Directory	/workspace/2.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_type.1089843593
Short name	T85
Test name
Test status
Simulation time	3422975000 ps
CPU time	2213.3 seconds
Started	Jul 23 04:44:00 PM PDT 24
Finished	Jul 23 05:20:57 PM PDT 24
Peak memory	264932 kb
Host	smart-5e8593de-36f1-47f4-a2f3-f28acf87a79c
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089843593 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.1089843593
Directory	/workspace/2.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_win.3390065211
Short name	T793
Test name
Test status
Simulation time	730589200 ps
CPU time	865.97 seconds
Started	Jul 23 04:44:00 PM PDT 24
Finished	Jul 23 04:58:29 PM PDT 24
Peak memory	270584 kb
Host	smart-77b9bf7a-e9cc-4cfc-a80e-1be3e0195f11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3390065211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.3390065211
Directory	/workspace/2.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fetch_code.1446338435
Short name	T45
Test name
Test status
Simulation time	1205339600 ps
CPU time	25.83 seconds
Started	Jul 23 04:44:00 PM PDT 24
Finished	Jul 23 04:44:29 PM PDT 24
Peak memory	262400 kb
Host	smart-5cbdead4-f658-4d5f-ba7d-eaa3a190f8ad
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446338435 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.1446338435
Directory	/workspace/2.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fs_sup.3478162506
Short name	T837
Test name
Test status
Simulation time	1782751900 ps
CPU time	36.67 seconds
Started	Jul 23 04:44:10 PM PDT 24
Finished	Jul 23 04:44:50 PM PDT 24
Peak memory	262964 kb
Host	smart-3f35062d-110e-4850-978b-9cb04d14502f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478162506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.flash_ctrl_fs_sup.3478162506
Directory	/workspace/2.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/2.flash_ctrl_full_mem_access.2274421347
Short name	T35
Test name
Test status
Simulation time	266363920600 ps
CPU time	2724.86 seconds
Started	Jul 23 04:43:57 PM PDT 24
Finished	Jul 23 05:29:27 PM PDT 24
Peak memory	265184 kb
Host	smart-ede945a3-2b6a-4067-83ca-9a603cf7af4a
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274421347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c trl_full_mem_access.2274421347
Directory	/workspace/2.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_addr_infection.3622025691
Short name	T766
Test name
Test status
Simulation time	27537000 ps
CPU time	30.07 seconds
Started	Jul 23 04:44:10 PM PDT 24
Finished	Jul 23 04:44:44 PM PDT 24
Peak memory	268448 kb
Host	smart-f5685495-69bd-481c-b131-3ff5596c7257
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622025691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_host_addr_infection.3622025691
Directory	/workspace/2.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.1620934391
Short name	T975
Test name
Test status
Simulation time	241421259300 ps
CPU time	2694 seconds
Started	Jul 23 04:43:57 PM PDT 24
Finished	Jul 23 05:28:56 PM PDT 24
Peak memory	263900 kb
Host	smart-ef1a7b7f-9bc9-45b0-842b-8a7533c0f20e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620934391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.flash_ctrl_host_ctrl_arb.1620934391
Directory	/workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_dir_rd.3656279378
Short name	T305
Test name
Test status
Simulation time	51741200 ps
CPU time	89.22 seconds
Started	Jul 23 04:43:59 PM PDT 24
Finished	Jul 23 04:45:32 PM PDT 24
Peak memory	262300 kb
Host	smart-ba155c12-55d1-47f3-b791-ad3c2bb4fbd2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3656279378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.3656279378
Directory	/workspace/2.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.584636352
Short name	T926
Test name
Test status
Simulation time	15756700 ps
CPU time	13.61 seconds
Started	Jul 23 04:44:09 PM PDT 24
Finished	Jul 23 04:44:26 PM PDT 24
Peak memory	259576 kb
Host	smart-091e6912-ada3-4a64-aa6c-fa168cc151e3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584636352 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.584636352
Directory	/workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma.1930685567
Short name	T877
Test name
Test status
Simulation time	85161451000 ps
CPU time	1813.39 seconds
Started	Jul 23 04:43:58 PM PDT 24
Finished	Jul 23 05:14:16 PM PDT 24
Peak memory	265092 kb
Host	smart-cccc6050-7e10-42b4-a68f-d9f093ebdb00
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930685567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.flash_ctrl_hw_rma.1930685567
Directory	/workspace/2.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma_reset.610813818
Short name	T645
Test name
Test status
Simulation time	80141269800 ps
CPU time	849.33 seconds
Started	Jul 23 04:44:00 PM PDT 24
Finished	Jul 23 04:58:13 PM PDT 24
Peak memory	262384 kb
Host	smart-d7ce5a59-6167-457a-beb9-8ddb10203590
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610813818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_hw_rma_reset.610813818
Directory	/workspace/2.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_sec_otp.3199301735
Short name	T973
Test name
Test status
Simulation time	2413298300 ps
CPU time	74.46 seconds
Started	Jul 23 04:43:58 PM PDT 24
Finished	Jul 23 04:45:17 PM PDT 24
Peak memory	260816 kb
Host	smart-d75123fa-b7c8-4635-866c-c16032f16176
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199301735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h w_sec_otp.3199301735
Directory	/workspace/2.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_integrity.2284533898
Short name	T273
Test name
Test status
Simulation time	4274134100 ps
CPU time	652.11 seconds
Started	Jul 23 04:44:13 PM PDT 24
Finished	Jul 23 04:55:08 PM PDT 24
Peak memory	334792 kb
Host	smart-5544588b-1144-4434-ae2b-93d6498820f6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284533898 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_integrity.2284533898
Directory	/workspace/2.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd.10318945
Short name	T469
Test name
Test status
Simulation time	7150032600 ps
CPU time	223.11 seconds
Started	Jul 23 04:44:15 PM PDT 24
Finished	Jul 23 04:48:01 PM PDT 24
Peak memory	284840 kb
Host	smart-9ff32aaa-89ec-41b3-aaf7-9b64ca5c5150
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10318945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ ctrl_intr_rd.10318945
Directory	/workspace/2.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.4259938245
Short name	T441
Test name
Test status
Simulation time	170969496900 ps
CPU time	340.4 seconds
Started	Jul 23 04:44:11 PM PDT 24
Finished	Jul 23 04:49:56 PM PDT 24
Peak memory	290916 kb
Host	smart-e84e47b2-ffd7-42c4-8683-ba65fc1628ef
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259938245 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.4259938245
Directory	/workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.4058196737
Short name	T886
Test name
Test status
Simulation time	18367125300 ps
CPU time	155.12 seconds
Started	Jul 23 04:44:10 PM PDT 24
Finished	Jul 23 04:46:49 PM PDT 24
Peak memory	259884 kb
Host	smart-4f3b34dc-b8da-4efa-b793-75a6e7a97134
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405 8196737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.4058196737
Directory	/workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_invalid_op.27810073
Short name	T500
Test name
Test status
Simulation time	1003755000 ps
CPU time	87.75 seconds
Started	Jul 23 04:44:02 PM PDT 24
Finished	Jul 23 04:45:32 PM PDT 24
Peak memory	263436 kb
Host	smart-417b857c-e7c4-48e4-92b4-23dc0d143d05
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27810073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.27810073
Directory	/workspace/2.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/2.flash_ctrl_lcmgr_intg.709498435
Short name	T685
Test name
Test status
Simulation time	45985900 ps
CPU time	13.33 seconds
Started	Jul 23 04:44:08 PM PDT 24
Finished	Jul 23 04:44:24 PM PDT 24
Peak memory	259912 kb
Host	smart-23098b27-e6f1-4f27-88ce-bbbd2b01698e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709498435 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.709498435
Directory	/workspace/2.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mid_op_rst.496211078
Short name	T213
Test name
Test status
Simulation time	1312536200 ps
CPU time	66.52 seconds
Started	Jul 23 04:43:58 PM PDT 24
Finished	Jul 23 04:45:09 PM PDT 24
Peak memory	260652 kb
Host	smart-67860b7c-4431-4b39-a784-7e27ef51c07d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=496211078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.496211078
Directory	/workspace/2.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/2.flash_ctrl_otp_reset.2147728768
Short name	T616
Test name
Test status
Simulation time	82116800 ps
CPU time	109.28 seconds
Started	Jul 23 04:44:00 PM PDT 24
Finished	Jul 23 04:45:53 PM PDT 24
Peak memory	261040 kb
Host	smart-1d72b9c8-1f8c-4dd6-a8ad-3759c873b5f8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147728768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot p_reset.2147728768
Directory	/workspace/2.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb.4147414227
Short name	T637
Test name
Test status
Simulation time	49871400 ps
CPU time	69.09 seconds
Started	Jul 23 04:43:59 PM PDT 24
Finished	Jul 23 04:45:12 PM PDT 24
Peak memory	263240 kb
Host	smart-5e95aad4-42fa-4148-9859-f88b76a37a81
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4147414227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.4147414227
Directory	/workspace/2.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.482662194
Short name	T246
Test name
Test status
Simulation time	40998100 ps
CPU time	14.05 seconds
Started	Jul 23 04:44:13 PM PDT 24
Finished	Jul 23 04:44:30 PM PDT 24
Peak memory	262916 kb
Host	smart-a4a5ad3e-61bc-4bfe-bfd8-4a37b670eeb3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482662194 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.482662194
Directory	/workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_prog_reset.2137032942
Short name	T739
Test name
Test status
Simulation time	5479851300 ps
CPU time	200.45 seconds
Started	Jul 23 04:45:20 PM PDT 24
Finished	Jul 23 04:48:41 PM PDT 24
Peak memory	264956 kb
Host	smart-c867a62b-7191-47dc-9817-9256c8568dbb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137032942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.flash_ctrl_prog_reset.2137032942
Directory	/workspace/2.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rand_ops.3843437059
Short name	T984
Test name
Test status
Simulation time	3200595500 ps
CPU time	975.84 seconds
Started	Jul 23 04:44:00 PM PDT 24
Finished	Jul 23 05:00:19 PM PDT 24
Peak memory	286252 kb
Host	smart-d68568fa-8a16-484a-a64d-de5e8b7a40bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843437059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.3843437059
Directory	/workspace/2.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_buff_evict.4243061432
Short name	T634
Test name
Test status
Simulation time	2917517700 ps
CPU time	149.81 seconds
Started	Jul 23 04:43:59 PM PDT 24
Finished	Jul 23 04:46:32 PM PDT 24
Peak memory	262980 kb
Host	smart-5973ddf4-2018-44d4-9411-b9e226b84719
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4243061432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.4243061432
Directory	/workspace/2.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_intg.1923962030
Short name	T43
Test name
Test status
Simulation time	63875500 ps
CPU time	30.66 seconds
Started	Jul 23 04:45:10 PM PDT 24
Finished	Jul 23 04:45:42 PM PDT 24
Peak memory	279384 kb
Host	smart-54a8231a-4c63-460b-8af4-d2d070938376
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923962030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.flash_ctrl_rd_intg.1923962030
Directory	/workspace/2.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_re_evict.670424823
Short name	T843
Test name
Test status
Simulation time	731627700 ps
CPU time	34.87 seconds
Started	Jul 23 04:44:16 PM PDT 24
Finished	Jul 23 04:44:53 PM PDT 24
Peak memory	268452 kb
Host	smart-74450d81-5ed2-4410-91c6-6182ee4ba413
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670424823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_re_evict.670424823
Directory	/workspace/2.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.3802219837
Short name	T944
Test name
Test status
Simulation time	39682600 ps
CPU time	22.53 seconds
Started	Jul 23 04:44:13 PM PDT 24
Finished	Jul 23 04:44:39 PM PDT 24
Peak memory	264808 kb
Host	smart-086174d4-78cd-424c-8a61-432fa761802c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802219837 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.3802219837
Directory	/workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.2438134789
Short name	T497
Test name
Test status
Simulation time	23987500 ps
CPU time	23.19 seconds
Started	Jul 23 04:44:09 PM PDT 24
Finished	Jul 23 04:44:35 PM PDT 24
Peak memory	265304 kb
Host	smart-727b7d47-3643-417e-a1d8-ae4a4774d801
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438134789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl ash_ctrl_read_word_sweep_serr.2438134789
Directory	/workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rma_err.546476504
Short name	T188
Test name
Test status
Simulation time	83547767900 ps
CPU time	919.51 seconds
Started	Jul 23 04:44:14 PM PDT 24
Finished	Jul 23 04:59:37 PM PDT 24
Peak memory	261332 kb
Host	smart-1e2c4856-68c8-4560-9644-d71464aee340
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546476504 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.546476504
Directory	/workspace/2.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro.3977476986
Short name	T1
Test name
Test status
Simulation time	560106200 ps
CPU time	106.22 seconds
Started	Jul 23 04:43:57 PM PDT 24
Finished	Jul 23 04:45:47 PM PDT 24
Peak memory	281116 kb
Host	smart-8610bd60-1f99-480c-8879-a2b3228bea1d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977476986 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_ro.3977476986
Directory	/workspace/2.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_derr.3875314077
Short name	T217
Test name
Test status
Simulation time	1218188200 ps
CPU time	147.68 seconds
Started	Jul 23 04:44:12 PM PDT 24
Finished	Jul 23 04:46:43 PM PDT 24
Peak memory	281788 kb
Host	smart-f584cafa-3525-4197-9f56-6aa33306274c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3875314077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.3875314077
Directory	/workspace/2.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_serr.410893856
Short name	T675
Test name
Test status
Simulation time	1269333600 ps
CPU time	143.44 seconds
Started	Jul 23 04:44:09 PM PDT 24
Finished	Jul 23 04:46:35 PM PDT 24
Peak memory	281732 kb
Host	smart-dcb6df04-aa6e-48ed-81de-a57de6d3f272
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410893856 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.410893856
Directory	/workspace/2.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw.1844924949
Short name	T129
Test name
Test status
Simulation time	7226014500 ps
CPU time	576.09 seconds
Started	Jul 23 04:44:15 PM PDT 24
Finished	Jul 23 04:53:54 PM PDT 24
Peak memory	314284 kb
Host	smart-8fcf30d0-88e6-4506-914a-a77fe3b8eb0c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844924949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.flash_ctrl_rw.1844924949
Directory	/workspace/2.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_derr.935429784
Short name	T1060
Test name
Test status
Simulation time	40319209000 ps
CPU time	784.35 seconds
Started	Jul 23 04:44:13 PM PDT 24
Finished	Jul 23 04:57:21 PM PDT 24
Peak memory	344728 kb
Host	smart-c8341b3e-fd25-4644-ae7e-4e494c142f79
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935429784 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.flash_ctrl_rw_derr.935429784
Directory	/workspace/2.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_evict.984689125
Short name	T431
Test name
Test status
Simulation time	181204600 ps
CPU time	28.86 seconds
Started	Jul 23 04:44:09 PM PDT 24
Finished	Jul 23 04:44:42 PM PDT 24
Peak memory	275680 kb
Host	smart-2fcb8e97-52d6-4eb9-8e4d-963d55abbd77
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984689125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_rw_evict.984689125
Directory	/workspace/2.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.2197368448
Short name	T765
Test name
Test status
Simulation time	26192800 ps
CPU time	30.97 seconds
Started	Jul 23 04:44:10 PM PDT 24
Finished	Jul 23 04:44:45 PM PDT 24
Peak memory	275724 kb
Host	smart-6de5d0c8-dd6c-4f40-9345-9cd178442c97
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197368448 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.2197368448
Directory	/workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_cm.3645238703
Short name	T115
Test name
Test status
Simulation time	2864478700 ps
CPU time	4674.85 seconds
Started	Jul 23 04:44:11 PM PDT 24
Finished	Jul 23 06:02:11 PM PDT 24
Peak memory	289168 kb
Host	smart-af5f0354-fee4-4943-af1a-a5704d25285c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645238703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.3645238703
Directory	/workspace/2.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_info_access.845523933
Short name	T679
Test name
Test status
Simulation time	3254688800 ps
CPU time	79.17 seconds
Started	Jul 23 04:44:09 PM PDT 24
Finished	Jul 23 04:45:32 PM PDT 24
Peak memory	264728 kb
Host	smart-48ae834b-bca7-4df4-b79f-8c170b139e21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=845523933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.845523933
Directory	/workspace/2.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_address.2106671149
Short name	T468
Test name
Test status
Simulation time	9089879600 ps
CPU time	80.07 seconds
Started	Jul 23 04:44:15 PM PDT 24
Finished	Jul 23 04:45:38 PM PDT 24
Peak memory	265328 kb
Host	smart-f115ff3f-fe22-47d6-8c51-9147211e607a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106671149 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_serr_address.2106671149
Directory	/workspace/2.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_counter.195591506
Short name	T132
Test name
Test status
Simulation time	3270056800 ps
CPU time	88.66 seconds
Started	Jul 23 04:44:09 PM PDT 24
Finished	Jul 23 04:45:41 PM PDT 24
Peak memory	274032 kb
Host	smart-d605b752-13cf-4c71-bccd-26bec269f385
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195591506 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_serr_counter.195591506
Directory	/workspace/2.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke.2248560195
Short name	T1063
Test name
Test status
Simulation time	64503900 ps
CPU time	76.16 seconds
Started	Jul 23 04:43:58 PM PDT 24
Finished	Jul 23 04:45:18 PM PDT 24
Peak memory	275392 kb
Host	smart-f698ca53-e0ad-492b-a525-27a2882dce1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2248560195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.2248560195
Directory	/workspace/2.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke_hw.1221387154
Short name	T56
Test name
Test status
Simulation time	30682100 ps
CPU time	23.86 seconds
Started	Jul 23 04:43:57 PM PDT 24
Finished	Jul 23 04:44:25 PM PDT 24
Peak memory	259596 kb
Host	smart-6cfafc4c-5aa0-4ee3-a1d5-4ed5a6bf9bae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1221387154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.1221387154
Directory	/workspace/2.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_stress_all.1194713412
Short name	T495
Test name
Test status
Simulation time	922363500 ps
CPU time	1446.34 seconds
Started	Jul 23 04:44:08 PM PDT 24
Finished	Jul 23 05:08:17 PM PDT 24
Peak memory	288664 kb
Host	smart-7c55639e-9303-42f7-857a-e3a25a74ef12
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194713412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres s_all.1194713412
Directory	/workspace/2.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sw_op.2674463171
Short name	T1003
Test name
Test status
Simulation time	22221700 ps
CPU time	26.71 seconds
Started	Jul 23 04:43:59 PM PDT 24
Finished	Jul 23 04:44:30 PM PDT 24
Peak memory	259720 kb
Host	smart-63d05cf3-5482-4f59-ae9b-009335efe167
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2674463171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.2674463171
Directory	/workspace/2.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/2.flash_ctrl_wo.3077288208
Short name	T51
Test name
Test status
Simulation time	28796148000 ps
CPU time	213.38 seconds
Started	Jul 23 04:43:59 PM PDT 24
Finished	Jul 23 04:47:36 PM PDT 24
Peak memory	259816 kb
Host	smart-94aa2d71-d1c9-45bf-a459-0d622ef63415
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077288208 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.flash_ctrl_wo.3077288208
Directory	/workspace/2.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/20.flash_ctrl_alert_test.4237247908
Short name	T512
Test name
Test status
Simulation time	61031700 ps
CPU time	13.5 seconds
Started	Jul 23 04:46:24 PM PDT 24
Finished	Jul 23 04:46:39 PM PDT 24
Peak memory	258408 kb
Host	smart-eed8cd6f-9732-48b8-af22-4541a8ae3ff2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237247908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test. 4237247908
Directory	/workspace/20.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.flash_ctrl_connect.1882964542
Short name	T910
Test name
Test status
Simulation time	26234800 ps
CPU time	15.85 seconds
Started	Jul 23 04:46:26 PM PDT 24
Finished	Jul 23 04:46:43 PM PDT 24
Peak memory	274952 kb
Host	smart-083354d1-ebdc-4597-9bea-1f9194236040
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1882964542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.1882964542
Directory	/workspace/20.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/20.flash_ctrl_disable.1303907719
Short name	T421
Test name
Test status
Simulation time	26502200 ps
CPU time	22.06 seconds
Started	Jul 23 04:46:27 PM PDT 24
Finished	Jul 23 04:46:50 PM PDT 24
Peak memory	273480 kb
Host	smart-d3489c42-3cfc-4e82-acbf-c2a56b11c195
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303907719 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_disable.1303907719
Directory	/workspace/20.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/20.flash_ctrl_hw_sec_otp.3681596682
Short name	T748
Test name
Test status
Simulation time	52749223900 ps
CPU time	252.5 seconds
Started	Jul 23 04:46:17 PM PDT 24
Finished	Jul 23 04:50:31 PM PDT 24
Peak memory	260912 kb
Host	smart-d5ebb77d-a97a-4cbc-819a-7d318a6ca733
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681596682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_ hw_sec_otp.3681596682
Directory	/workspace/20.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.155972517
Short name	T357
Test name
Test status
Simulation time	50057234900 ps
CPU time	564.07 seconds
Started	Jul 23 04:46:28 PM PDT 24
Finished	Jul 23 04:55:53 PM PDT 24
Peak memory	284872 kb
Host	smart-09ddfa54-18eb-4f1e-9de0-fa4beeb9373b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155972517 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.155972517
Directory	/workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/20.flash_ctrl_otp_reset.4107963229
Short name	T336
Test name
Test status
Simulation time	67930300 ps
CPU time	131.75 seconds
Started	Jul 23 04:46:24 PM PDT 24
Finished	Jul 23 04:48:37 PM PDT 24
Peak memory	260192 kb
Host	smart-87bc4421-6038-4983-8bef-af0e7e56087d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107963229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o tp_reset.4107963229
Directory	/workspace/20.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_prog_reset.1722681071
Short name	T393
Test name
Test status
Simulation time	101113100 ps
CPU time	13.6 seconds
Started	Jul 23 04:46:28 PM PDT 24
Finished	Jul 23 04:46:42 PM PDT 24
Peak memory	259200 kb
Host	smart-b4bbc161-6f29-4685-a79f-6b765d2c4c50
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722681071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.flash_ctrl_prog_reset.1722681071
Directory	/workspace/20.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.3685770230
Short name	T631
Test name
Test status
Simulation time	29611900 ps
CPU time	30.95 seconds
Started	Jul 23 04:46:26 PM PDT 24
Finished	Jul 23 04:46:58 PM PDT 24
Peak memory	268464 kb
Host	smart-55c45ee4-de6f-4409-bc5a-ffdf7504e171
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685770230 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.3685770230
Directory	/workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/20.flash_ctrl_sec_info_access.1569744466
Short name	T163
Test name
Test status
Simulation time	1706898000 ps
CPU time	65.01 seconds
Started	Jul 23 04:46:24 PM PDT 24
Finished	Jul 23 04:47:30 PM PDT 24
Peak memory	262964 kb
Host	smart-c5c3755a-4c2a-42a8-aa15-84835f6174e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1569744466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.1569744466
Directory	/workspace/20.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/20.flash_ctrl_smoke.2130662062
Short name	T991
Test name
Test status
Simulation time	32486900 ps
CPU time	49.29 seconds
Started	Jul 23 04:46:16 PM PDT 24
Finished	Jul 23 04:47:07 PM PDT 24
Peak memory	271328 kb
Host	smart-4ba07a79-1e46-4cf7-ba1f-2171a554ab74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2130662062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.2130662062
Directory	/workspace/20.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.flash_ctrl_alert_test.1204503345
Short name	T784
Test name
Test status
Simulation time	313288200 ps
CPU time	14.06 seconds
Started	Jul 23 04:46:27 PM PDT 24
Finished	Jul 23 04:46:42 PM PDT 24
Peak memory	265260 kb
Host	smart-478e3521-b640-41e1-8c1a-00691dd9607a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204503345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test. 1204503345
Directory	/workspace/21.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.flash_ctrl_connect.1313851741
Short name	T482
Test name
Test status
Simulation time	26337800 ps
CPU time	13.37 seconds
Started	Jul 23 04:46:29 PM PDT 24
Finished	Jul 23 04:46:43 PM PDT 24
Peak memory	284244 kb
Host	smart-eae4ccb0-567f-4fc4-b841-9a948bd106dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1313851741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.1313851741
Directory	/workspace/21.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/21.flash_ctrl_disable.1181489226
Short name	T976
Test name
Test status
Simulation time	10679900 ps
CPU time	20.49 seconds
Started	Jul 23 04:46:25 PM PDT 24
Finished	Jul 23 04:46:46 PM PDT 24
Peak memory	273580 kb
Host	smart-988d8623-ecb8-4595-b64a-8d31925ab0a0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181489226 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_disable.1181489226
Directory	/workspace/21.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/21.flash_ctrl_hw_sec_otp.13617711
Short name	T1058
Test name
Test status
Simulation time	8669886900 ps
CPU time	183.22 seconds
Started	Jul 23 04:46:24 PM PDT 24
Finished	Jul 23 04:49:29 PM PDT 24
Peak memory	262272 kb
Host	smart-cf6f8ed7-6a89-43c5-a0d3-56d805fb08af
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13617711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_hw _sec_otp.13617711
Directory	/workspace/21.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd.1979715513
Short name	T838
Test name
Test status
Simulation time	3369940000 ps
CPU time	205.89 seconds
Started	Jul 23 04:46:26 PM PDT 24
Finished	Jul 23 04:49:53 PM PDT 24
Peak memory	284848 kb
Host	smart-bb3db8b3-b4a3-40a5-96b7-a89fa7ccc52c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979715513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla sh_ctrl_intr_rd.1979715513
Directory	/workspace/21.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.2125185755
Short name	T557
Test name
Test status
Simulation time	38599540300 ps
CPU time	293.06 seconds
Started	Jul 23 04:46:26 PM PDT 24
Finished	Jul 23 04:51:20 PM PDT 24
Peak memory	289904 kb
Host	smart-6603d72e-d6a9-41c3-a41c-6d4801805460
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125185755 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.2125185755
Directory	/workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/21.flash_ctrl_otp_reset.416348970
Short name	T696
Test name
Test status
Simulation time	36240800 ps
CPU time	131.39 seconds
Started	Jul 23 04:46:27 PM PDT 24
Finished	Jul 23 04:48:40 PM PDT 24
Peak memory	260024 kb
Host	smart-85545333-64e0-46f1-b04a-52fc3eb869fb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416348970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_ot p_reset.416348970
Directory	/workspace/21.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_prog_reset.1912704494
Short name	T505
Test name
Test status
Simulation time	37364200 ps
CPU time	13.49 seconds
Started	Jul 23 04:46:27 PM PDT 24
Finished	Jul 23 04:46:41 PM PDT 24
Peak memory	265264 kb
Host	smart-72bf9a47-42aa-4190-8ba1-1e1853598c96
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912704494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.flash_ctrl_prog_reset.1912704494
Directory	/workspace/21.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_rw_evict.918979121
Short name	T514
Test name
Test status
Simulation time	33595100 ps
CPU time	28.92 seconds
Started	Jul 23 04:46:29 PM PDT 24
Finished	Jul 23 04:46:59 PM PDT 24
Peak memory	275684 kb
Host	smart-3318e3d9-1948-4809-ad77-f6df4ee66496
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918979121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla sh_ctrl_rw_evict.918979121
Directory	/workspace/21.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.1768947722
Short name	T763
Test name
Test status
Simulation time	28184900 ps
CPU time	31.01 seconds
Started	Jul 23 04:46:29 PM PDT 24
Finished	Jul 23 04:47:01 PM PDT 24
Peak memory	268512 kb
Host	smart-dd83e752-7a21-4a6a-b792-66f687a0af3d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768947722 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.1768947722
Directory	/workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/21.flash_ctrl_sec_info_access.1103079350
Short name	T407
Test name
Test status
Simulation time	350181700 ps
CPU time	54.39 seconds
Started	Jul 23 04:46:28 PM PDT 24
Finished	Jul 23 04:47:24 PM PDT 24
Peak memory	263564 kb
Host	smart-0f463cc9-c3a3-4c83-a378-febb4f746e32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1103079350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.1103079350
Directory	/workspace/21.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/21.flash_ctrl_smoke.1192329614
Short name	T513
Test name
Test status
Simulation time	110724600 ps
CPU time	172.49 seconds
Started	Jul 23 04:46:26 PM PDT 24
Finished	Jul 23 04:49:20 PM PDT 24
Peak memory	277356 kb
Host	smart-fa56d5ec-1e99-460e-a253-bd2ed24d2111
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1192329614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.1192329614
Directory	/workspace/21.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.flash_ctrl_alert_test.368595916
Short name	T989
Test name
Test status
Simulation time	99349900 ps
CPU time	13.82 seconds
Started	Jul 23 04:46:37 PM PDT 24
Finished	Jul 23 04:46:54 PM PDT 24
Peak memory	265312 kb
Host	smart-d2aefbb1-1348-4b83-a314-0202bf85ad3e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368595916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.368595916
Directory	/workspace/22.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.flash_ctrl_connect.2426734617
Short name	T1016
Test name
Test status
Simulation time	45807100 ps
CPU time	13.46 seconds
Started	Jul 23 04:46:35 PM PDT 24
Finished	Jul 23 04:46:50 PM PDT 24
Peak memory	274900 kb
Host	smart-4fdf9a31-732c-4c6f-a891-4366eebb6daf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2426734617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.2426734617
Directory	/workspace/22.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/22.flash_ctrl_disable.1393763177
Short name	T819
Test name
Test status
Simulation time	13752700 ps
CPU time	22 seconds
Started	Jul 23 04:46:42 PM PDT 24
Finished	Jul 23 04:47:06 PM PDT 24
Peak memory	273644 kb
Host	smart-02048aed-dece-422c-8259-65df3b190b7b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393763177 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_disable.1393763177
Directory	/workspace/22.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/22.flash_ctrl_intr_rd.948394714
Short name	T1019
Test name
Test status
Simulation time	855910500 ps
CPU time	154.84 seconds
Started	Jul 23 04:46:36 PM PDT 24
Finished	Jul 23 04:49:13 PM PDT 24
Peak memory	293296 kb
Host	smart-77cb4994-7a42-439b-80c9-5e718eb9e250
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948394714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flas h_ctrl_intr_rd.948394714
Directory	/workspace/22.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1375284955
Short name	T366
Test name
Test status
Simulation time	12042298300 ps
CPU time	276.97 seconds
Started	Jul 23 04:46:35 PM PDT 24
Finished	Jul 23 04:51:13 PM PDT 24
Peak memory	292044 kb
Host	smart-37459292-2511-4305-a35f-d2a275e758b6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375284955 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.1375284955
Directory	/workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/22.flash_ctrl_otp_reset.2081279774
Short name	T175
Test name
Test status
Simulation time	64835600 ps
CPU time	131.76 seconds
Started	Jul 23 04:46:34 PM PDT 24
Finished	Jul 23 04:48:47 PM PDT 24
Peak memory	261132 kb
Host	smart-05210ab6-5a83-4f34-ba52-d75a52bc261c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081279774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o tp_reset.2081279774
Directory	/workspace/22.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/22.flash_ctrl_prog_reset.205226536
Short name	T552
Test name
Test status
Simulation time	22060100 ps
CPU time	13.85 seconds
Started	Jul 23 04:46:36 PM PDT 24
Finished	Jul 23 04:46:53 PM PDT 24
Peak memory	258984 kb
Host	smart-329e2100-0a45-4106-835c-f495569cc8af
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205226536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.flash_ctrl_prog_reset.205226536
Directory	/workspace/22.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/22.flash_ctrl_rw_evict.868947672
Short name	T203
Test name
Test status
Simulation time	75654200 ps
CPU time	31.27 seconds
Started	Jul 23 04:46:35 PM PDT 24
Finished	Jul 23 04:47:08 PM PDT 24
Peak memory	273628 kb
Host	smart-8e187058-753a-4068-9c49-e013403a32f1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868947672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla sh_ctrl_rw_evict.868947672
Directory	/workspace/22.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.3163336993
Short name	T881
Test name
Test status
Simulation time	63936200 ps
CPU time	31.55 seconds
Started	Jul 23 04:46:34 PM PDT 24
Finished	Jul 23 04:47:06 PM PDT 24
Peak memory	275580 kb
Host	smart-16772da3-3688-4674-ac58-b5096984a776
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163336993 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.3163336993
Directory	/workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/22.flash_ctrl_sec_info_access.1786280550
Short name	T349
Test name
Test status
Simulation time	1717428200 ps
CPU time	60.18 seconds
Started	Jul 23 04:46:35 PM PDT 24
Finished	Jul 23 04:47:37 PM PDT 24
Peak memory	263676 kb
Host	smart-a35f7017-426c-4f9e-bf9f-d72168768a2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786280550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.1786280550
Directory	/workspace/22.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/22.flash_ctrl_smoke.3943739769
Short name	T969
Test name
Test status
Simulation time	30368600 ps
CPU time	125.17 seconds
Started	Jul 23 04:46:29 PM PDT 24
Finished	Jul 23 04:48:35 PM PDT 24
Peak memory	276584 kb
Host	smart-1cffca92-acbd-42f2-811f-3f2bf031a63e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3943739769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.3943739769
Directory	/workspace/22.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.flash_ctrl_alert_test.3580785302
Short name	T661
Test name
Test status
Simulation time	52501600 ps
CPU time	13.5 seconds
Started	Jul 23 04:46:36 PM PDT 24
Finished	Jul 23 04:46:52 PM PDT 24
Peak memory	265300 kb
Host	smart-19769ec4-e148-433c-9ca8-fbcbb88144b7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580785302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test. 3580785302
Directory	/workspace/23.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.flash_ctrl_connect.500517744
Short name	T907
Test name
Test status
Simulation time	69388000 ps
CPU time	15.61 seconds
Started	Jul 23 04:46:35 PM PDT 24
Finished	Jul 23 04:46:53 PM PDT 24
Peak memory	274832 kb
Host	smart-1b8b4b17-4746-4b43-bfe9-5b88d38c5e67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=500517744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.500517744
Directory	/workspace/23.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/23.flash_ctrl_disable.3333177347
Short name	T729
Test name
Test status
Simulation time	13458400 ps
CPU time	22.3 seconds
Started	Jul 23 04:46:39 PM PDT 24
Finished	Jul 23 04:47:03 PM PDT 24
Peak memory	273588 kb
Host	smart-c4bc8d88-ec1e-4822-b014-cf847f98e8c8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333177347 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_disable.3333177347
Directory	/workspace/23.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/23.flash_ctrl_hw_sec_otp.138452435
Short name	T1005
Test name
Test status
Simulation time	40855078800 ps
CPU time	111.38 seconds
Started	Jul 23 04:46:37 PM PDT 24
Finished	Jul 23 04:48:31 PM PDT 24
Peak memory	263184 kb
Host	smart-e341c0fa-aa19-4342-bebe-ac0f1854aa59
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138452435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_h w_sec_otp.138452435
Directory	/workspace/23.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd.3483195607
Short name	T878
Test name
Test status
Simulation time	778979900 ps
CPU time	145.52 seconds
Started	Jul 23 04:46:36 PM PDT 24
Finished	Jul 23 04:49:03 PM PDT 24
Peak memory	294148 kb
Host	smart-995ee338-c213-4202-b9f9-79fadded1d52
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483195607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla sh_ctrl_intr_rd.3483195607
Directory	/workspace/23.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.529008539
Short name	T832
Test name
Test status
Simulation time	23830372200 ps
CPU time	163.03 seconds
Started	Jul 23 04:46:36 PM PDT 24
Finished	Jul 23 04:49:21 PM PDT 24
Peak memory	292504 kb
Host	smart-a08c5ca9-2a06-4738-b3b8-df40af2ef909
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529008539 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.529008539
Directory	/workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/23.flash_ctrl_otp_reset.3766912693
Short name	T508
Test name
Test status
Simulation time	144107100 ps
CPU time	132.37 seconds
Started	Jul 23 04:46:35 PM PDT 24
Finished	Jul 23 04:48:50 PM PDT 24
Peak memory	261052 kb
Host	smart-b91f0aef-f3be-4a11-8f52-030252596730
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766912693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o tp_reset.3766912693
Directory	/workspace/23.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/23.flash_ctrl_prog_reset.3571732175
Short name	T153
Test name
Test status
Simulation time	1925559400 ps
CPU time	158.83 seconds
Started	Jul 23 04:46:36 PM PDT 24
Finished	Jul 23 04:49:17 PM PDT 24
Peak memory	260040 kb
Host	smart-9437a71d-65b3-4791-98b7-e78fb4783fc9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571732175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.flash_ctrl_prog_reset.3571732175
Directory	/workspace/23.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/23.flash_ctrl_rw_evict.3220705535
Short name	T229
Test name
Test status
Simulation time	41421900 ps
CPU time	31.65 seconds
Started	Jul 23 04:46:36 PM PDT 24
Finished	Jul 23 04:47:10 PM PDT 24
Peak memory	268460 kb
Host	smart-b9751bff-6e06-471b-b27d-9b203dd0c2e5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220705535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl ash_ctrl_rw_evict.3220705535
Directory	/workspace/23.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.3288115858
Short name	T850
Test name
Test status
Simulation time	128648600 ps
CPU time	30.74 seconds
Started	Jul 23 04:46:36 PM PDT 24
Finished	Jul 23 04:47:09 PM PDT 24
Peak memory	267544 kb
Host	smart-11abb60c-55a2-4746-89f6-790ee54962f5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288115858 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.3288115858
Directory	/workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/23.flash_ctrl_smoke.3337243323
Short name	T601
Test name
Test status
Simulation time	50020400 ps
CPU time	77.66 seconds
Started	Jul 23 04:46:36 PM PDT 24
Finished	Jul 23 04:47:55 PM PDT 24
Peak memory	275588 kb
Host	smart-a4a5297e-fc25-42c6-9333-56997769bce7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3337243323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.3337243323
Directory	/workspace/23.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.flash_ctrl_alert_test.1090408908
Short name	T467
Test name
Test status
Simulation time	49722100 ps
CPU time	13.46 seconds
Started	Jul 23 04:46:43 PM PDT 24
Finished	Jul 23 04:47:00 PM PDT 24
Peak memory	265232 kb
Host	smart-9b2f2257-7784-4561-ae6f-9ed9a163490a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090408908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test. 1090408908
Directory	/workspace/24.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.flash_ctrl_connect.2618927713
Short name	T537
Test name
Test status
Simulation time	13666600 ps
CPU time	13.82 seconds
Started	Jul 23 04:46:43 PM PDT 24
Finished	Jul 23 04:47:00 PM PDT 24
Peak memory	275008 kb
Host	smart-19a892cf-d66d-4b2c-8a4e-70a9b29d753a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618927713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.2618927713
Directory	/workspace/24.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/24.flash_ctrl_disable.1903493814
Short name	T101
Test name
Test status
Simulation time	17914300 ps
CPU time	21.76 seconds
Started	Jul 23 04:46:42 PM PDT 24
Finished	Jul 23 04:47:06 PM PDT 24
Peak memory	273628 kb
Host	smart-86ec18c3-6eb1-411f-b04c-2b690dfc33bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903493814 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_disable.1903493814
Directory	/workspace/24.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/24.flash_ctrl_hw_sec_otp.3718117489
Short name	T559
Test name
Test status
Simulation time	2204380900 ps
CPU time	84.11 seconds
Started	Jul 23 04:46:42 PM PDT 24
Finished	Jul 23 04:48:09 PM PDT 24
Peak memory	261028 kb
Host	smart-0a5dbe33-a959-4f7e-977a-ae0de11db985
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718117489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_ hw_sec_otp.3718117489
Directory	/workspace/24.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.1462313550
Short name	T628
Test name
Test status
Simulation time	58458900900 ps
CPU time	158.34 seconds
Started	Jul 23 04:46:37 PM PDT 24
Finished	Jul 23 04:49:18 PM PDT 24
Peak memory	293100 kb
Host	smart-ee93cd70-801d-4717-a2a2-bdafe96dd331
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462313550 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.1462313550
Directory	/workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/24.flash_ctrl_otp_reset.1952003511
Short name	T1065
Test name
Test status
Simulation time	151510100 ps
CPU time	130.3 seconds
Started	Jul 23 04:46:42 PM PDT 24
Finished	Jul 23 04:48:54 PM PDT 24
Peak memory	260504 kb
Host	smart-814855de-b1fe-4be9-a517-98bc62d7e291
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952003511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o tp_reset.1952003511
Directory	/workspace/24.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_prog_reset.3867712068
Short name	T119
Test name
Test status
Simulation time	41917700 ps
CPU time	13.49 seconds
Started	Jul 23 04:46:37 PM PDT 24
Finished	Jul 23 04:46:53 PM PDT 24
Peak memory	259044 kb
Host	smart-7b11f26e-7a27-4b5f-9bac-dfbbdf9b81b0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867712068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.flash_ctrl_prog_reset.3867712068
Directory	/workspace/24.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_rw_evict.3306005643
Short name	T202
Test name
Test status
Simulation time	44910800 ps
CPU time	31.24 seconds
Started	Jul 23 04:46:42 PM PDT 24
Finished	Jul 23 04:47:15 PM PDT 24
Peak memory	275720 kb
Host	smart-7a710bc9-e47d-4ced-8a69-446a9a3ae5f6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306005643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl ash_ctrl_rw_evict.3306005643
Directory	/workspace/24.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.2150222388
Short name	T25
Test name
Test status
Simulation time	40700200 ps
CPU time	27.87 seconds
Started	Jul 23 04:46:37 PM PDT 24
Finished	Jul 23 04:47:07 PM PDT 24
Peak memory	275624 kb
Host	smart-fc176a0b-ef38-4600-8045-5ad945d8ede6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150222388 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.2150222388
Directory	/workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/24.flash_ctrl_smoke.458814418
Short name	T636
Test name
Test status
Simulation time	56933500 ps
CPU time	99.24 seconds
Started	Jul 23 04:46:38 PM PDT 24
Finished	Jul 23 04:48:20 PM PDT 24
Peak memory	276372 kb
Host	smart-6b401670-348a-44fc-92d5-69d01bbea490
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=458814418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.458814418
Directory	/workspace/24.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.flash_ctrl_alert_test.2777630787
Short name	T470
Test name
Test status
Simulation time	42519100 ps
CPU time	13.79 seconds
Started	Jul 23 04:46:50 PM PDT 24
Finished	Jul 23 04:47:12 PM PDT 24
Peak memory	258296 kb
Host	smart-3701e073-a9c0-4866-8cc0-c6573e7c0c79
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777630787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test. 2777630787
Directory	/workspace/25.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.flash_ctrl_connect.1341860050
Short name	T665
Test name
Test status
Simulation time	15346200 ps
CPU time	15.56 seconds
Started	Jul 23 04:46:50 PM PDT 24
Finished	Jul 23 04:47:13 PM PDT 24
Peak memory	284392 kb
Host	smart-1c6c08f3-d030-46b2-9536-42c6adebf392
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1341860050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.1341860050
Directory	/workspace/25.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/25.flash_ctrl_hw_sec_otp.3161124606
Short name	T338
Test name
Test status
Simulation time	12698719500 ps
CPU time	228.71 seconds
Started	Jul 23 04:46:45 PM PDT 24
Finished	Jul 23 04:50:40 PM PDT 24
Peak memory	260948 kb
Host	smart-eabe4b4c-6600-4dd0-9ff0-81c7946e68d0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161124606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_ hw_sec_otp.3161124606
Directory	/workspace/25.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd.3553911251
Short name	T722
Test name
Test status
Simulation time	1474946400 ps
CPU time	140.7 seconds
Started	Jul 23 04:46:45 PM PDT 24
Finished	Jul 23 04:49:11 PM PDT 24
Peak memory	292936 kb
Host	smart-c115d954-cc68-45fd-bb78-b228c1cc2560
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553911251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla sh_ctrl_intr_rd.3553911251
Directory	/workspace/25.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.2078627959
Short name	T504
Test name
Test status
Simulation time	11786725600 ps
CPU time	140.22 seconds
Started	Jul 23 04:46:45 PM PDT 24
Finished	Jul 23 04:49:11 PM PDT 24
Peak memory	293028 kb
Host	smart-4d893f3a-0237-47f9-95ef-d64be9f48b1e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078627959 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.2078627959
Directory	/workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/25.flash_ctrl_otp_reset.2873480680
Short name	T541
Test name
Test status
Simulation time	197410800 ps
CPU time	129.25 seconds
Started	Jul 23 04:46:44 PM PDT 24
Finished	Jul 23 04:48:57 PM PDT 24
Peak memory	260360 kb
Host	smart-4b0a0e62-0dba-423b-a1c5-2f53b6f6b932
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873480680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o tp_reset.2873480680
Directory	/workspace/25.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_prog_reset.886153789
Short name	T848
Test name
Test status
Simulation time	2421999400 ps
CPU time	201.24 seconds
Started	Jul 23 04:46:45 PM PDT 24
Finished	Jul 23 04:50:12 PM PDT 24
Peak memory	259988 kb
Host	smart-c3b5f112-4822-437b-93b1-1095f4315c25
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886153789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.flash_ctrl_prog_reset.886153789
Directory	/workspace/25.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict.1800931619
Short name	T589
Test name
Test status
Simulation time	31985600 ps
CPU time	30.73 seconds
Started	Jul 23 04:46:49 PM PDT 24
Finished	Jul 23 04:47:28 PM PDT 24
Peak memory	273536 kb
Host	smart-43892ea3-13dc-486a-a94e-e2cf3f3f4ee0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800931619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl ash_ctrl_rw_evict.1800931619
Directory	/workspace/25.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.3278073151
Short name	T440
Test name
Test status
Simulation time	29758400 ps
CPU time	30.89 seconds
Started	Jul 23 04:46:44 PM PDT 24
Finished	Jul 23 04:47:18 PM PDT 24
Peak memory	275732 kb
Host	smart-cd154705-0723-4cda-870e-adc748125f6f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278073151 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.3278073151
Directory	/workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/25.flash_ctrl_sec_info_access.1579807589
Short name	T411
Test name
Test status
Simulation time	481156800 ps
CPU time	60.56 seconds
Started	Jul 23 04:46:44 PM PDT 24
Finished	Jul 23 04:47:49 PM PDT 24
Peak memory	263120 kb
Host	smart-10840ed7-699b-4602-8178-b1843fca5967
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1579807589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1579807589
Directory	/workspace/25.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/25.flash_ctrl_smoke.3645390143
Short name	T620
Test name
Test status
Simulation time	58086900 ps
CPU time	121.89 seconds
Started	Jul 23 04:46:44 PM PDT 24
Finished	Jul 23 04:48:50 PM PDT 24
Peak memory	278040 kb
Host	smart-73b5ee9d-4e42-4b36-a266-9f182d0a72fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3645390143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.3645390143
Directory	/workspace/25.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.flash_ctrl_alert_test.403362547
Short name	T866
Test name
Test status
Simulation time	59495900 ps
CPU time	13.68 seconds
Started	Jul 23 04:46:44 PM PDT 24
Finished	Jul 23 04:47:01 PM PDT 24
Peak memory	265324 kb
Host	smart-f8162afc-e727-46b0-b2e9-f23a29aed1a9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403362547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.403362547
Directory	/workspace/26.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.flash_ctrl_connect.4015770255
Short name	T813
Test name
Test status
Simulation time	42344700 ps
CPU time	16.13 seconds
Started	Jul 23 04:46:45 PM PDT 24
Finished	Jul 23 04:47:07 PM PDT 24
Peak memory	274932 kb
Host	smart-2c0cf818-c923-4786-bc0a-ec8dcb149a94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4015770255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.4015770255
Directory	/workspace/26.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/26.flash_ctrl_disable.723779686
Short name	T738
Test name
Test status
Simulation time	14076400 ps
CPU time	22.4 seconds
Started	Jul 23 04:46:44 PM PDT 24
Finished	Jul 23 04:47:11 PM PDT 24
Peak memory	273624 kb
Host	smart-3fe533b0-2663-4510-b2dd-d52f10f83e35
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723779686 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_disable.723779686
Directory	/workspace/26.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/26.flash_ctrl_hw_sec_otp.516133296
Short name	T485
Test name
Test status
Simulation time	5242595000 ps
CPU time	115.96 seconds
Started	Jul 23 04:46:44 PM PDT 24
Finished	Jul 23 04:48:44 PM PDT 24
Peak memory	263268 kb
Host	smart-c47f8815-4ea9-4615-9769-c782ea7617df
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516133296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_h w_sec_otp.516133296
Directory	/workspace/26.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.4051879759
Short name	T863
Test name
Test status
Simulation time	16628613800 ps
CPU time	124.41 seconds
Started	Jul 23 04:46:44 PM PDT 24
Finished	Jul 23 04:48:52 PM PDT 24
Peak memory	293128 kb
Host	smart-423f08e0-9d6b-462f-86f7-04a2d6962c22
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051879759 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.4051879759
Directory	/workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/26.flash_ctrl_otp_reset.1985537247
Short name	T667
Test name
Test status
Simulation time	76629300 ps
CPU time	111.29 seconds
Started	Jul 23 04:46:43 PM PDT 24
Finished	Jul 23 04:48:38 PM PDT 24
Peak memory	260256 kb
Host	smart-915d113d-c883-4a8c-95ea-79c9ef33cea7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985537247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o tp_reset.1985537247
Directory	/workspace/26.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_prog_reset.1620033421
Short name	T399
Test name
Test status
Simulation time	27790000 ps
CPU time	13.71 seconds
Started	Jul 23 04:46:50 PM PDT 24
Finished	Jul 23 04:47:12 PM PDT 24
Peak memory	259500 kb
Host	smart-a5c02abb-8a23-4e16-94d9-7a2f16742ee6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620033421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.flash_ctrl_prog_reset.1620033421
Directory	/workspace/26.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_rw_evict.1253018441
Short name	T429
Test name
Test status
Simulation time	32420700 ps
CPU time	31.05 seconds
Started	Jul 23 04:46:50 PM PDT 24
Finished	Jul 23 04:47:29 PM PDT 24
Peak memory	273660 kb
Host	smart-116110ed-1384-4b34-a874-07895ec51098
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253018441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl ash_ctrl_rw_evict.1253018441
Directory	/workspace/26.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.1108327042
Short name	T928
Test name
Test status
Simulation time	68728800 ps
CPU time	31.79 seconds
Started	Jul 23 04:46:45 PM PDT 24
Finished	Jul 23 04:47:22 PM PDT 24
Peak memory	275652 kb
Host	smart-75b28737-6c27-450f-89c2-c5c2984baa13
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108327042 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.1108327042
Directory	/workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/26.flash_ctrl_sec_info_access.2917884788
Short name	T509
Test name
Test status
Simulation time	2853026900 ps
CPU time	71.56 seconds
Started	Jul 23 04:46:44 PM PDT 24
Finished	Jul 23 04:48:00 PM PDT 24
Peak memory	263708 kb
Host	smart-b883c9e9-f310-4f23-b9b9-6a9305af49b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2917884788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.2917884788
Directory	/workspace/26.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/26.flash_ctrl_smoke.2596510898
Short name	T584
Test name
Test status
Simulation time	152129500 ps
CPU time	96.67 seconds
Started	Jul 23 04:46:44 PM PDT 24
Finished	Jul 23 04:48:25 PM PDT 24
Peak memory	277396 kb
Host	smart-adbde42e-f6c2-4a1b-be4f-bbc5ed1478bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596510898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.2596510898
Directory	/workspace/26.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.flash_ctrl_alert_test.2575454714
Short name	T580
Test name
Test status
Simulation time	62621100 ps
CPU time	13.87 seconds
Started	Jul 23 04:46:51 PM PDT 24
Finished	Jul 23 04:47:13 PM PDT 24
Peak memory	265232 kb
Host	smart-beaf89c2-a4af-4898-8a2c-bca550bbf8da
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575454714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test. 2575454714
Directory	/workspace/27.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.flash_ctrl_connect.1155668593
Short name	T809
Test name
Test status
Simulation time	24675400 ps
CPU time	13.71 seconds
Started	Jul 23 04:46:51 PM PDT 24
Finished	Jul 23 04:47:12 PM PDT 24
Peak memory	284432 kb
Host	smart-5801f32e-8489-4794-a804-994a91c15fc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1155668593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.1155668593
Directory	/workspace/27.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/27.flash_ctrl_disable.3205237555
Short name	T996
Test name
Test status
Simulation time	12050100 ps
CPU time	21.79 seconds
Started	Jul 23 04:46:53 PM PDT 24
Finished	Jul 23 04:47:22 PM PDT 24
Peak memory	273516 kb
Host	smart-88e7fa90-9d06-4864-92e2-a15b3e72ddb1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205237555 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_disable.3205237555
Directory	/workspace/27.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/27.flash_ctrl_hw_sec_otp.661222532
Short name	T869
Test name
Test status
Simulation time	24351184500 ps
CPU time	163.83 seconds
Started	Jul 23 04:46:44 PM PDT 24
Finished	Jul 23 04:49:32 PM PDT 24
Peak memory	263388 kb
Host	smart-2266292b-73a1-4296-9545-d1febd6892f1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661222532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_h w_sec_otp.661222532
Directory	/workspace/27.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd.1630176432
Short name	T244
Test name
Test status
Simulation time	1241307500 ps
CPU time	125.24 seconds
Started	Jul 23 04:46:43 PM PDT 24
Finished	Jul 23 04:48:52 PM PDT 24
Peak memory	293992 kb
Host	smart-b63aed02-b390-46bd-a9d4-f87a050268c4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630176432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla sh_ctrl_intr_rd.1630176432
Directory	/workspace/27.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.630843740
Short name	T683
Test name
Test status
Simulation time	11971657000 ps
CPU time	255.91 seconds
Started	Jul 23 04:46:49 PM PDT 24
Finished	Jul 23 04:51:14 PM PDT 24
Peak memory	289892 kb
Host	smart-60f6c140-e639-4db0-867d-507300da3c50
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630843740 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.630843740
Directory	/workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/27.flash_ctrl_otp_reset.750542186
Short name	T403
Test name
Test status
Simulation time	36948000 ps
CPU time	132.29 seconds
Started	Jul 23 04:46:50 PM PDT 24
Finished	Jul 23 04:49:11 PM PDT 24
Peak memory	261096 kb
Host	smart-262b02d9-fec7-41bc-a3c7-ce28b72f04a1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750542186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_ot p_reset.750542186
Directory	/workspace/27.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/27.flash_ctrl_prog_reset.1816866443
Short name	T443
Test name
Test status
Simulation time	23503400 ps
CPU time	13.29 seconds
Started	Jul 23 04:46:44 PM PDT 24
Finished	Jul 23 04:47:02 PM PDT 24
Peak memory	265212 kb
Host	smart-03dd02fa-1ec3-48e5-9a2c-e40ab83edbbc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816866443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.flash_ctrl_prog_reset.1816866443
Directory	/workspace/27.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/27.flash_ctrl_rw_evict.740760977
Short name	T230
Test name
Test status
Simulation time	42416500 ps
CPU time	30.83 seconds
Started	Jul 23 04:46:49 PM PDT 24
Finished	Jul 23 04:47:27 PM PDT 24
Peak memory	268408 kb
Host	smart-249a42d7-f40f-49aa-b9ca-7374d3aa78a2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740760977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla sh_ctrl_rw_evict.740760977
Directory	/workspace/27.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.1956189522
Short name	T224
Test name
Test status
Simulation time	41820900 ps
CPU time	31.33 seconds
Started	Jul 23 04:46:52 PM PDT 24
Finished	Jul 23 04:47:32 PM PDT 24
Peak memory	275560 kb
Host	smart-79b5a2c6-8228-40fb-b8cc-55a1db1ee440
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956189522 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.1956189522
Directory	/workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/27.flash_ctrl_sec_info_access.2321443489
Short name	T818
Test name
Test status
Simulation time	6166164400 ps
CPU time	73.81 seconds
Started	Jul 23 04:46:56 PM PDT 24
Finished	Jul 23 04:48:17 PM PDT 24
Peak memory	263776 kb
Host	smart-dbb5af07-4b0f-4aea-a054-7f2ffe20f157
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2321443489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.2321443489
Directory	/workspace/27.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/27.flash_ctrl_smoke.1162139999
Short name	T625
Test name
Test status
Simulation time	31951300 ps
CPU time	167.59 seconds
Started	Jul 23 04:46:45 PM PDT 24
Finished	Jul 23 04:49:37 PM PDT 24
Peak memory	277056 kb
Host	smart-b759a435-fc3b-48e7-bd24-910877597d80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1162139999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.1162139999
Directory	/workspace/27.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.flash_ctrl_alert_test.3764564419
Short name	T740
Test name
Test status
Simulation time	37101500 ps
CPU time	13.76 seconds
Started	Jul 23 04:46:51 PM PDT 24
Finished	Jul 23 04:47:13 PM PDT 24
Peak memory	258164 kb
Host	smart-7baf30b1-14e1-4548-921a-fcabf324d786
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764564419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test. 3764564419
Directory	/workspace/28.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.flash_ctrl_connect.2671810330
Short name	T891
Test name
Test status
Simulation time	73653200 ps
CPU time	13.64 seconds
Started	Jul 23 04:46:52 PM PDT 24
Finished	Jul 23 04:47:13 PM PDT 24
Peak memory	284200 kb
Host	smart-60c4f05a-15af-4f49-a9a5-62573d222814
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2671810330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.2671810330
Directory	/workspace/28.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/28.flash_ctrl_disable.2897693474
Short name	T391
Test name
Test status
Simulation time	12562500 ps
CPU time	22.06 seconds
Started	Jul 23 04:46:54 PM PDT 24
Finished	Jul 23 04:47:24 PM PDT 24
Peak memory	273608 kb
Host	smart-843f4bc2-d51f-44c5-8f96-706edce5266e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897693474 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_disable.2897693474
Directory	/workspace/28.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/28.flash_ctrl_hw_sec_otp.285222849
Short name	T342
Test name
Test status
Simulation time	1934148500 ps
CPU time	68.89 seconds
Started	Jul 23 04:46:55 PM PDT 24
Finished	Jul 23 04:48:12 PM PDT 24
Peak memory	262752 kb
Host	smart-9851dc60-928e-4eeb-8e25-e6463e29d63a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285222849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_h w_sec_otp.285222849
Directory	/workspace/28.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd.2108360395
Short name	T1032
Test name
Test status
Simulation time	1356257700 ps
CPU time	139.13 seconds
Started	Jul 23 04:46:52 PM PDT 24
Finished	Jul 23 04:49:19 PM PDT 24
Peak memory	293996 kb
Host	smart-45082325-e764-4c1c-bf0a-ca9c031db0d7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108360395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla sh_ctrl_intr_rd.2108360395
Directory	/workspace/28.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/28.flash_ctrl_otp_reset.3506293616
Short name	T105
Test name
Test status
Simulation time	34707300 ps
CPU time	129.49 seconds
Started	Jul 23 04:46:56 PM PDT 24
Finished	Jul 23 04:49:13 PM PDT 24
Peak memory	259892 kb
Host	smart-888dc8db-9cfe-4b3b-b696-2fceb49d70f6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506293616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o tp_reset.3506293616
Directory	/workspace/28.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_prog_reset.1435816091
Short name	T713
Test name
Test status
Simulation time	27685300 ps
CPU time	13.71 seconds
Started	Jul 23 04:46:50 PM PDT 24
Finished	Jul 23 04:47:12 PM PDT 24
Peak memory	259416 kb
Host	smart-a3ebaa2b-73c4-4f41-8e2f-3e3d2b1ab461
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435816091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.flash_ctrl_prog_reset.1435816091
Directory	/workspace/28.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict.2404741089
Short name	T903
Test name
Test status
Simulation time	30843700 ps
CPU time	30.94 seconds
Started	Jul 23 04:46:54 PM PDT 24
Finished	Jul 23 04:47:32 PM PDT 24
Peak memory	268384 kb
Host	smart-14a2a91f-61e6-4ef1-8caa-bea55d4b693d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404741089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl ash_ctrl_rw_evict.2404741089
Directory	/workspace/28.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.3231827178
Short name	T791
Test name
Test status
Simulation time	90690300 ps
CPU time	30.82 seconds
Started	Jul 23 04:46:51 PM PDT 24
Finished	Jul 23 04:47:29 PM PDT 24
Peak memory	267484 kb
Host	smart-877e9717-4148-4093-af3a-35d8400d5113
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231827178 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.3231827178
Directory	/workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/28.flash_ctrl_sec_info_access.2543889551
Short name	T418
Test name
Test status
Simulation time	2073928500 ps
CPU time	63.15 seconds
Started	Jul 23 04:46:54 PM PDT 24
Finished	Jul 23 04:48:05 PM PDT 24
Peak memory	263140 kb
Host	smart-244e0b7d-b246-45e0-ac54-776ba4d64066
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2543889551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.2543889551
Directory	/workspace/28.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/28.flash_ctrl_smoke.328103363
Short name	T688
Test name
Test status
Simulation time	73313700 ps
CPU time	100.5 seconds
Started	Jul 23 04:46:51 PM PDT 24
Finished	Jul 23 04:48:39 PM PDT 24
Peak memory	276264 kb
Host	smart-30794fb9-d6da-479b-b59d-8f8f7faf27f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=328103363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.328103363
Directory	/workspace/28.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.flash_ctrl_alert_test.1036229905
Short name	T1083
Test name
Test status
Simulation time	33213400 ps
CPU time	13.58 seconds
Started	Jul 23 04:46:52 PM PDT 24
Finished	Jul 23 04:47:14 PM PDT 24
Peak memory	258224 kb
Host	smart-56f5d646-006f-4e60-91d4-0b7baa62c02f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036229905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test. 1036229905
Directory	/workspace/29.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.flash_ctrl_connect.3177572881
Short name	T980
Test name
Test status
Simulation time	23991000 ps
CPU time	16.06 seconds
Started	Jul 23 04:46:53 PM PDT 24
Finished	Jul 23 04:47:17 PM PDT 24
Peak memory	284272 kb
Host	smart-49b5971b-0bcf-433e-ab7e-2b776a6515c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3177572881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.3177572881
Directory	/workspace/29.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/29.flash_ctrl_disable.2249285064
Short name	T463
Test name
Test status
Simulation time	29905100 ps
CPU time	20.43 seconds
Started	Jul 23 04:46:51 PM PDT 24
Finished	Jul 23 04:47:19 PM PDT 24
Peak memory	265628 kb
Host	smart-b709a570-7053-43f0-b563-ba4bb924fa2d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249285064 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_disable.2249285064
Directory	/workspace/29.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/29.flash_ctrl_hw_sec_otp.2259087040
Short name	T521
Test name
Test status
Simulation time	13393548400 ps
CPU time	227.34 seconds
Started	Jul 23 04:46:52 PM PDT 24
Finished	Jul 23 04:50:48 PM PDT 24
Peak memory	262468 kb
Host	smart-f52fd3a4-50eb-41dc-8e4a-b88a86dc5d1c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259087040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_ hw_sec_otp.2259087040
Directory	/workspace/29.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/29.flash_ctrl_intr_rd.2076186747
Short name	T1049
Test name
Test status
Simulation time	1839043200 ps
CPU time	217.86 seconds
Started	Jul 23 04:46:53 PM PDT 24
Finished	Jul 23 04:50:39 PM PDT 24
Peak memory	290892 kb
Host	smart-f79a8522-54d9-4084-9fcc-641e594ad59a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076186747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla sh_ctrl_intr_rd.2076186747
Directory	/workspace/29.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.1390397913
Short name	T370
Test name
Test status
Simulation time	17518035500 ps
CPU time	195.48 seconds
Started	Jul 23 04:46:53 PM PDT 24
Finished	Jul 23 04:50:16 PM PDT 24
Peak memory	292876 kb
Host	smart-53fdc4fa-2058-411d-853d-773319597005
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390397913 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.1390397913
Directory	/workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/29.flash_ctrl_otp_reset.670142654
Short name	T522
Test name
Test status
Simulation time	80915400 ps
CPU time	133.46 seconds
Started	Jul 23 04:46:52 PM PDT 24
Finished	Jul 23 04:49:14 PM PDT 24
Peak memory	265416 kb
Host	smart-33547892-347f-49ed-8f01-d2562bb38d29
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670142654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_ot p_reset.670142654
Directory	/workspace/29.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_prog_reset.749870070
Short name	T690
Test name
Test status
Simulation time	87764900 ps
CPU time	13.54 seconds
Started	Jul 23 04:46:51 PM PDT 24
Finished	Jul 23 04:47:12 PM PDT 24
Peak memory	265272 kb
Host	smart-9b7d919a-bd57-402f-9db5-6c4ac3af96a0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749870070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.flash_ctrl_prog_reset.749870070
Directory	/workspace/29.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_rw_evict.2144342093
Short name	T23
Test name
Test status
Simulation time	29321700 ps
CPU time	28.4 seconds
Started	Jul 23 04:46:53 PM PDT 24
Finished	Jul 23 04:47:29 PM PDT 24
Peak memory	268432 kb
Host	smart-283fde44-0490-4f46-b67e-cb99daeec3d2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144342093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl ash_ctrl_rw_evict.2144342093
Directory	/workspace/29.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.1733764561
Short name	T155
Test name
Test status
Simulation time	70359200 ps
CPU time	28.59 seconds
Started	Jul 23 04:46:51 PM PDT 24
Finished	Jul 23 04:47:27 PM PDT 24
Peak memory	268440 kb
Host	smart-dea43c2d-9f6b-474d-b941-9a5319270dcc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733764561 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.1733764561
Directory	/workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/29.flash_ctrl_sec_info_access.2357614445
Short name	T268
Test name
Test status
Simulation time	4340178800 ps
CPU time	82.69 seconds
Started	Jul 23 04:46:53 PM PDT 24
Finished	Jul 23 04:48:23 PM PDT 24
Peak memory	263756 kb
Host	smart-da21059f-c66a-4ce8-85fe-4a7453706cba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2357614445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.2357614445
Directory	/workspace/29.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/29.flash_ctrl_smoke.2345674464
Short name	T525
Test name
Test status
Simulation time	63846200 ps
CPU time	172.02 seconds
Started	Jul 23 04:46:53 PM PDT 24
Finished	Jul 23 04:49:53 PM PDT 24
Peak memory	278604 kb
Host	smart-3aa2da2c-5cbe-4228-8ac3-3cf47eb24f37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2345674464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.2345674464
Directory	/workspace/29.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_alert_test.2459695072
Short name	T1034
Test name
Test status
Simulation time	268072800 ps
CPU time	14.33 seconds
Started	Jul 23 04:44:20 PM PDT 24
Finished	Jul 23 04:44:36 PM PDT 24
Peak memory	258372 kb
Host	smart-3c916ecb-c03f-4d98-a686-cd068d809640
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459695072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.2 459695072
Directory	/workspace/3.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.flash_ctrl_config_regwen.2528451834
Short name	T274
Test name
Test status
Simulation time	20781400 ps
CPU time	13.86 seconds
Started	Jul 23 04:44:25 PM PDT 24
Finished	Jul 23 04:44:44 PM PDT 24
Peak memory	264900 kb
Host	smart-e1298ef3-792b-467d-a17e-f691ae725e19
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528451834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .flash_ctrl_config_regwen.2528451834
Directory	/workspace/3.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/3.flash_ctrl_connect.284678875
Short name	T697
Test name
Test status
Simulation time	45526800 ps
CPU time	15.8 seconds
Started	Jul 23 04:44:28 PM PDT 24
Finished	Jul 23 04:44:48 PM PDT 24
Peak memory	274932 kb
Host	smart-26c2cd76-7094-49ee-83f4-3243210cf302
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=284678875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.284678875
Directory	/workspace/3.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/3.flash_ctrl_disable.4059804200
Short name	T389
Test name
Test status
Simulation time	29931100 ps
CPU time	21.75 seconds
Started	Jul 23 04:44:21 PM PDT 24
Finished	Jul 23 04:44:46 PM PDT 24
Peak memory	273588 kb
Host	smart-85b1ae9e-c796-40b2-b739-a973f2edaad6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059804200 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_disable.4059804200
Directory	/workspace/3.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/3.flash_ctrl_erase_suspend.3291118289
Short name	T1067
Test name
Test status
Simulation time	3071770900 ps
CPU time	404.75 seconds
Started	Jul 23 04:44:07 PM PDT 24
Finished	Jul 23 04:50:54 PM PDT 24
Peak memory	263408 kb
Host	smart-bfb8efea-7d05-4dd3-a454-90134c11359e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3291118289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.3291118289
Directory	/workspace/3.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_mp.793686377
Short name	T691
Test name
Test status
Simulation time	4482968500 ps
CPU time	2170.71 seconds
Started	Jul 23 04:44:24 PM PDT 24
Finished	Jul 23 05:20:38 PM PDT 24
Peak memory	264556 kb
Host	smart-7145b0ae-ce0e-411a-b8f8-50a55ecc4a35
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=793686377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.793686377
Directory	/workspace/3.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_win.1184542669
Short name	T320
Test name
Test status
Simulation time	553984900 ps
CPU time	987.4 seconds
Started	Jul 23 04:44:22 PM PDT 24
Finished	Jul 23 05:00:52 PM PDT 24
Peak memory	273324 kb
Host	smart-573fb435-2196-4e33-9aa6-bdf5aa039292
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184542669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.1184542669
Directory	/workspace/3.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fetch_code.56753916
Short name	T845
Test name
Test status
Simulation time	385818100 ps
CPU time	21.85 seconds
Started	Jul 23 04:44:28 PM PDT 24
Finished	Jul 23 04:44:54 PM PDT 24
Peak memory	263612 kb
Host	smart-30be33c6-2e40-4e9f-9aee-e716dd861250
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56753916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_fetch_code.56753916
Directory	/workspace/3.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fs_sup.2853782487
Short name	T901
Test name
Test status
Simulation time	340127600 ps
CPU time	40 seconds
Started	Jul 23 04:44:21 PM PDT 24
Finished	Jul 23 04:45:04 PM PDT 24
Peak memory	265352 kb
Host	smart-4d66d31d-07c2-462b-a313-3661512ee0c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853782487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 3.flash_ctrl_fs_sup.2853782487
Directory	/workspace/3.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/3.flash_ctrl_full_mem_access.2465939755
Short name	T144
Test name
Test status
Simulation time	50873412700 ps
CPU time	4152.23 seconds
Started	Jul 23 04:44:21 PM PDT 24
Finished	Jul 23 05:53:37 PM PDT 24
Peak memory	265120 kb
Host	smart-2e8e7c32-03d4-4be4-a9b2-61b739184541
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465939755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c trl_full_mem_access.2465939755
Directory	/workspace/3.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.2162398362
Short name	T111
Test name
Test status
Simulation time	548189363800 ps
CPU time	1954.36 seconds
Started	Jul 23 04:44:23 PM PDT 24
Finished	Jul 23 05:17:01 PM PDT 24
Peak memory	263888 kb
Host	smart-62942a41-8e6e-4667-aeab-56d122f2c7fd
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162398362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.flash_ctrl_host_ctrl_arb.2162398362
Directory	/workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_dir_rd.1414832384
Short name	T465
Test name
Test status
Simulation time	91124600 ps
CPU time	34.69 seconds
Started	Jul 23 04:44:15 PM PDT 24
Finished	Jul 23 04:44:52 PM PDT 24
Peak memory	262516 kb
Host	smart-f80ce6f1-8aea-4fdd-93cf-4bbbcb1018b8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1414832384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.1414832384
Directory	/workspace/3.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2103637113
Short name	T698
Test name
Test status
Simulation time	10047779100 ps
CPU time	48.7 seconds
Started	Jul 23 04:44:24 PM PDT 24
Finished	Jul 23 04:45:16 PM PDT 24
Peak memory	282336 kb
Host	smart-c0f91430-9b63-4ce7-b547-46b0beafb505
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103637113 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.2103637113
Directory	/workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.3468350280
Short name	T210
Test name
Test status
Simulation time	46680200 ps
CPU time	13.36 seconds
Started	Jul 23 04:44:20 PM PDT 24
Finished	Jul 23 04:44:35 PM PDT 24
Peak memory	258520 kb
Host	smart-2df76312-046e-48d4-ab5b-08cfc491b1c4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468350280 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.3468350280
Directory	/workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_rma_reset.4231147722
Short name	T199
Test name
Test status
Simulation time	270232424000 ps
CPU time	1041.86 seconds
Started	Jul 23 04:44:09 PM PDT 24
Finished	Jul 23 05:01:34 PM PDT 24
Peak memory	261056 kb
Host	smart-b93b3862-696a-4962-ad56-d9539b042efa
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231147722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 3.flash_ctrl_hw_rma_reset.4231147722
Directory	/workspace/3.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_sec_otp.2998940185
Short name	T484
Test name
Test status
Simulation time	19632049000 ps
CPU time	160.42 seconds
Started	Jul 23 04:44:13 PM PDT 24
Finished	Jul 23 04:46:57 PM PDT 24
Peak memory	262784 kb
Host	smart-2dab9756-f947-4261-93d0-2cd0bf9cafc5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998940185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h w_sec_otp.2998940185
Directory	/workspace/3.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd.3057969616
Short name	T358
Test name
Test status
Simulation time	1001941900 ps
CPU time	175.84 seconds
Started	Jul 23 04:44:22 PM PDT 24
Finished	Jul 23 04:47:20 PM PDT 24
Peak memory	294096 kb
Host	smart-8b0cccf7-d414-4557-8ab3-40edb7c9a578
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057969616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_intr_rd.3057969616
Directory	/workspace/3.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.3555052065
Short name	T355
Test name
Test status
Simulation time	24995675800 ps
CPU time	462.78 seconds
Started	Jul 23 04:44:27 PM PDT 24
Finished	Jul 23 04:52:15 PM PDT 24
Peak memory	285028 kb
Host	smart-ff9c0591-ecec-4451-b67a-e4718b3b9f0f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555052065 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.3555052065
Directory	/workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr.1248954630
Short name	T1092
Test name
Test status
Simulation time	2176357300 ps
CPU time	62.26 seconds
Started	Jul 23 04:44:24 PM PDT 24
Finished	Jul 23 04:45:30 PM PDT 24
Peak memory	260632 kb
Host	smart-ec8308fa-5fe1-4fc4-843f-23bdd6160afb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248954630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.flash_ctrl_intr_wr.1248954630
Directory	/workspace/3.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.2100467240
Short name	T710
Test name
Test status
Simulation time	36189666600 ps
CPU time	190.03 seconds
Started	Jul 23 04:44:23 PM PDT 24
Finished	Jul 23 04:47:37 PM PDT 24
Peak memory	260424 kb
Host	smart-4389fab1-44bf-45b1-b197-83ff6f1f05b3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210 0467240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.2100467240
Directory	/workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_lcmgr_intg.1480110693
Short name	T507
Test name
Test status
Simulation time	15478700 ps
CPU time	13.48 seconds
Started	Jul 23 04:44:23 PM PDT 24
Finished	Jul 23 04:44:41 PM PDT 24
Peak memory	264908 kb
Host	smart-e998347d-d03d-4695-a976-edd53c7d84b6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480110693 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.1480110693
Directory	/workspace/3.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mid_op_rst.375514691
Short name	T81
Test name
Test status
Simulation time	2569683600 ps
CPU time	71.85 seconds
Started	Jul 23 04:44:27 PM PDT 24
Finished	Jul 23 04:45:44 PM PDT 24
Peak memory	260496 kb
Host	smart-080f04c4-a2dd-4581-8893-739c7d7b54b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375514691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.375514691
Directory	/workspace/3.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mp_regions.3039137398
Short name	T695
Test name
Test status
Simulation time	5371568400 ps
CPU time	196.15 seconds
Started	Jul 23 04:44:23 PM PDT 24
Finished	Jul 23 04:47:42 PM PDT 24
Peak memory	265284 kb
Host	smart-fba741be-c1cc-4b2b-9ce1-bda7e60608e3
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039137398 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.3039137398
Directory	/workspace/3.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/3.flash_ctrl_otp_reset.2520410562
Short name	T801
Test name
Test status
Simulation time	501950900 ps
CPU time	130.62 seconds
Started	Jul 23 04:44:25 PM PDT 24
Finished	Jul 23 04:46:40 PM PDT 24
Peak memory	260268 kb
Host	smart-bbcba7fe-56ff-4cb7-a387-6bea40d11d2f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520410562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot p_reset.2520410562
Directory	/workspace/3.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_oversize_error.2441968849
Short name	T1104
Test name
Test status
Simulation time	2367377800 ps
CPU time	158.86 seconds
Started	Jul 23 04:44:25 PM PDT 24
Finished	Jul 23 04:47:08 PM PDT 24
Peak memory	289956 kb
Host	smart-468c1e30-c0bb-4236-9d3d-878a539e322e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441968849 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.2441968849
Directory	/workspace/3.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.2302189736
Short name	T50
Test name
Test status
Simulation time	48658500 ps
CPU time	13.99 seconds
Started	Jul 23 04:44:26 PM PDT 24
Finished	Jul 23 04:44:44 PM PDT 24
Peak memory	277044 kb
Host	smart-2f21e15d-14a7-429f-a0c5-e74f7e4e2164
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2302189736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.2302189736
Directory	/workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb.3578881829
Short name	T66
Test name
Test status
Simulation time	1438980500 ps
CPU time	533.19 seconds
Started	Jul 23 04:44:08 PM PDT 24
Finished	Jul 23 04:53:04 PM PDT 24
Peak memory	263224 kb
Host	smart-1a8a71f3-decc-4cf4-bb6e-9ca1b157ea67
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3578881829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.3578881829
Directory	/workspace/3.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb_redun.1014497462
Short name	T73
Test name
Test status
Simulation time	857233800 ps
CPU time	18.85 seconds
Started	Jul 23 04:44:23 PM PDT 24
Finished	Jul 23 04:44:45 PM PDT 24
Peak memory	264116 kb
Host	smart-26c337d3-4d47-416f-9de9-1ab83b51a915
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014497462 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.1014497462
Directory	/workspace/3.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/3.flash_ctrl_prog_reset.500288663
Short name	T606
Test name
Test status
Simulation time	2285112900 ps
CPU time	172.26 seconds
Started	Jul 23 04:44:21 PM PDT 24
Finished	Jul 23 04:47:15 PM PDT 24
Peak memory	260608 kb
Host	smart-0b4dad81-9b02-475e-89ae-ce20012ccca5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500288663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.flash_ctrl_prog_reset.500288663
Directory	/workspace/3.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rand_ops.3117012089
Short name	T147
Test name
Test status
Simulation time	1478534700 ps
CPU time	754.13 seconds
Started	Jul 23 04:44:11 PM PDT 24
Finished	Jul 23 04:56:49 PM PDT 24
Peak memory	284928 kb
Host	smart-ea79d401-a1c5-4577-bf05-9d497f16a287
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3117012089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.3117012089
Directory	/workspace/3.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rd_buff_evict.1681875621
Short name	T302
Test name
Test status
Simulation time	1406713100 ps
CPU time	151.53 seconds
Started	Jul 23 04:44:08 PM PDT 24
Finished	Jul 23 04:46:41 PM PDT 24
Peak memory	262744 kb
Host	smart-53e1fc9e-7faa-40dc-84d8-d401372f3124
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1681875621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.1681875621
Directory	/workspace/3.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.3125197275
Short name	T708
Test name
Test status
Simulation time	19437800 ps
CPU time	22.65 seconds
Started	Jul 23 04:44:20 PM PDT 24
Finished	Jul 23 04:44:44 PM PDT 24
Peak memory	265320 kb
Host	smart-929770a4-4be9-4f66-ba81-2423d003b260
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125197275 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.3125197275
Directory	/workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.696470786
Short name	T650
Test name
Test status
Simulation time	23583100 ps
CPU time	22.9 seconds
Started	Jul 23 04:44:22 PM PDT 24
Finished	Jul 23 04:44:48 PM PDT 24
Peak memory	265068 kb
Host	smart-056e50a2-deaa-44d4-a460-88ae6b0135ea
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696470786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_read_word_sweep_serr.696470786
Directory	/workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro.1051431407
Short name	T817
Test name
Test status
Simulation time	625845900 ps
CPU time	128.7 seconds
Started	Jul 23 04:44:23 PM PDT 24
Finished	Jul 23 04:46:35 PM PDT 24
Peak memory	289996 kb
Host	smart-a95b8784-1755-4470-ac44-1a71bdac0a3d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051431407 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_ro.1051431407
Directory	/workspace/3.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_derr.3494985612
Short name	T216
Test name
Test status
Simulation time	1893749700 ps
CPU time	135.61 seconds
Started	Jul 23 04:44:22 PM PDT 24
Finished	Jul 23 04:46:40 PM PDT 24
Peak memory	281812 kb
Host	smart-8f09ae52-16d4-4468-9400-ec54c07fdf7b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3494985612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.3494985612
Directory	/workspace/3.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_serr.2847297970
Short name	T892
Test name
Test status
Simulation time	12109832000 ps
CPU time	160.64 seconds
Started	Jul 23 04:44:21 PM PDT 24
Finished	Jul 23 04:47:03 PM PDT 24
Peak memory	281728 kb
Host	smart-8cfd31cd-4221-43ce-b126-60826a49427e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847297970 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.2847297970
Directory	/workspace/3.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw.1425098303
Short name	T764
Test name
Test status
Simulation time	13469565700 ps
CPU time	554.96 seconds
Started	Jul 23 04:44:24 PM PDT 24
Finished	Jul 23 04:53:43 PM PDT 24
Peak memory	309740 kb
Host	smart-55508995-f5d5-47b3-8a25-de0e239f01bf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425098303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.flash_ctrl_rw.1425098303
Directory	/workspace/3.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.3915146120
Short name	T162
Test name
Test status
Simulation time	72348900 ps
CPU time	31.46 seconds
Started	Jul 23 04:44:27 PM PDT 24
Finished	Jul 23 04:45:03 PM PDT 24
Peak memory	275624 kb
Host	smart-bfd9fe6f-4b2c-4fdc-a4e4-50a7d94ac592
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915146120 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.3915146120
Directory	/workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_info_access.1633596795
Short name	T760
Test name
Test status
Simulation time	3111446700 ps
CPU time	69.43 seconds
Started	Jul 23 04:44:27 PM PDT 24
Finished	Jul 23 04:45:41 PM PDT 24
Peak memory	263896 kb
Host	smart-db00509a-424e-4c7f-b9e5-b441ae099aa2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633596795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1633596795
Directory	/workspace/3.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_address.4018938143
Short name	T576
Test name
Test status
Simulation time	1210177200 ps
CPU time	63.69 seconds
Started	Jul 23 04:44:22 PM PDT 24
Finished	Jul 23 04:45:29 PM PDT 24
Peak memory	273524 kb
Host	smart-eba45f68-5af6-4898-ace4-7962756ad5c8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018938143 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_serr_address.4018938143
Directory	/workspace/3.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_counter.2859405865
Short name	T52
Test name
Test status
Simulation time	921273300 ps
CPU time	61.17 seconds
Started	Jul 23 04:44:19 PM PDT 24
Finished	Jul 23 04:45:21 PM PDT 24
Peak memory	274140 kb
Host	smart-49d7fc41-63b8-4e9c-88ec-f4e4aa76f62b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859405865 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 3.flash_ctrl_serr_counter.2859405865
Directory	/workspace/3.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke.3196736061
Short name	T882
Test name
Test status
Simulation time	50255400 ps
CPU time	99.65 seconds
Started	Jul 23 04:44:09 PM PDT 24
Finished	Jul 23 04:45:51 PM PDT 24
Peak memory	276348 kb
Host	smart-7868180b-6b3a-473a-8fd4-d4f4ac2cca7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196736061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.3196736061
Directory	/workspace/3.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke_hw.379890565
Short name	T55
Test name
Test status
Simulation time	16915700 ps
CPU time	24.28 seconds
Started	Jul 23 04:44:11 PM PDT 24
Finished	Jul 23 04:44:39 PM PDT 24
Peak memory	259632 kb
Host	smart-2770e58d-2c40-45b1-ba1a-b8dc04833246
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=379890565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.379890565
Directory	/workspace/3.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_stress_all.163752425
Short name	T931
Test name
Test status
Simulation time	195865400 ps
CPU time	700.8 seconds
Started	Jul 23 04:44:25 PM PDT 24
Finished	Jul 23 04:56:10 PM PDT 24
Peak memory	282236 kb
Host	smart-cb4dc16a-ddd9-40a5-84a3-a5af9e3dbf75
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163752425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress _all.163752425
Directory	/workspace/3.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sw_op.327004397
Short name	T585
Test name
Test status
Simulation time	107636700 ps
CPU time	27.16 seconds
Started	Jul 23 04:44:14 PM PDT 24
Finished	Jul 23 04:44:44 PM PDT 24
Peak memory	259672 kb
Host	smart-20c48f8e-4a0e-4d72-b210-c6bc94aea097
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=327004397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.327004397
Directory	/workspace/3.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/3.flash_ctrl_wo.1206811657
Short name	T397
Test name
Test status
Simulation time	4256531200 ps
CPU time	180.8 seconds
Started	Jul 23 04:44:27 PM PDT 24
Finished	Jul 23 04:47:33 PM PDT 24
Peak memory	259944 kb
Host	smart-f2027fae-0ce6-4be3-84c2-152f3e0f6e1b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206811657 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.flash_ctrl_wo.1206811657
Directory	/workspace/3.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/30.flash_ctrl_connect.3918038422
Short name	T446
Test name
Test status
Simulation time	16227100 ps
CPU time	16.34 seconds
Started	Jul 23 04:46:58 PM PDT 24
Finished	Jul 23 04:47:21 PM PDT 24
Peak memory	274716 kb
Host	smart-aa6b044f-5fc8-4f6a-9e04-d559c24f35d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3918038422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.3918038422
Directory	/workspace/30.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/30.flash_ctrl_disable.373883897
Short name	T947
Test name
Test status
Simulation time	20568800 ps
CPU time	20.97 seconds
Started	Jul 23 04:46:58 PM PDT 24
Finished	Jul 23 04:47:25 PM PDT 24
Peak memory	265648 kb
Host	smart-a6e4b864-d322-4b04-b4cc-c5528442ca5e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373883897 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_disable.373883897
Directory	/workspace/30.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/30.flash_ctrl_hw_sec_otp.3031694783
Short name	T786
Test name
Test status
Simulation time	499500400 ps
CPU time	47.38 seconds
Started	Jul 23 04:47:00 PM PDT 24
Finished	Jul 23 04:47:53 PM PDT 24
Peak memory	260984 kb
Host	smart-0b5ca684-7681-4c3f-af8c-cabd9c336ae6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031694783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_ hw_sec_otp.3031694783
Directory	/workspace/30.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd.1924537621
Short name	T32
Test name
Test status
Simulation time	1131685000 ps
CPU time	138.04 seconds
Started	Jul 23 04:47:00 PM PDT 24
Finished	Jul 23 04:49:23 PM PDT 24
Peak memory	285360 kb
Host	smart-675e3569-e4c3-4af3-ba49-5c0cb03efed3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924537621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla sh_ctrl_intr_rd.1924537621
Directory	/workspace/30.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.805984939
Short name	T88
Test name
Test status
Simulation time	12462286500 ps
CPU time	462.21 seconds
Started	Jul 23 04:46:59 PM PDT 24
Finished	Jul 23 04:54:47 PM PDT 24
Peak memory	293012 kb
Host	smart-24bec959-98ae-4532-a374-c2a7013c795c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805984939 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.805984939
Directory	/workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/30.flash_ctrl_otp_reset.3501921376
Short name	T731
Test name
Test status
Simulation time	66788400 ps
CPU time	109.29 seconds
Started	Jul 23 04:46:59 PM PDT 24
Finished	Jul 23 04:48:54 PM PDT 24
Peak memory	261060 kb
Host	smart-41d7ce11-9c3b-4514-ad2b-8a815a83ef8a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501921376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o tp_reset.3501921376
Directory	/workspace/30.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/30.flash_ctrl_rw_evict.2060894639
Short name	T952
Test name
Test status
Simulation time	45809800 ps
CPU time	30.56 seconds
Started	Jul 23 04:47:05 PM PDT 24
Finished	Jul 23 04:47:37 PM PDT 24
Peak memory	268512 kb
Host	smart-af529378-8e46-4886-952f-21add52c5fc5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060894639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl ash_ctrl_rw_evict.2060894639
Directory	/workspace/30.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.2309296472
Short name	T434
Test name
Test status
Simulation time	67458900 ps
CPU time	30.48 seconds
Started	Jul 23 04:46:58 PM PDT 24
Finished	Jul 23 04:47:35 PM PDT 24
Peak memory	275676 kb
Host	smart-14b86ec9-ae36-4fb2-8bd7-24835cc5b6fe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309296472 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.2309296472
Directory	/workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/30.flash_ctrl_sec_info_access.322751602
Short name	T1113
Test name
Test status
Simulation time	457900600 ps
CPU time	54.66 seconds
Started	Jul 23 04:46:59 PM PDT 24
Finished	Jul 23 04:47:59 PM PDT 24
Peak memory	264108 kb
Host	smart-ea4f4efa-920e-4889-9cfc-9ab03a60583e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=322751602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.322751602
Directory	/workspace/30.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/30.flash_ctrl_smoke.1030357459
Short name	T798
Test name
Test status
Simulation time	187704900 ps
CPU time	52.56 seconds
Started	Jul 23 04:46:59 PM PDT 24
Finished	Jul 23 04:47:57 PM PDT 24
Peak memory	271280 kb
Host	smart-bd92a2a6-bb55-4323-b403-4c1b1d8c40bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1030357459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.1030357459
Directory	/workspace/30.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.flash_ctrl_alert_test.1841444262
Short name	T994
Test name
Test status
Simulation time	51333400 ps
CPU time	13.71 seconds
Started	Jul 23 04:46:59 PM PDT 24
Finished	Jul 23 04:47:19 PM PDT 24
Peak memory	265216 kb
Host	smart-2e70100c-2c1a-4552-bbd5-40563adc4397
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841444262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test. 1841444262
Directory	/workspace/31.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.flash_ctrl_connect.248261045
Short name	T954
Test name
Test status
Simulation time	28202600 ps
CPU time	16.01 seconds
Started	Jul 23 04:47:02 PM PDT 24
Finished	Jul 23 04:47:22 PM PDT 24
Peak memory	284456 kb
Host	smart-28bb654b-8208-41cb-8a22-c1030bacf212
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=248261045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.248261045
Directory	/workspace/31.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3344413184
Short name	T575
Test name
Test status
Simulation time	2113892800 ps
CPU time	67.81 seconds
Started	Jul 23 04:47:00 PM PDT 24
Finished	Jul 23 04:48:13 PM PDT 24
Peak memory	263256 kb
Host	smart-614d8bf7-1568-483e-a1ff-21fc769c6f6e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344413184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_ hw_sec_otp.3344413184
Directory	/workspace/31.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd.4165572280
Short name	T361
Test name
Test status
Simulation time	5568054000 ps
CPU time	211.05 seconds
Started	Jul 23 04:47:00 PM PDT 24
Finished	Jul 23 04:50:36 PM PDT 24
Peak memory	285036 kb
Host	smart-d60b280a-89ba-457e-b676-f2156cefe2b3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165572280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla sh_ctrl_intr_rd.4165572280
Directory	/workspace/31.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.4188939153
Short name	T33
Test name
Test status
Simulation time	80940586900 ps
CPU time	281.46 seconds
Started	Jul 23 04:47:02 PM PDT 24
Finished	Jul 23 04:51:48 PM PDT 24
Peak memory	289896 kb
Host	smart-f82eda8c-1cdf-46ca-932d-698b671a4146
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188939153 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.4188939153
Directory	/workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/31.flash_ctrl_otp_reset.579380026
Short name	T782
Test name
Test status
Simulation time	124693600 ps
CPU time	131.72 seconds
Started	Jul 23 04:47:01 PM PDT 24
Finished	Jul 23 04:49:18 PM PDT 24
Peak memory	260200 kb
Host	smart-7c77d2f1-e79e-4576-a144-a90586aa7f98
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579380026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_ot p_reset.579380026
Directory	/workspace/31.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/31.flash_ctrl_rw_evict.3266327319
Short name	T306
Test name
Test status
Simulation time	56730900 ps
CPU time	30.4 seconds
Started	Jul 23 04:47:06 PM PDT 24
Finished	Jul 23 04:47:38 PM PDT 24
Peak memory	268504 kb
Host	smart-cf358cc3-014f-4cda-975d-d04e16f4da2c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266327319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl ash_ctrl_rw_evict.3266327319
Directory	/workspace/31.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.1324476059
Short name	T930
Test name
Test status
Simulation time	27345500 ps
CPU time	31.15 seconds
Started	Jul 23 04:47:02 PM PDT 24
Finished	Jul 23 04:47:37 PM PDT 24
Peak memory	268404 kb
Host	smart-8fae881b-1274-4a29-b0bf-8f2f8e296ac6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324476059 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.1324476059
Directory	/workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/31.flash_ctrl_sec_info_access.275897089
Short name	T617
Test name
Test status
Simulation time	1325585900 ps
CPU time	59.17 seconds
Started	Jul 23 04:47:00 PM PDT 24
Finished	Jul 23 04:48:05 PM PDT 24
Peak memory	263628 kb
Host	smart-00c8e489-bb4e-4fe0-8e9d-5f8ed545614c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=275897089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.275897089
Directory	/workspace/31.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/31.flash_ctrl_smoke.4080804322
Short name	T632
Test name
Test status
Simulation time	102375200 ps
CPU time	122.12 seconds
Started	Jul 23 04:47:04 PM PDT 24
Finished	Jul 23 04:49:09 PM PDT 24
Peak memory	276328 kb
Host	smart-a0975a4e-49f5-40b2-a38a-ee7791d188fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4080804322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.4080804322
Directory	/workspace/31.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.flash_ctrl_alert_test.2280533311
Short name	T1013
Test name
Test status
Simulation time	26444200 ps
CPU time	13.48 seconds
Started	Jul 23 04:47:07 PM PDT 24
Finished	Jul 23 04:47:23 PM PDT 24
Peak memory	265168 kb
Host	smart-2c0a067e-d7c8-47e9-8ec5-2a5acc6a116c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280533311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test. 2280533311
Directory	/workspace/32.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.flash_ctrl_connect.3462620118
Short name	T686
Test name
Test status
Simulation time	53431100 ps
CPU time	15.79 seconds
Started	Jul 23 04:47:07 PM PDT 24
Finished	Jul 23 04:47:26 PM PDT 24
Peak memory	275032 kb
Host	smart-abfde8a5-6a6e-43f7-aaec-940118acb1b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462620118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.3462620118
Directory	/workspace/32.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/32.flash_ctrl_disable.4272805986
Short name	T811
Test name
Test status
Simulation time	15674700 ps
CPU time	20.21 seconds
Started	Jul 23 04:47:11 PM PDT 24
Finished	Jul 23 04:47:33 PM PDT 24
Peak memory	273616 kb
Host	smart-52ed1635-b438-47ca-867e-06ed7eba5a2a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272805986 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_disable.4272805986
Directory	/workspace/32.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/32.flash_ctrl_hw_sec_otp.742319008
Short name	T518
Test name
Test status
Simulation time	15257750500 ps
CPU time	84.82 seconds
Started	Jul 23 04:46:59 PM PDT 24
Finished	Jul 23 04:48:30 PM PDT 24
Peak memory	260808 kb
Host	smart-e42ea768-f39b-4900-a114-7e64402b4260
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742319008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_h w_sec_otp.742319008
Directory	/workspace/32.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd.1858436618
Short name	T652
Test name
Test status
Simulation time	6482141200 ps
CPU time	216.78 seconds
Started	Jul 23 04:47:01 PM PDT 24
Finished	Jul 23 04:50:42 PM PDT 24
Peak memory	284832 kb
Host	smart-3b9e93a1-910b-4ec9-afd5-3ba58da6254a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858436618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla sh_ctrl_intr_rd.1858436618
Directory	/workspace/32.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.2769735075
Short name	T364
Test name
Test status
Simulation time	26034527600 ps
CPU time	294.26 seconds
Started	Jul 23 04:47:11 PM PDT 24
Finished	Jul 23 04:52:06 PM PDT 24
Peak memory	292084 kb
Host	smart-185ac826-0ce4-47ff-acb6-95f3a62dc726
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769735075 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.2769735075
Directory	/workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/32.flash_ctrl_otp_reset.3187005384
Short name	T489
Test name
Test status
Simulation time	36840200 ps
CPU time	131.86 seconds
Started	Jul 23 04:47:00 PM PDT 24
Finished	Jul 23 04:49:17 PM PDT 24
Peak memory	260196 kb
Host	smart-b493b25e-6955-4e3f-a033-4c23eddea957
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187005384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o tp_reset.3187005384
Directory	/workspace/32.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/32.flash_ctrl_rw_evict.1261023855
Short name	T266
Test name
Test status
Simulation time	169720300 ps
CPU time	31.47 seconds
Started	Jul 23 04:47:08 PM PDT 24
Finished	Jul 23 04:47:41 PM PDT 24
Peak memory	268420 kb
Host	smart-4f6e0eb6-1672-43e1-874f-057973589f5e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261023855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl ash_ctrl_rw_evict.1261023855
Directory	/workspace/32.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.3800346968
Short name	T438
Test name
Test status
Simulation time	61039300 ps
CPU time	31.08 seconds
Started	Jul 23 04:47:07 PM PDT 24
Finished	Jul 23 04:47:40 PM PDT 24
Peak memory	267492 kb
Host	smart-777b84aa-277b-49bc-a7e6-a2e51aaca5d4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800346968 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.3800346968
Directory	/workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/32.flash_ctrl_sec_info_access.414603424
Short name	T779
Test name
Test status
Simulation time	2899480300 ps
CPU time	68.69 seconds
Started	Jul 23 04:47:11 PM PDT 24
Finished	Jul 23 04:48:21 PM PDT 24
Peak memory	263756 kb
Host	smart-36308137-f031-4d36-ad87-0b561f839783
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=414603424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.414603424
Directory	/workspace/32.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/32.flash_ctrl_smoke.282388640
Short name	T999
Test name
Test status
Simulation time	115594400 ps
CPU time	99.75 seconds
Started	Jul 23 04:47:00 PM PDT 24
Finished	Jul 23 04:48:45 PM PDT 24
Peak memory	268760 kb
Host	smart-d175a25a-04ac-4854-a1d5-51eac273720d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=282388640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.282388640
Directory	/workspace/32.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.flash_ctrl_alert_test.306258278
Short name	T979
Test name
Test status
Simulation time	40145900 ps
CPU time	13.53 seconds
Started	Jul 23 04:47:19 PM PDT 24
Finished	Jul 23 04:47:34 PM PDT 24
Peak memory	258444 kb
Host	smart-263ecbd4-3387-41ac-8e5f-20ce31a0925c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306258278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.306258278
Directory	/workspace/33.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.flash_ctrl_connect.2309518182
Short name	T663
Test name
Test status
Simulation time	12842300 ps
CPU time	13.32 seconds
Started	Jul 23 04:47:16 PM PDT 24
Finished	Jul 23 04:47:31 PM PDT 24
Peak memory	284356 kb
Host	smart-0e7a2ecf-d9e5-4cb2-b0b9-0a51990648ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2309518182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.2309518182
Directory	/workspace/33.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/33.flash_ctrl_disable.3299952067
Short name	T390
Test name
Test status
Simulation time	21106000 ps
CPU time	22.04 seconds
Started	Jul 23 04:47:09 PM PDT 24
Finished	Jul 23 04:47:33 PM PDT 24
Peak memory	273520 kb
Host	smart-26fb6541-4117-4f5f-8cdf-6f6774902ae4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299952067 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_disable.3299952067
Directory	/workspace/33.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/33.flash_ctrl_hw_sec_otp.1009700529
Short name	T166
Test name
Test status
Simulation time	3211721700 ps
CPU time	141.71 seconds
Started	Jul 23 04:47:11 PM PDT 24
Finished	Jul 23 04:49:34 PM PDT 24
Peak memory	261044 kb
Host	smart-c647bf0a-6b07-4586-931a-21911a1673ed
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009700529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_ hw_sec_otp.1009700529
Directory	/workspace/33.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd.1355401253
Short name	T1106
Test name
Test status
Simulation time	20098146600 ps
CPU time	222.24 seconds
Started	Jul 23 04:47:09 PM PDT 24
Finished	Jul 23 04:50:53 PM PDT 24
Peak memory	284796 kb
Host	smart-241d5d4d-6da0-4ac7-bf1c-c136c120a3f3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355401253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla sh_ctrl_intr_rd.1355401253
Directory	/workspace/33.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.3237714870
Short name	T870
Test name
Test status
Simulation time	25991140300 ps
CPU time	414.71 seconds
Started	Jul 23 04:47:06 PM PDT 24
Finished	Jul 23 04:54:03 PM PDT 24
Peak memory	291932 kb
Host	smart-0bf02869-e154-4b87-b50e-ac4fc284c7b3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237714870 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.3237714870
Directory	/workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/33.flash_ctrl_otp_reset.3713476889
Short name	T885
Test name
Test status
Simulation time	43007500 ps
CPU time	110.62 seconds
Started	Jul 23 04:47:08 PM PDT 24
Finished	Jul 23 04:49:00 PM PDT 24
Peak memory	263472 kb
Host	smart-e2b300a3-13f3-4a84-8f02-7218730edcb3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713476889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o tp_reset.3713476889
Directory	/workspace/33.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/33.flash_ctrl_rw_evict.2708882999
Short name	T719
Test name
Test status
Simulation time	26596500 ps
CPU time	30.67 seconds
Started	Jul 23 04:47:07 PM PDT 24
Finished	Jul 23 04:47:40 PM PDT 24
Peak memory	273536 kb
Host	smart-09ccf203-af65-4128-9efb-00846f7f1c73
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708882999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl ash_ctrl_rw_evict.2708882999
Directory	/workspace/33.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.1049149912
Short name	T922
Test name
Test status
Simulation time	29182800 ps
CPU time	30.66 seconds
Started	Jul 23 04:47:07 PM PDT 24
Finished	Jul 23 04:47:40 PM PDT 24
Peak memory	268424 kb
Host	smart-55f284d5-f53d-4b93-a7af-6b50a16fe589
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049149912 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.1049149912
Directory	/workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/33.flash_ctrl_sec_info_access.4175998346
Short name	T15
Test name
Test status
Simulation time	723176200 ps
CPU time	54.24 seconds
Started	Jul 23 04:47:10 PM PDT 24
Finished	Jul 23 04:48:05 PM PDT 24
Peak memory	265096 kb
Host	smart-5b3aba26-5993-422b-a673-a6d4ac627082
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175998346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.4175998346
Directory	/workspace/33.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/33.flash_ctrl_smoke.4233874250
Short name	T568
Test name
Test status
Simulation time	1563686700 ps
CPU time	78.71 seconds
Started	Jul 23 04:47:07 PM PDT 24
Finished	Jul 23 04:48:28 PM PDT 24
Peak memory	280736 kb
Host	smart-39a85ccf-8f3b-4108-a128-5d23489638a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4233874250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.4233874250
Directory	/workspace/33.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.flash_ctrl_alert_test.4261307782
Short name	T524
Test name
Test status
Simulation time	61267300 ps
CPU time	13.6 seconds
Started	Jul 23 04:47:19 PM PDT 24
Finished	Jul 23 04:47:34 PM PDT 24
Peak memory	258288 kb
Host	smart-8b11e75b-6444-46cd-813a-354a254cce1e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261307782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test. 4261307782
Directory	/workspace/34.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.flash_ctrl_connect.143197026
Short name	T113
Test name
Test status
Simulation time	26400300 ps
CPU time	13.97 seconds
Started	Jul 23 04:47:15 PM PDT 24
Finished	Jul 23 04:47:30 PM PDT 24
Peak memory	274940 kb
Host	smart-1f32ae8e-3cf3-4026-a8b6-3207971d1726
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=143197026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.143197026
Directory	/workspace/34.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/34.flash_ctrl_disable.258708568
Short name	T194
Test name
Test status
Simulation time	41851800 ps
CPU time	21.88 seconds
Started	Jul 23 04:47:16 PM PDT 24
Finished	Jul 23 04:47:39 PM PDT 24
Peak memory	273456 kb
Host	smart-c411b7c1-d34b-407e-ae53-cc56f1d20e32
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258708568 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_disable.258708568
Directory	/workspace/34.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/34.flash_ctrl_hw_sec_otp.936607404
Short name	T995
Test name
Test status
Simulation time	10677349300 ps
CPU time	83.23 seconds
Started	Jul 23 04:47:16 PM PDT 24
Finished	Jul 23 04:48:41 PM PDT 24
Peak memory	262816 kb
Host	smart-a4869f2d-bb6b-4b75-ab0b-7864f90ef821
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936607404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_h w_sec_otp.936607404
Directory	/workspace/34.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd.2174291721
Short name	T1117
Test name
Test status
Simulation time	2353203700 ps
CPU time	251.23 seconds
Started	Jul 23 04:47:18 PM PDT 24
Finished	Jul 23 04:51:31 PM PDT 24
Peak memory	284728 kb
Host	smart-f964f5e5-2f38-4cb2-b40d-793cb3baa7f0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174291721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla sh_ctrl_intr_rd.2174291721
Directory	/workspace/34.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3489498242
Short name	T340
Test name
Test status
Simulation time	49418890400 ps
CPU time	273.87 seconds
Started	Jul 23 04:47:19 PM PDT 24
Finished	Jul 23 04:51:55 PM PDT 24
Peak memory	291132 kb
Host	smart-27306d7d-c5f9-43ef-babf-810fc4437e65
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489498242 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.3489498242
Directory	/workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/34.flash_ctrl_otp_reset.333436820
Short name	T1022
Test name
Test status
Simulation time	80577500 ps
CPU time	132.91 seconds
Started	Jul 23 04:47:19 PM PDT 24
Finished	Jul 23 04:49:33 PM PDT 24
Peak memory	260192 kb
Host	smart-e0ced097-64d5-4091-aa0b-2d14392133d8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333436820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_ot p_reset.333436820
Directory	/workspace/34.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.2028698694
Short name	T986
Test name
Test status
Simulation time	27289300 ps
CPU time	30.96 seconds
Started	Jul 23 04:47:14 PM PDT 24
Finished	Jul 23 04:47:46 PM PDT 24
Peak memory	275688 kb
Host	smart-ae1c4edb-4b78-4d75-baa6-961ade94e900
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028698694 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.2028698694
Directory	/workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/34.flash_ctrl_sec_info_access.1726754702
Short name	T416
Test name
Test status
Simulation time	2528177700 ps
CPU time	70.33 seconds
Started	Jul 23 04:47:16 PM PDT 24
Finished	Jul 23 04:48:27 PM PDT 24
Peak memory	263688 kb
Host	smart-d1bb7b67-f4b7-4918-8116-274274c52bd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726754702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.1726754702
Directory	/workspace/34.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/34.flash_ctrl_smoke.2210687637
Short name	T1089
Test name
Test status
Simulation time	84994800 ps
CPU time	192.5 seconds
Started	Jul 23 04:47:16 PM PDT 24
Finished	Jul 23 04:50:30 PM PDT 24
Peak memory	277544 kb
Host	smart-0c99ffe1-23f0-48e5-bbdc-27e66e40756e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2210687637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.2210687637
Directory	/workspace/34.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.flash_ctrl_alert_test.1118131984
Short name	T1024
Test name
Test status
Simulation time	37767400 ps
CPU time	13.93 seconds
Started	Jul 23 04:47:14 PM PDT 24
Finished	Jul 23 04:47:29 PM PDT 24
Peak memory	258104 kb
Host	smart-44761023-5af1-4bca-a686-d513cdb3f717
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118131984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test. 1118131984
Directory	/workspace/35.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.flash_ctrl_connect.2273441041
Short name	T492
Test name
Test status
Simulation time	25644600 ps
CPU time	15.6 seconds
Started	Jul 23 04:47:17 PM PDT 24
Finished	Jul 23 04:47:34 PM PDT 24
Peak memory	284428 kb
Host	smart-9790f68a-ce02-4b8f-91fc-ad699b51505b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2273441041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2273441041
Directory	/workspace/35.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/35.flash_ctrl_disable.1173116770
Short name	T455
Test name
Test status
Simulation time	16218200 ps
CPU time	20.78 seconds
Started	Jul 23 04:47:18 PM PDT 24
Finished	Jul 23 04:47:41 PM PDT 24
Peak memory	273548 kb
Host	smart-83a5222e-833b-4561-9c47-d3a93aba1d80
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173116770 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_disable.1173116770
Directory	/workspace/35.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/35.flash_ctrl_hw_sec_otp.3937475888
Short name	T117
Test name
Test status
Simulation time	4721435200 ps
CPU time	121.96 seconds
Started	Jul 23 04:47:16 PM PDT 24
Finished	Jul 23 04:49:19 PM PDT 24
Peak memory	260812 kb
Host	smart-3d000e9d-c852-4808-878c-63fcfcd62b46
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937475888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ hw_sec_otp.3937475888
Directory	/workspace/35.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd.2000773997
Short name	T365
Test name
Test status
Simulation time	1807695300 ps
CPU time	144.17 seconds
Started	Jul 23 04:47:16 PM PDT 24
Finished	Jul 23 04:49:42 PM PDT 24
Peak memory	294052 kb
Host	smart-28b4967e-a430-4f34-92ae-2eb021dd0dd3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000773997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla sh_ctrl_intr_rd.2000773997
Directory	/workspace/35.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.3365035039
Short name	T86
Test name
Test status
Simulation time	8497112000 ps
CPU time	202.34 seconds
Started	Jul 23 04:47:18 PM PDT 24
Finished	Jul 23 04:50:41 PM PDT 24
Peak memory	293280 kb
Host	smart-e15cea59-ea5e-4925-842b-e97a0637f395
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365035039 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.3365035039
Directory	/workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/35.flash_ctrl_otp_reset.3678888479
Short name	T627
Test name
Test status
Simulation time	149465000 ps
CPU time	132.06 seconds
Started	Jul 23 04:47:15 PM PDT 24
Finished	Jul 23 04:49:28 PM PDT 24
Peak memory	260964 kb
Host	smart-7e193a81-c626-442e-876a-f0da11028b68
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678888479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o tp_reset.3678888479
Directory	/workspace/35.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/35.flash_ctrl_rw_evict.3953282950
Short name	T598
Test name
Test status
Simulation time	76013900 ps
CPU time	28.63 seconds
Started	Jul 23 04:47:20 PM PDT 24
Finished	Jul 23 04:47:50 PM PDT 24
Peak memory	268480 kb
Host	smart-5db12f75-2504-4223-a787-d4e72ced136f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953282950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl ash_ctrl_rw_evict.3953282950
Directory	/workspace/35.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.1033167642
Short name	T502
Test name
Test status
Simulation time	68169700 ps
CPU time	30.38 seconds
Started	Jul 23 04:47:16 PM PDT 24
Finished	Jul 23 04:47:48 PM PDT 24
Peak memory	268436 kb
Host	smart-e590ab89-4a07-4203-a767-9ead6b819567
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033167642 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.1033167642
Directory	/workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/35.flash_ctrl_sec_info_access.2667739534
Short name	T594
Test name
Test status
Simulation time	7903458800 ps
CPU time	76.19 seconds
Started	Jul 23 04:47:16 PM PDT 24
Finished	Jul 23 04:48:34 PM PDT 24
Peak memory	263108 kb
Host	smart-5ccf5327-5c5c-45c1-b7fe-71ae11a5b1de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2667739534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.2667739534
Directory	/workspace/35.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/35.flash_ctrl_smoke.3907480561
Short name	T761
Test name
Test status
Simulation time	43046900 ps
CPU time	147.25 seconds
Started	Jul 23 04:47:19 PM PDT 24
Finished	Jul 23 04:49:48 PM PDT 24
Peak memory	278148 kb
Host	smart-f3ee1335-8d7e-4b0b-926d-c336cb385b06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3907480561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.3907480561
Directory	/workspace/35.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.flash_ctrl_alert_test.2541954259
Short name	T475
Test name
Test status
Simulation time	32378700 ps
CPU time	13.66 seconds
Started	Jul 23 04:47:24 PM PDT 24
Finished	Jul 23 04:47:40 PM PDT 24
Peak memory	258328 kb
Host	smart-306d9e35-53e9-4de5-885f-5a9cada4e7b0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541954259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test. 2541954259
Directory	/workspace/36.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.flash_ctrl_connect.3363710198
Short name	T206
Test name
Test status
Simulation time	23932700 ps
CPU time	15.6 seconds
Started	Jul 23 04:47:24 PM PDT 24
Finished	Jul 23 04:47:42 PM PDT 24
Peak memory	284444 kb
Host	smart-eca327ad-1657-473d-ae8e-aff9b0104bba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363710198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.3363710198
Directory	/workspace/36.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/36.flash_ctrl_disable.1545132768
Short name	T1008
Test name
Test status
Simulation time	30776800 ps
CPU time	21.64 seconds
Started	Jul 23 04:47:18 PM PDT 24
Finished	Jul 23 04:47:41 PM PDT 24
Peak memory	273648 kb
Host	smart-7d5e33f6-c6c5-4bbf-9a34-cba5d6acc09a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545132768 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_disable.1545132768
Directory	/workspace/36.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/36.flash_ctrl_hw_sec_otp.104119710
Short name	T1006
Test name
Test status
Simulation time	3205815700 ps
CPU time	275.96 seconds
Started	Jul 23 04:47:15 PM PDT 24
Finished	Jul 23 04:51:52 PM PDT 24
Peak memory	260972 kb
Host	smart-81ea0f09-7ad1-4c29-9e99-35b2d1c59ee2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104119710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_h w_sec_otp.104119710
Directory	/workspace/36.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd.2074453347
Short name	T830
Test name
Test status
Simulation time	1889325100 ps
CPU time	212.48 seconds
Started	Jul 23 04:47:16 PM PDT 24
Finished	Jul 23 04:50:49 PM PDT 24
Peak memory	284900 kb
Host	smart-35a48525-be7e-4f99-b042-102df14c7818
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074453347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla sh_ctrl_intr_rd.2074453347
Directory	/workspace/36.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.2037753999
Short name	T1014
Test name
Test status
Simulation time	114659695000 ps
CPU time	492.38 seconds
Started	Jul 23 04:47:18 PM PDT 24
Finished	Jul 23 04:55:32 PM PDT 24
Peak memory	292040 kb
Host	smart-2c9d1775-20ca-4fe3-a969-5aa9e59988c9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037753999 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.2037753999
Directory	/workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/36.flash_ctrl_otp_reset.3294633509
Short name	T109
Test name
Test status
Simulation time	373750400 ps
CPU time	109.72 seconds
Started	Jul 23 04:47:15 PM PDT 24
Finished	Jul 23 04:49:05 PM PDT 24
Peak memory	261092 kb
Host	smart-2be0e26e-3340-47d9-8427-1a2c70a2aaa8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294633509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o tp_reset.3294633509
Directory	/workspace/36.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/36.flash_ctrl_rw_evict.1507024456
Short name	T205
Test name
Test status
Simulation time	41498600 ps
CPU time	30.72 seconds
Started	Jul 23 04:47:16 PM PDT 24
Finished	Jul 23 04:47:49 PM PDT 24
Peak memory	275632 kb
Host	smart-f333cc40-4102-48ff-8ff5-dc4160cda148
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507024456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl ash_ctrl_rw_evict.1507024456
Directory	/workspace/36.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.3585099318
Short name	T204
Test name
Test status
Simulation time	44480400 ps
CPU time	28.96 seconds
Started	Jul 23 04:47:15 PM PDT 24
Finished	Jul 23 04:47:45 PM PDT 24
Peak memory	275624 kb
Host	smart-0e952f6c-f505-4950-bb9b-342b259f8afd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585099318 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.3585099318
Directory	/workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/36.flash_ctrl_sec_info_access.2334126883
Short name	T412
Test name
Test status
Simulation time	2835802800 ps
CPU time	59.34 seconds
Started	Jul 23 04:47:23 PM PDT 24
Finished	Jul 23 04:48:24 PM PDT 24
Peak memory	263740 kb
Host	smart-022e06b8-d5b5-4845-a267-021da9ced763
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334126883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.2334126883
Directory	/workspace/36.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/36.flash_ctrl_smoke.3185319774
Short name	T653
Test name
Test status
Simulation time	25412600 ps
CPU time	76.33 seconds
Started	Jul 23 04:47:15 PM PDT 24
Finished	Jul 23 04:48:32 PM PDT 24
Peak memory	275528 kb
Host	smart-b6179c5c-454e-4c51-87b4-6b3cdd33292a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3185319774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.3185319774
Directory	/workspace/36.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.flash_ctrl_alert_test.3927180664
Short name	T560
Test name
Test status
Simulation time	131322000 ps
CPU time	13.82 seconds
Started	Jul 23 04:47:24 PM PDT 24
Finished	Jul 23 04:47:39 PM PDT 24
Peak memory	258296 kb
Host	smart-a46c5d25-c4f4-497a-98fe-1dd51ef12b0c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927180664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test. 3927180664
Directory	/workspace/37.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.flash_ctrl_connect.2679312193
Short name	T128
Test name
Test status
Simulation time	14250700 ps
CPU time	16.04 seconds
Started	Jul 23 04:47:23 PM PDT 24
Finished	Jul 23 04:47:40 PM PDT 24
Peak memory	274844 kb
Host	smart-5e9e0310-5c33-4f1a-9291-c4a5d2c3f403
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2679312193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.2679312193
Directory	/workspace/37.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/37.flash_ctrl_disable.2413120111
Short name	T1033
Test name
Test status
Simulation time	10216500 ps
CPU time	21.55 seconds
Started	Jul 23 04:47:24 PM PDT 24
Finished	Jul 23 04:47:48 PM PDT 24
Peak memory	274680 kb
Host	smart-8c8ce093-0abd-449d-875b-3496d7d8b3f3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413120111 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_disable.2413120111
Directory	/workspace/37.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/37.flash_ctrl_hw_sec_otp.1092528748
Short name	T529
Test name
Test status
Simulation time	24823783900 ps
CPU time	103.07 seconds
Started	Jul 23 04:47:24 PM PDT 24
Finished	Jul 23 04:49:09 PM PDT 24
Peak memory	263204 kb
Host	smart-c57c5e39-978a-4a4e-942f-554d7495ebf9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092528748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_ hw_sec_otp.1092528748
Directory	/workspace/37.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd.2856577369
Short name	T913
Test name
Test status
Simulation time	1472114100 ps
CPU time	126.01 seconds
Started	Jul 23 04:47:24 PM PDT 24
Finished	Jul 23 04:49:31 PM PDT 24
Peak memory	293452 kb
Host	smart-b535b40a-c464-4cdc-b44c-b50f0543632f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856577369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla sh_ctrl_intr_rd.2856577369
Directory	/workspace/37.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.1497438903
Short name	T457
Test name
Test status
Simulation time	51041395500 ps
CPU time	158.94 seconds
Started	Jul 23 04:47:23 PM PDT 24
Finished	Jul 23 04:50:03 PM PDT 24
Peak memory	292868 kb
Host	smart-cb5f2605-1879-4905-a6bf-f358874896c1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497438903 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.1497438903
Directory	/workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/37.flash_ctrl_otp_reset.3386413835
Short name	T727
Test name
Test status
Simulation time	39024000 ps
CPU time	130.19 seconds
Started	Jul 23 04:47:25 PM PDT 24
Finished	Jul 23 04:49:37 PM PDT 24
Peak memory	261020 kb
Host	smart-08f358db-c8a0-4de6-a466-a8b16127785f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386413835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o tp_reset.3386413835
Directory	/workspace/37.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict.3215122541
Short name	T535
Test name
Test status
Simulation time	48880600 ps
CPU time	30.14 seconds
Started	Jul 23 04:47:24 PM PDT 24
Finished	Jul 23 04:47:55 PM PDT 24
Peak memory	268504 kb
Host	smart-8dc68bb3-9d99-4d65-84f0-b02a3cd3f329
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215122541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl ash_ctrl_rw_evict.3215122541
Directory	/workspace/37.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.3425614238
Short name	T721
Test name
Test status
Simulation time	28909700 ps
CPU time	32.07 seconds
Started	Jul 23 04:47:24 PM PDT 24
Finished	Jul 23 04:47:58 PM PDT 24
Peak memory	275600 kb
Host	smart-3cf7b51b-b088-41fd-9858-8f26af1e536e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425614238 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.3425614238
Directory	/workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/37.flash_ctrl_sec_info_access.1545129877
Short name	T1090
Test name
Test status
Simulation time	787135900 ps
CPU time	64.59 seconds
Started	Jul 23 04:47:25 PM PDT 24
Finished	Jul 23 04:48:31 PM PDT 24
Peak memory	263156 kb
Host	smart-f000fb71-e563-43ec-88db-e6bd4a58a8b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1545129877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.1545129877
Directory	/workspace/37.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/37.flash_ctrl_smoke.3707427140
Short name	T251
Test name
Test status
Simulation time	2839221200 ps
CPU time	174.39 seconds
Started	Jul 23 04:47:24 PM PDT 24
Finished	Jul 23 04:50:20 PM PDT 24
Peak memory	281540 kb
Host	smart-b37adcb2-4242-43f6-b42a-b06dbed59a50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3707427140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.3707427140
Directory	/workspace/37.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.flash_ctrl_alert_test.2537362447
Short name	T346
Test name
Test status
Simulation time	179867000 ps
CPU time	14.02 seconds
Started	Jul 23 04:47:27 PM PDT 24
Finished	Jul 23 04:47:42 PM PDT 24
Peak memory	258388 kb
Host	smart-7f1f27af-9405-41c6-b51c-d1a5c9709dbf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537362447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test. 2537362447
Directory	/workspace/38.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.flash_ctrl_connect.3436242845
Short name	T611
Test name
Test status
Simulation time	22851700 ps
CPU time	13.47 seconds
Started	Jul 23 04:47:24 PM PDT 24
Finished	Jul 23 04:47:40 PM PDT 24
Peak memory	274912 kb
Host	smart-1b20a847-40de-4170-8327-e88aad350dd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3436242845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.3436242845
Directory	/workspace/38.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/38.flash_ctrl_disable.211806975
Short name	T716
Test name
Test status
Simulation time	15444300 ps
CPU time	21.64 seconds
Started	Jul 23 04:47:25 PM PDT 24
Finished	Jul 23 04:47:48 PM PDT 24
Peak memory	273612 kb
Host	smart-c6b62beb-44c2-4786-a850-ec3e7979d0c1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211806975 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_disable.211806975
Directory	/workspace/38.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/38.flash_ctrl_hw_sec_otp.3790122465
Short name	T1087
Test name
Test status
Simulation time	2938488000 ps
CPU time	233.56 seconds
Started	Jul 23 04:47:25 PM PDT 24
Finished	Jul 23 04:51:20 PM PDT 24
Peak memory	261396 kb
Host	smart-cd790bc4-af9f-45d2-8569-ddf54f9c43f4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790122465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ hw_sec_otp.3790122465
Directory	/workspace/38.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd.3686364871
Short name	T359
Test name
Test status
Simulation time	1400982700 ps
CPU time	146.88 seconds
Started	Jul 23 04:47:24 PM PDT 24
Finished	Jul 23 04:49:53 PM PDT 24
Peak memory	294020 kb
Host	smart-faac40c2-1a33-47d1-94b5-02518a340944
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686364871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla sh_ctrl_intr_rd.3686364871
Directory	/workspace/38.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.289335258
Short name	T699
Test name
Test status
Simulation time	12270940300 ps
CPU time	265.56 seconds
Started	Jul 23 04:47:24 PM PDT 24
Finished	Jul 23 04:51:51 PM PDT 24
Peak memory	289992 kb
Host	smart-b9afc5c6-eb1e-4b12-bd8e-107f8d07fd45
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289335258 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.289335258
Directory	/workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/38.flash_ctrl_otp_reset.616404086
Short name	T720
Test name
Test status
Simulation time	39539700 ps
CPU time	129.19 seconds
Started	Jul 23 04:47:23 PM PDT 24
Finished	Jul 23 04:49:33 PM PDT 24
Peak memory	260048 kb
Host	smart-e4afbcf2-6932-4361-b0f1-3bbc853b77c6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616404086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ot p_reset.616404086
Directory	/workspace/38.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/38.flash_ctrl_rw_evict.924149583
Short name	T623
Test name
Test status
Simulation time	36509100 ps
CPU time	29.95 seconds
Started	Jul 23 04:47:25 PM PDT 24
Finished	Jul 23 04:47:57 PM PDT 24
Peak memory	268420 kb
Host	smart-42cb2f40-50df-4b18-b75c-1744963ad031
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924149583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla sh_ctrl_rw_evict.924149583
Directory	/workspace/38.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.2421143288
Short name	T527
Test name
Test status
Simulation time	29269500 ps
CPU time	28.64 seconds
Started	Jul 23 04:47:24 PM PDT 24
Finished	Jul 23 04:47:55 PM PDT 24
Peak memory	267424 kb
Host	smart-e1180899-d370-4f06-9847-38bbb73a09c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421143288 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.2421143288
Directory	/workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/38.flash_ctrl_sec_info_access.2620928809
Short name	T717
Test name
Test status
Simulation time	488272700 ps
CPU time	58.91 seconds
Started	Jul 23 04:47:26 PM PDT 24
Finished	Jul 23 04:48:26 PM PDT 24
Peak memory	264900 kb
Host	smart-4dc7ad9d-da9c-47fd-9bfb-f3e7eb43ac52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620928809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.2620928809
Directory	/workspace/38.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/38.flash_ctrl_smoke.2877350049
Short name	T942
Test name
Test status
Simulation time	31336300 ps
CPU time	168.28 seconds
Started	Jul 23 04:47:24 PM PDT 24
Finished	Jul 23 04:50:14 PM PDT 24
Peak memory	277236 kb
Host	smart-1e7a6ad2-eea4-4dc3-a9f9-20267c95c878
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877350049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.2877350049
Directory	/workspace/38.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.flash_ctrl_alert_test.3546594152
Short name	T709
Test name
Test status
Simulation time	201410400 ps
CPU time	14.07 seconds
Started	Jul 23 04:47:30 PM PDT 24
Finished	Jul 23 04:47:46 PM PDT 24
Peak memory	265208 kb
Host	smart-0723286b-8543-4852-a1ee-8aae38fa01d0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546594152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test. 3546594152
Directory	/workspace/39.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.flash_ctrl_connect.1165604719
Short name	T700
Test name
Test status
Simulation time	46581000 ps
CPU time	13.44 seconds
Started	Jul 23 04:47:36 PM PDT 24
Finished	Jul 23 04:47:51 PM PDT 24
Peak memory	274944 kb
Host	smart-1ac31334-335c-4c7e-9cca-e0cd1d1586b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1165604719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.1165604719
Directory	/workspace/39.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/39.flash_ctrl_disable.642854996
Short name	T836
Test name
Test status
Simulation time	28773400 ps
CPU time	22.1 seconds
Started	Jul 23 04:47:29 PM PDT 24
Finished	Jul 23 04:47:53 PM PDT 24
Peak memory	273536 kb
Host	smart-f6d8c24f-fcfe-41a2-b03f-cef31a27d9ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642854996 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_disable.642854996
Directory	/workspace/39.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/39.flash_ctrl_hw_sec_otp.1044045637
Short name	T1093
Test name
Test status
Simulation time	5896165800 ps
CPU time	89.93 seconds
Started	Jul 23 04:47:31 PM PDT 24
Finished	Jul 23 04:49:03 PM PDT 24
Peak memory	260888 kb
Host	smart-8d1a2977-2581-4f6d-a358-788462189ad5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044045637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_ hw_sec_otp.1044045637
Directory	/workspace/39.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd.2786577919
Short name	T742
Test name
Test status
Simulation time	1587161400 ps
CPU time	188.36 seconds
Started	Jul 23 04:47:33 PM PDT 24
Finished	Jul 23 04:50:43 PM PDT 24
Peak memory	285104 kb
Host	smart-ef90b25f-1c72-45e0-a91b-83f3ea09ae60
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786577919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla sh_ctrl_intr_rd.2786577919
Directory	/workspace/39.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/39.flash_ctrl_otp_reset.4279473896
Short name	T191
Test name
Test status
Simulation time	150188100 ps
CPU time	130.56 seconds
Started	Jul 23 04:47:30 PM PDT 24
Finished	Jul 23 04:49:42 PM PDT 24
Peak memory	265044 kb
Host	smart-2a061b27-5da3-47d7-8573-d2885a798935
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279473896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o tp_reset.4279473896
Directory	/workspace/39.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/39.flash_ctrl_rw_evict.94412764
Short name	T868
Test name
Test status
Simulation time	29690700 ps
CPU time	30.81 seconds
Started	Jul 23 04:47:33 PM PDT 24
Finished	Jul 23 04:48:06 PM PDT 24
Peak memory	273836 kb
Host	smart-a8ffb605-90d4-4fa4-a765-a1f17bcb4d8f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94412764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flas h_ctrl_rw_evict.94412764
Directory	/workspace/39.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.753932595
Short name	T3
Test name
Test status
Simulation time	34019800 ps
CPU time	30.78 seconds
Started	Jul 23 04:47:31 PM PDT 24
Finished	Jul 23 04:48:04 PM PDT 24
Peak memory	275656 kb
Host	smart-7cd01552-d7e6-4e14-8242-77a8ada1148d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753932595 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.753932595
Directory	/workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/39.flash_ctrl_sec_info_access.1392826799
Short name	T448
Test name
Test status
Simulation time	1194233500 ps
CPU time	60.49 seconds
Started	Jul 23 04:47:35 PM PDT 24
Finished	Jul 23 04:48:36 PM PDT 24
Peak memory	265084 kb
Host	smart-d5d318ca-1a9e-42c6-b32a-0eddbad5869d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1392826799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.1392826799
Directory	/workspace/39.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/39.flash_ctrl_smoke.4277398238
Short name	T398
Test name
Test status
Simulation time	37184500 ps
CPU time	76.77 seconds
Started	Jul 23 04:47:31 PM PDT 24
Finished	Jul 23 04:48:50 PM PDT 24
Peak memory	276468 kb
Host	smart-2f9e55d9-98f3-45fe-8a10-fa1878ac6d38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4277398238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.4277398238
Directory	/workspace/39.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_alert_test.1662152049
Short name	T480
Test name
Test status
Simulation time	69067100 ps
CPU time	13.57 seconds
Started	Jul 23 04:44:32 PM PDT 24
Finished	Jul 23 04:44:49 PM PDT 24
Peak memory	258284 kb
Host	smart-e8e4a80d-af8e-462c-91f8-c28e5a5f5402
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662152049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.1 662152049
Directory	/workspace/4.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.flash_ctrl_config_regwen.1214967340
Short name	T654
Test name
Test status
Simulation time	36842700 ps
CPU time	13.9 seconds
Started	Jul 23 04:44:33 PM PDT 24
Finished	Jul 23 04:44:51 PM PDT 24
Peak memory	261716 kb
Host	smart-3826079f-65f1-4e80-92dd-4d2c1e83ce08
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214967340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .flash_ctrl_config_regwen.1214967340
Directory	/workspace/4.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/4.flash_ctrl_connect.3868105972
Short name	T825
Test name
Test status
Simulation time	14205500 ps
CPU time	16.08 seconds
Started	Jul 23 04:44:36 PM PDT 24
Finished	Jul 23 04:44:58 PM PDT 24
Peak memory	284332 kb
Host	smart-1ac64a8d-764f-430e-b544-5c37bfb270e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3868105972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.3868105972
Directory	/workspace/4.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/4.flash_ctrl_disable.64354911
Short name	T1054
Test name
Test status
Simulation time	13810600 ps
CPU time	22.03 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 04:45:03 PM PDT 24
Peak memory	273892 kb
Host	smart-372bde6c-c70f-4f12-a781-97e24c7df691
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64354911 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 4.flash_ctrl_disable.64354911
Directory	/workspace/4.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_mp.2262463584
Short name	T488
Test name
Test status
Simulation time	30602275400 ps
CPU time	2266.61 seconds
Started	Jul 23 04:44:31 PM PDT 24
Finished	Jul 23 05:22:21 PM PDT 24
Peak memory	265152 kb
Host	smart-c509f7ec-b2a1-41f4-a280-66d8c03a1e59
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2262463584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.2262463584
Directory	/workspace/4.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_type.2998395685
Short name	T908
Test name
Test status
Simulation time	4551626400 ps
CPU time	1926.33 seconds
Started	Jul 23 04:44:27 PM PDT 24
Finished	Jul 23 05:16:38 PM PDT 24
Peak memory	265172 kb
Host	smart-285a3713-7863-4513-9fb2-cb2ccd739f25
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998395685 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.2998395685
Directory	/workspace/4.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_win.1400187099
Short name	T533
Test name
Test status
Simulation time	839228000 ps
CPU time	890.39 seconds
Started	Jul 23 04:44:24 PM PDT 24
Finished	Jul 23 04:59:18 PM PDT 24
Peak memory	273464 kb
Host	smart-c7158eb1-319f-4030-aed0-c6cee4505309
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1400187099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.1400187099
Directory	/workspace/4.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fetch_code.1634688757
Short name	T854
Test name
Test status
Simulation time	599982600 ps
CPU time	22.66 seconds
Started	Jul 23 04:44:25 PM PDT 24
Finished	Jul 23 04:44:53 PM PDT 24
Peak memory	263672 kb
Host	smart-2e5f754d-5db7-4b33-9b16-531f1d039a94
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634688757 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.1634688757
Directory	/workspace/4.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/4.flash_ctrl_full_mem_access.4130773881
Short name	T126
Test name
Test status
Simulation time	324141008800 ps
CPU time	2835.34 seconds
Started	Jul 23 04:44:24 PM PDT 24
Finished	Jul 23 05:31:43 PM PDT 24
Peak memory	263240 kb
Host	smart-8d2fd92b-c8b7-4691-b623-51b9590b6c81
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130773881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c trl_full_mem_access.4130773881
Directory	/workspace/4.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_dir_rd.4058081572
Short name	T79
Test name
Test status
Simulation time	34513300 ps
CPU time	26.59 seconds
Started	Jul 23 04:44:29 PM PDT 24
Finished	Jul 23 04:44:59 PM PDT 24
Peak memory	265164 kb
Host	smart-55899720-79e7-4289-a500-5826b30bbfbd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4058081572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.4058081572
Directory	/workspace/4.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.2826056992
Short name	T531
Test name
Test status
Simulation time	10031020900 ps
CPU time	50.35 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 04:45:31 PM PDT 24
Peak memory	274496 kb
Host	smart-93c62674-b16f-442f-ac68-2a074d0739e0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826056992 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.2826056992
Directory	/workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.3093110372
Short name	T214
Test name
Test status
Simulation time	15384300 ps
CPU time	13.4 seconds
Started	Jul 23 04:44:34 PM PDT 24
Finished	Jul 23 04:44:53 PM PDT 24
Peak memory	258468 kb
Host	smart-51cf7c02-c3a4-4f46-9e58-a12f77920e54
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093110372 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.3093110372
Directory	/workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_rma_reset.3829990543
Short name	T177
Test name
Test status
Simulation time	350283549900 ps
CPU time	1147.83 seconds
Started	Jul 23 04:44:32 PM PDT 24
Finished	Jul 23 05:03:43 PM PDT 24
Peak memory	264356 kb
Host	smart-8ac12a81-1f4d-4d81-a326-f43f4fc33421
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829990543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.flash_ctrl_hw_rma_reset.3829990543
Directory	/workspace/4.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_sec_otp.4155537367
Short name	T684
Test name
Test status
Simulation time	1469294700 ps
CPU time	56.26 seconds
Started	Jul 23 04:44:24 PM PDT 24
Finished	Jul 23 04:45:24 PM PDT 24
Peak memory	262756 kb
Host	smart-cdb60ac8-0ae8-42be-9a07-04eceed24011
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155537367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h w_sec_otp.4155537367
Directory	/workspace/4.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_integrity.3942137652
Short name	T270
Test name
Test status
Simulation time	4690993300 ps
CPU time	656.8 seconds
Started	Jul 23 04:44:33 PM PDT 24
Finished	Jul 23 04:55:33 PM PDT 24
Peak memory	342480 kb
Host	smart-e6307cef-7346-4d4e-a98a-75767678743d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942137652 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_integrity.3942137652
Directory	/workspace/4.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_rd.2651833938
Short name	T360
Test name
Test status
Simulation time	10690762300 ps
CPU time	242.54 seconds
Started	Jul 23 04:44:27 PM PDT 24
Finished	Jul 23 04:48:34 PM PDT 24
Peak memory	284656 kb
Host	smart-9a43199c-b4f5-4c39-975c-21eda1a78dec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651833938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_intr_rd.2651833938
Directory	/workspace/4.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.3841099464
Short name	T987
Test name
Test status
Simulation time	23945681100 ps
CPU time	245.11 seconds
Started	Jul 23 04:44:30 PM PDT 24
Finished	Jul 23 04:48:39 PM PDT 24
Peak memory	290992 kb
Host	smart-3118f8f9-cdaa-4daa-97ae-426554ffa8fb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841099464 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.3841099464
Directory	/workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr.4075311242
Short name	T558
Test name
Test status
Simulation time	4826976400 ps
CPU time	76.05 seconds
Started	Jul 23 04:44:25 PM PDT 24
Finished	Jul 23 04:45:46 PM PDT 24
Peak memory	265244 kb
Host	smart-556e4c8c-6854-4fd5-91d5-4121b907ea6c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075311242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.flash_ctrl_intr_wr.4075311242
Directory	/workspace/4.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.443714265
Short name	T816
Test name
Test status
Simulation time	41602967800 ps
CPU time	197.94 seconds
Started	Jul 23 04:44:24 PM PDT 24
Finished	Jul 23 04:47:46 PM PDT 24
Peak memory	260420 kb
Host	smart-1f7a6a3a-3bab-4c61-87d2-4ac3afc47a15
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443 714265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.443714265
Directory	/workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_invalid_op.2818778913
Short name	T515
Test name
Test status
Simulation time	2564079400 ps
CPU time	87.48 seconds
Started	Jul 23 04:44:28 PM PDT 24
Finished	Jul 23 04:46:00 PM PDT 24
Peak memory	260504 kb
Host	smart-fd70b9d6-3d20-4ae5-9c8d-3827d6a2018e
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818778913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.2818778913
Directory	/workspace/4.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_lcmgr_intg.1784618553
Short name	T172
Test name
Test status
Simulation time	33777100 ps
CPU time	13.31 seconds
Started	Jul 23 04:44:32 PM PDT 24
Finished	Jul 23 04:44:49 PM PDT 24
Peak memory	260008 kb
Host	smart-8edb0a92-1353-4a1e-b169-62499e11af55
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784618553 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.1784618553
Directory	/workspace/4.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/4.flash_ctrl_mid_op_rst.560219858
Short name	T1099
Test name
Test status
Simulation time	932645700 ps
CPU time	67.47 seconds
Started	Jul 23 04:44:28 PM PDT 24
Finished	Jul 23 04:45:40 PM PDT 24
Peak memory	260588 kb
Host	smart-a0213e51-b9cd-4419-9736-3c1008bc5a0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=560219858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.560219858
Directory	/workspace/4.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/4.flash_ctrl_mp_regions.4047479039
Short name	T1114
Test name
Test status
Simulation time	19382246700 ps
CPU time	291.13 seconds
Started	Jul 23 04:44:27 PM PDT 24
Finished	Jul 23 04:49:23 PM PDT 24
Peak memory	275008 kb
Host	smart-1c318f5f-a257-4d89-9ce0-70a8adb87036
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047479039 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.4047479039
Directory	/workspace/4.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/4.flash_ctrl_otp_reset.599622559
Short name	T812
Test name
Test status
Simulation time	397231900 ps
CPU time	131.89 seconds
Started	Jul 23 04:44:33 PM PDT 24
Finished	Jul 23 04:46:49 PM PDT 24
Peak memory	260088 kb
Host	smart-5c42395f-4396-417a-babe-fec358819947
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599622559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_otp _reset.599622559
Directory	/workspace/4.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_oversize_error.2417490201
Short name	T630
Test name
Test status
Simulation time	1031545700 ps
CPU time	158.93 seconds
Started	Jul 23 04:44:26 PM PDT 24
Finished	Jul 23 04:47:10 PM PDT 24
Peak memory	290488 kb
Host	smart-d0334341-7ddc-4b96-9df9-f98a0cb67ad9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417490201 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.2417490201
Directory	/workspace/4.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_arb.3148785419
Short name	T990
Test name
Test status
Simulation time	4118270100 ps
CPU time	501.73 seconds
Started	Jul 23 04:44:25 PM PDT 24
Finished	Jul 23 04:52:52 PM PDT 24
Peak memory	263292 kb
Host	smart-eda1c591-81d6-4124-a6dd-94f2900a1da1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3148785419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.3148785419
Directory	/workspace/4.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/4.flash_ctrl_prog_reset.1282270422
Short name	T609
Test name
Test status
Simulation time	22214000 ps
CPU time	13.73 seconds
Started	Jul 23 04:44:25 PM PDT 24
Finished	Jul 23 04:44:44 PM PDT 24
Peak memory	258976 kb
Host	smart-af39eb71-68f5-46ed-aa07-798416409bc2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282270422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.flash_ctrl_prog_reset.1282270422
Directory	/workspace/4.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rand_ops.241064315
Short name	T706
Test name
Test status
Simulation time	706194800 ps
CPU time	924.31 seconds
Started	Jul 23 04:44:23 PM PDT 24
Finished	Jul 23 04:59:51 PM PDT 24
Peak memory	285624 kb
Host	smart-3f8e1cac-83ed-4343-8063-ce0e98505da5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=241064315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.241064315
Directory	/workspace/4.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rd_buff_evict.2535676101
Short name	T875
Test name
Test status
Simulation time	159660000 ps
CPU time	97.63 seconds
Started	Jul 23 04:44:31 PM PDT 24
Finished	Jul 23 04:46:12 PM PDT 24
Peak memory	262664 kb
Host	smart-d986469b-91af-4f4c-a26a-6d5354c8f69d
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2535676101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2535676101
Directory	/workspace/4.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_re_evict.3424467191
Short name	T427
Test name
Test status
Simulation time	75552800 ps
CPU time	32.33 seconds
Started	Jul 23 04:44:30 PM PDT 24
Finished	Jul 23 04:45:06 PM PDT 24
Peak memory	275676 kb
Host	smart-28c94ec2-c261-4afa-bc36-17807e388edb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424467191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_re_evict.3424467191
Directory	/workspace/4.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.1275667765
Short name	T228
Test name
Test status
Simulation time	22167100 ps
CPU time	22.2 seconds
Started	Jul 23 04:44:32 PM PDT 24
Finished	Jul 23 04:44:58 PM PDT 24
Peak memory	265336 kb
Host	smart-6d0775c1-2fbd-40ab-bb20-938598f1200b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275667765 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.1275667765
Directory	/workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.3962332412
Short name	T551
Test name
Test status
Simulation time	24815200 ps
CPU time	22.74 seconds
Started	Jul 23 04:44:33 PM PDT 24
Finished	Jul 23 04:44:59 PM PDT 24
Peak memory	265324 kb
Host	smart-5ebfb66b-3f3b-477a-9485-d5d8a7ef8ffa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962332412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl ash_ctrl_read_word_sweep_serr.3962332412
Directory	/workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro.4040015762
Short name	T1048
Test name
Test status
Simulation time	1037791100 ps
CPU time	94.22 seconds
Started	Jul 23 04:44:25 PM PDT 24
Finished	Jul 23 04:46:04 PM PDT 24
Peak memory	289284 kb
Host	smart-3ee14949-d390-4833-93fd-725f288ab7c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040015762 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_ro.4040015762
Directory	/workspace/4.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_derr.2216956118
Short name	T272
Test name
Test status
Simulation time	1577867600 ps
CPU time	159.56 seconds
Started	Jul 23 04:44:27 PM PDT 24
Finished	Jul 23 04:47:11 PM PDT 24
Peak memory	282852 kb
Host	smart-d2ae633b-981c-47bb-b4c5-b92ac89d2662
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2216956118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.2216956118
Directory	/workspace/4.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_serr.4016410266
Short name	T586
Test name
Test status
Simulation time	724201100 ps
CPU time	125.14 seconds
Started	Jul 23 04:44:25 PM PDT 24
Finished	Jul 23 04:46:34 PM PDT 24
Peak memory	281784 kb
Host	smart-448df100-4889-4b9e-b803-933a6b611b4f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016410266 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.4016410266
Directory	/workspace/4.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw.2160030792
Short name	T245
Test name
Test status
Simulation time	17058365600 ps
CPU time	608.62 seconds
Started	Jul 23 04:44:25 PM PDT 24
Finished	Jul 23 04:54:39 PM PDT 24
Peak memory	314416 kb
Host	smart-f34b7850-6e41-4eef-b9f5-d68774da30eb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160030792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.flash_ctrl_rw.2160030792
Directory	/workspace/4.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_derr.3087685630
Short name	T226
Test name
Test status
Simulation time	7871576300 ps
CPU time	554.66 seconds
Started	Jul 23 04:44:29 PM PDT 24
Finished	Jul 23 04:53:48 PM PDT 24
Peak memory	335440 kb
Host	smart-95f0ef05-bbb4-4f77-b124-5479c30d4b93
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087685630 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_rw_derr.3087685630
Directory	/workspace/4.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.2898843001
Short name	T473
Test name
Test status
Simulation time	120821600 ps
CPU time	30.79 seconds
Started	Jul 23 04:44:32 PM PDT 24
Finished	Jul 23 04:45:06 PM PDT 24
Peak memory	268392 kb
Host	smart-20231818-aaca-4640-94f2-454e56345cff
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898843001 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.2898843001
Directory	/workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_cm.3072096047
Short name	T49
Test name
Test status
Simulation time	1891346900 ps
CPU time	4688.4 seconds
Started	Jul 23 04:44:32 PM PDT 24
Finished	Jul 23 06:02:44 PM PDT 24
Peak memory	284896 kb
Host	smart-7db182db-a015-4f4e-a8d2-4bda9f22fc91
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072096047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3072096047
Directory	/workspace/4.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_info_access.1998643959
Short name	T29
Test name
Test status
Simulation time	1034524600 ps
CPU time	55.53 seconds
Started	Jul 23 04:44:32 PM PDT 24
Finished	Jul 23 04:45:31 PM PDT 24
Peak memory	264296 kb
Host	smart-6b5d015c-9c49-447d-96f7-ef46b7d2cc19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1998643959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.1998643959
Directory	/workspace/4.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/4.flash_ctrl_serr_address.2585187663
Short name	T820
Test name
Test status
Simulation time	675537000 ps
CPU time	72.33 seconds
Started	Jul 23 04:44:24 PM PDT 24
Finished	Jul 23 04:45:40 PM PDT 24
Peak memory	265336 kb
Host	smart-78be2e17-3885-4f93-b59b-4b6a0e9769a7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585187663 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 4.flash_ctrl_serr_address.2585187663
Directory	/workspace/4.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/4.flash_ctrl_serr_counter.180970701
Short name	T461
Test name
Test status
Simulation time	4426290300 ps
CPU time	90.62 seconds
Started	Jul 23 04:44:33 PM PDT 24
Finished	Jul 23 04:46:07 PM PDT 24
Peak memory	274184 kb
Host	smart-e588064e-9231-421b-a2cb-0fcc9507ae60
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180970701 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 4.flash_ctrl_serr_counter.180970701
Directory	/workspace/4.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke.3146406364
Short name	T883
Test name
Test status
Simulation time	34265100 ps
CPU time	72.59 seconds
Started	Jul 23 04:44:32 PM PDT 24
Finished	Jul 23 04:45:48 PM PDT 24
Peak memory	276408 kb
Host	smart-205c6a24-fb47-4e5a-bbfa-91b42e7bc02f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3146406364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.3146406364
Directory	/workspace/4.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke_hw.2015515947
Short name	T806
Test name
Test status
Simulation time	30673800 ps
CPU time	25.99 seconds
Started	Jul 23 04:44:25 PM PDT 24
Finished	Jul 23 04:44:55 PM PDT 24
Peak memory	259496 kb
Host	smart-02d99fef-a15c-47fd-bca5-1e7f61a0d99f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2015515947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.2015515947
Directory	/workspace/4.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_stress_all.120427042
Short name	T972
Test name
Test status
Simulation time	60656400 ps
CPU time	285.32 seconds
Started	Jul 23 04:44:33 PM PDT 24
Finished	Jul 23 04:49:22 PM PDT 24
Peak memory	279056 kb
Host	smart-a3a4bcd9-49cb-4a0f-bfe3-079633a71d73
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120427042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress _all.120427042
Directory	/workspace/4.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sw_op.3304636154
Short name	T445
Test name
Test status
Simulation time	28048300 ps
CPU time	26.16 seconds
Started	Jul 23 04:44:25 PM PDT 24
Finished	Jul 23 04:44:56 PM PDT 24
Peak memory	262248 kb
Host	smart-619cd297-3df5-4f80-859b-df49c2fda19e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3304636154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.3304636154
Directory	/workspace/4.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_wo.3427834723
Short name	T1038
Test name
Test status
Simulation time	4797713500 ps
CPU time	164.68 seconds
Started	Jul 23 04:44:32 PM PDT 24
Finished	Jul 23 04:47:20 PM PDT 24
Peak memory	259400 kb
Host	smart-81f32924-4830-4ab2-928b-a73dc297645d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427834723 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.flash_ctrl_wo.3427834723
Directory	/workspace/4.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/40.flash_ctrl_alert_test.3930691702
Short name	T918
Test name
Test status
Simulation time	26046000 ps
CPU time	13.64 seconds
Started	Jul 23 04:47:31 PM PDT 24
Finished	Jul 23 04:47:46 PM PDT 24
Peak memory	265264 kb
Host	smart-aadc1669-1342-483e-afbc-850d74c115dd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930691702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test. 3930691702
Directory	/workspace/40.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.flash_ctrl_connect.3159782732
Short name	T1077
Test name
Test status
Simulation time	25130500 ps
CPU time	15.86 seconds
Started	Jul 23 04:47:34 PM PDT 24
Finished	Jul 23 04:47:51 PM PDT 24
Peak memory	275120 kb
Host	smart-5cf77bee-68b2-49a5-abf1-835432d1291d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3159782732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.3159782732
Directory	/workspace/40.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/40.flash_ctrl_disable.712862575
Short name	T657
Test name
Test status
Simulation time	9944200 ps
CPU time	21.9 seconds
Started	Jul 23 04:47:31 PM PDT 24
Finished	Jul 23 04:47:55 PM PDT 24
Peak memory	274704 kb
Host	smart-85d84ab6-5665-43d3-ba45-b37e508dc9b6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712862575 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_disable.712862575
Directory	/workspace/40.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/40.flash_ctrl_hw_sec_otp.2676436850
Short name	T829
Test name
Test status
Simulation time	17496725600 ps
CPU time	131.26 seconds
Started	Jul 23 04:47:37 PM PDT 24
Finished	Jul 23 04:49:49 PM PDT 24
Peak memory	260648 kb
Host	smart-fd33cac4-54a1-427c-8086-75296a126def
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676436850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_ hw_sec_otp.2676436850
Directory	/workspace/40.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/40.flash_ctrl_otp_reset.2466220139
Short name	T895
Test name
Test status
Simulation time	48901900 ps
CPU time	129.93 seconds
Started	Jul 23 04:47:33 PM PDT 24
Finished	Jul 23 04:49:44 PM PDT 24
Peak memory	265116 kb
Host	smart-3de8258d-0a3a-4275-9dcb-403103d80524
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466220139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o tp_reset.2466220139
Directory	/workspace/40.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/40.flash_ctrl_sec_info_access.2490454688
Short name	T701
Test name
Test status
Simulation time	23906195400 ps
CPU time	74.84 seconds
Started	Jul 23 04:47:32 PM PDT 24
Finished	Jul 23 04:48:49 PM PDT 24
Peak memory	263584 kb
Host	smart-efb324a4-5a6e-4abf-80c1-11035225863d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490454688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.2490454688
Directory	/workspace/40.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/40.flash_ctrl_smoke.2654901977
Short name	T395
Test name
Test status
Simulation time	92741500 ps
CPU time	172.44 seconds
Started	Jul 23 04:47:30 PM PDT 24
Finished	Jul 23 04:50:24 PM PDT 24
Peak memory	279676 kb
Host	smart-47e2b67a-29f9-40b9-a584-49c63b31e3b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2654901977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.2654901977
Directory	/workspace/40.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.flash_ctrl_alert_test.2981339096
Short name	T490
Test name
Test status
Simulation time	88991100 ps
CPU time	14.08 seconds
Started	Jul 23 04:47:30 PM PDT 24
Finished	Jul 23 04:47:45 PM PDT 24
Peak memory	265200 kb
Host	smart-2d9b48d0-4b64-4c1d-9320-a99cc3d9ee23
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981339096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test. 2981339096
Directory	/workspace/41.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.flash_ctrl_connect.1370028580
Short name	T1042
Test name
Test status
Simulation time	16604500 ps
CPU time	16.19 seconds
Started	Jul 23 04:47:31 PM PDT 24
Finished	Jul 23 04:47:49 PM PDT 24
Peak memory	274972 kb
Host	smart-1c8521fb-485d-4d86-b4f1-af0422b2cd32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370028580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.1370028580
Directory	/workspace/41.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/41.flash_ctrl_disable.1929999999
Short name	T900
Test name
Test status
Simulation time	118919800 ps
CPU time	21.43 seconds
Started	Jul 23 04:47:30 PM PDT 24
Finished	Jul 23 04:47:54 PM PDT 24
Peak memory	274796 kb
Host	smart-d5609bbf-6b1e-421a-aa84-b683a45bffd3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929999999 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_disable.1929999999
Directory	/workspace/41.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.1113732742
Short name	T269
Test name
Test status
Simulation time	15880899700 ps
CPU time	149.15 seconds
Started	Jul 23 04:47:32 PM PDT 24
Finished	Jul 23 04:50:03 PM PDT 24
Peak memory	262748 kb
Host	smart-887a4b27-8931-4a2d-878d-5c44a6ebcae0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113732742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ hw_sec_otp.1113732742
Directory	/workspace/41.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/41.flash_ctrl_otp_reset.602098074
Short name	T659
Test name
Test status
Simulation time	216414200 ps
CPU time	130.58 seconds
Started	Jul 23 04:47:32 PM PDT 24
Finished	Jul 23 04:49:44 PM PDT 24
Peak memory	260136 kb
Host	smart-6861de88-7c56-4750-a48a-2128b361d0ef
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602098074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ot p_reset.602098074
Directory	/workspace/41.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/41.flash_ctrl_sec_info_access.2290161457
Short name	T610
Test name
Test status
Simulation time	5971660100 ps
CPU time	73.87 seconds
Started	Jul 23 04:47:34 PM PDT 24
Finished	Jul 23 04:48:49 PM PDT 24
Peak memory	264916 kb
Host	smart-98a415f7-1348-40b3-93f9-5fec3c0ecbe7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2290161457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.2290161457
Directory	/workspace/41.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/41.flash_ctrl_smoke.3956790737
Short name	T925
Test name
Test status
Simulation time	55462400 ps
CPU time	52.12 seconds
Started	Jul 23 04:47:35 PM PDT 24
Finished	Jul 23 04:48:28 PM PDT 24
Peak memory	271364 kb
Host	smart-65de8948-7b20-441a-b2e7-6ecff36c2af1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956790737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.3956790737
Directory	/workspace/41.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.flash_ctrl_alert_test.1899128241
Short name	T90
Test name
Test status
Simulation time	76505600 ps
CPU time	13.6 seconds
Started	Jul 23 04:47:39 PM PDT 24
Finished	Jul 23 04:47:54 PM PDT 24
Peak memory	265272 kb
Host	smart-1388fb81-eaf7-4f6b-ac58-de1c2f1f50f3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899128241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test. 1899128241
Directory	/workspace/42.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.flash_ctrl_connect.2125722520
Short name	T588
Test name
Test status
Simulation time	53712300 ps
CPU time	16.07 seconds
Started	Jul 23 04:47:40 PM PDT 24
Finished	Jul 23 04:47:57 PM PDT 24
Peak memory	274816 kb
Host	smart-f664fdc9-f17d-4e4a-a8e2-9ed6bc035db7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125722520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.2125722520
Directory	/workspace/42.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/42.flash_ctrl_disable.507976775
Short name	T1096
Test name
Test status
Simulation time	46028800 ps
CPU time	20.64 seconds
Started	Jul 23 04:47:38 PM PDT 24
Finished	Jul 23 04:47:59 PM PDT 24
Peak memory	265444 kb
Host	smart-df49f37e-4b96-454a-970f-ec892d721015
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507976775 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_disable.507976775
Directory	/workspace/42.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/42.flash_ctrl_hw_sec_otp.4128325820
Short name	T547
Test name
Test status
Simulation time	10947231200 ps
CPU time	114.77 seconds
Started	Jul 23 04:47:33 PM PDT 24
Finished	Jul 23 04:49:29 PM PDT 24
Peak memory	263236 kb
Host	smart-c5bd2f29-3c44-45e5-a792-61625b507861
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128325820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_ hw_sec_otp.4128325820
Directory	/workspace/42.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/42.flash_ctrl_otp_reset.4041927213
Short name	T753
Test name
Test status
Simulation time	133064200 ps
CPU time	128.81 seconds
Started	Jul 23 04:47:33 PM PDT 24
Finished	Jul 23 04:49:43 PM PDT 24
Peak memory	260144 kb
Host	smart-2a4e5861-51e8-4778-90a0-27b4f1512260
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041927213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o tp_reset.4041927213
Directory	/workspace/42.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/42.flash_ctrl_sec_info_access.328733293
Short name	T37
Test name
Test status
Simulation time	45454237700 ps
CPU time	94.36 seconds
Started	Jul 23 04:47:36 PM PDT 24
Finished	Jul 23 04:49:12 PM PDT 24
Peak memory	263756 kb
Host	smart-ff288fb4-24b2-48d6-ab0f-19909cc5f500
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=328733293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.328733293
Directory	/workspace/42.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/42.flash_ctrl_smoke.3429769073
Short name	T938
Test name
Test status
Simulation time	47123100 ps
CPU time	170.7 seconds
Started	Jul 23 04:47:30 PM PDT 24
Finished	Jul 23 04:50:22 PM PDT 24
Peak memory	278584 kb
Host	smart-a818ed97-4ca6-4d18-b75b-426b07b69ac8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429769073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.3429769073
Directory	/workspace/42.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.flash_ctrl_alert_test.1227194596
Short name	T1074
Test name
Test status
Simulation time	85454200 ps
CPU time	13.85 seconds
Started	Jul 23 04:47:38 PM PDT 24
Finished	Jul 23 04:47:53 PM PDT 24
Peak memory	258324 kb
Host	smart-9431d772-5457-43df-8dd4-e1b782737fe5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227194596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test. 1227194596
Directory	/workspace/43.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.flash_ctrl_connect.2005118144
Short name	T704
Test name
Test status
Simulation time	44508700 ps
CPU time	13.44 seconds
Started	Jul 23 04:47:37 PM PDT 24
Finished	Jul 23 04:47:51 PM PDT 24
Peak memory	274704 kb
Host	smart-9cb266c9-c6fb-4d62-b3e9-0d3c3e14e020
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2005118144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.2005118144
Directory	/workspace/43.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/43.flash_ctrl_disable.1266606987
Short name	T386
Test name
Test status
Simulation time	10304600 ps
CPU time	20.49 seconds
Started	Jul 23 04:47:45 PM PDT 24
Finished	Jul 23 04:48:07 PM PDT 24
Peak memory	273832 kb
Host	smart-0bd1a72e-c229-4bbb-b66d-7cb9d9d50d1f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266606987 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_disable.1266606987
Directory	/workspace/43.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/43.flash_ctrl_hw_sec_otp.3666295321
Short name	T1057
Test name
Test status
Simulation time	2285271000 ps
CPU time	164.19 seconds
Started	Jul 23 04:47:45 PM PDT 24
Finished	Jul 23 04:50:31 PM PDT 24
Peak memory	262588 kb
Host	smart-ff6d7a2a-335d-43a9-baef-7e315e38f0c6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666295321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_ hw_sec_otp.3666295321
Directory	/workspace/43.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/43.flash_ctrl_otp_reset.3645274867
Short name	T173
Test name
Test status
Simulation time	37811200 ps
CPU time	131.03 seconds
Started	Jul 23 04:47:37 PM PDT 24
Finished	Jul 23 04:49:49 PM PDT 24
Peak memory	260264 kb
Host	smart-8c00c5b3-2feb-4456-b3e8-3b56e3fa1d11
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645274867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o tp_reset.3645274867
Directory	/workspace/43.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/43.flash_ctrl_sec_info_access.1440565168
Short name	T415
Test name
Test status
Simulation time	3786044200 ps
CPU time	67.41 seconds
Started	Jul 23 04:47:39 PM PDT 24
Finished	Jul 23 04:48:48 PM PDT 24
Peak memory	263572 kb
Host	smart-4cf2cdac-762a-4554-9c37-e03be8028bc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1440565168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.1440565168
Directory	/workspace/43.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/43.flash_ctrl_smoke.1534384878
Short name	T770
Test name
Test status
Simulation time	82389600 ps
CPU time	75.92 seconds
Started	Jul 23 04:47:41 PM PDT 24
Finished	Jul 23 04:48:58 PM PDT 24
Peak memory	276736 kb
Host	smart-9b260002-6d24-4736-a48b-6d22c19480ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1534384878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.1534384878
Directory	/workspace/43.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.flash_ctrl_alert_test.885507062
Short name	T998
Test name
Test status
Simulation time	28230200 ps
CPU time	13.67 seconds
Started	Jul 23 04:47:39 PM PDT 24
Finished	Jul 23 04:47:54 PM PDT 24
Peak memory	265324 kb
Host	smart-9b7744c6-0c77-49b4-a6fb-875d19424c73
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885507062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.885507062
Directory	/workspace/44.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.flash_ctrl_connect.2743735159
Short name	T496
Test name
Test status
Simulation time	60983500 ps
CPU time	13.42 seconds
Started	Jul 23 04:47:45 PM PDT 24
Finished	Jul 23 04:47:59 PM PDT 24
Peak memory	284588 kb
Host	smart-e6b7848e-3d70-4c3b-9ff4-6d5e7c9774c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2743735159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.2743735159
Directory	/workspace/44.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/44.flash_ctrl_disable.2146539015
Short name	T388
Test name
Test status
Simulation time	26784200 ps
CPU time	20.38 seconds
Started	Jul 23 04:47:39 PM PDT 24
Finished	Jul 23 04:48:01 PM PDT 24
Peak memory	273496 kb
Host	smart-01d5743c-5577-44c8-88ab-aafd8a943587
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146539015 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_disable.2146539015
Directory	/workspace/44.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/44.flash_ctrl_hw_sec_otp.2819605469
Short name	T451
Test name
Test status
Simulation time	13684137500 ps
CPU time	93.56 seconds
Started	Jul 23 04:47:37 PM PDT 24
Finished	Jul 23 04:49:12 PM PDT 24
Peak memory	260908 kb
Host	smart-2dfb5be2-f383-401d-8efa-1476a31e81df
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819605469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ hw_sec_otp.2819605469
Directory	/workspace/44.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/44.flash_ctrl_otp_reset.3560671253
Short name	T183
Test name
Test status
Simulation time	155226400 ps
CPU time	131.63 seconds
Started	Jul 23 04:47:39 PM PDT 24
Finished	Jul 23 04:49:52 PM PDT 24
Peak memory	260260 kb
Host	smart-e8afc0d0-efeb-4926-9c69-f7d0057769d5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560671253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o tp_reset.3560671253
Directory	/workspace/44.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/44.flash_ctrl_sec_info_access.3238978953
Short name	T478
Test name
Test status
Simulation time	4709592000 ps
CPU time	67.73 seconds
Started	Jul 23 04:47:45 PM PDT 24
Finished	Jul 23 04:48:55 PM PDT 24
Peak memory	265000 kb
Host	smart-7ee7a7da-3006-4614-bd67-80c66ccf938f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3238978953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.3238978953
Directory	/workspace/44.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/45.flash_ctrl_alert_test.1162439675
Short name	T953
Test name
Test status
Simulation time	137671900 ps
CPU time	13.87 seconds
Started	Jul 23 04:47:56 PM PDT 24
Finished	Jul 23 04:48:12 PM PDT 24
Peak memory	265316 kb
Host	smart-762afb13-63e9-4f93-86f1-75f94c562603
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162439675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test. 1162439675
Directory	/workspace/45.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.flash_ctrl_connect.2599629388
Short name	T1052
Test name
Test status
Simulation time	29235200 ps
CPU time	16.11 seconds
Started	Jul 23 04:47:54 PM PDT 24
Finished	Jul 23 04:48:13 PM PDT 24
Peak memory	274844 kb
Host	smart-c1323261-3835-4e6e-b3cc-29bba6b5d810
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599629388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.2599629388
Directory	/workspace/45.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/45.flash_ctrl_disable.3447203584
Short name	T997
Test name
Test status
Simulation time	12475300 ps
CPU time	22.1 seconds
Started	Jul 23 04:47:54 PM PDT 24
Finished	Jul 23 04:48:18 PM PDT 24
Peak memory	273612 kb
Host	smart-a240b41d-609d-47c1-a5ee-113f23ccf8a3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447203584 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_disable.3447203584
Directory	/workspace/45.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/45.flash_ctrl_hw_sec_otp.3827687230
Short name	T746
Test name
Test status
Simulation time	2760241400 ps
CPU time	69.13 seconds
Started	Jul 23 04:47:40 PM PDT 24
Finished	Jul 23 04:48:50 PM PDT 24
Peak memory	263092 kb
Host	smart-2e7365c1-678c-4d71-a699-50706fd6e5a9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827687230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_ hw_sec_otp.3827687230
Directory	/workspace/45.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/45.flash_ctrl_otp_reset.1654456606
Short name	T737
Test name
Test status
Simulation time	69763500 ps
CPU time	129.54 seconds
Started	Jul 23 04:47:38 PM PDT 24
Finished	Jul 23 04:49:49 PM PDT 24
Peak memory	264236 kb
Host	smart-02904997-03da-4bd1-b458-df927127b633
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654456606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o tp_reset.1654456606
Directory	/workspace/45.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/45.flash_ctrl_sec_info_access.3527440197
Short name	T263
Test name
Test status
Simulation time	7416628900 ps
CPU time	79.85 seconds
Started	Jul 23 04:47:55 PM PDT 24
Finished	Jul 23 04:49:18 PM PDT 24
Peak memory	263108 kb
Host	smart-6c68c495-753b-42e6-8fe4-1134e8c33f18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3527440197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.3527440197
Directory	/workspace/45.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/45.flash_ctrl_smoke.2706837318
Short name	T581
Test name
Test status
Simulation time	31062000 ps
CPU time	126.78 seconds
Started	Jul 23 04:47:45 PM PDT 24
Finished	Jul 23 04:49:54 PM PDT 24
Peak memory	277800 kb
Host	smart-c19f5835-c74f-4c6c-b620-69f465dd8ff6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2706837318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.2706837318
Directory	/workspace/45.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.flash_ctrl_alert_test.2378327367
Short name	T929
Test name
Test status
Simulation time	40573800 ps
CPU time	13.99 seconds
Started	Jul 23 04:47:54 PM PDT 24
Finished	Jul 23 04:48:10 PM PDT 24
Peak memory	258320 kb
Host	smart-29b39c4e-4993-4b0d-aadd-ed992cc6de45
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378327367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test. 2378327367
Directory	/workspace/46.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.flash_ctrl_connect.2177459740
Short name	T732
Test name
Test status
Simulation time	22639900 ps
CPU time	16.48 seconds
Started	Jul 23 04:48:03 PM PDT 24
Finished	Jul 23 04:48:26 PM PDT 24
Peak memory	275048 kb
Host	smart-1138eb9d-bf4e-4656-ba22-8e7c346c3385
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2177459740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.2177459740
Directory	/workspace/46.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/46.flash_ctrl_hw_sec_otp.2910182748
Short name	T337
Test name
Test status
Simulation time	2873266800 ps
CPU time	121.67 seconds
Started	Jul 23 04:47:54 PM PDT 24
Finished	Jul 23 04:49:58 PM PDT 24
Peak memory	262872 kb
Host	smart-31111e92-053f-48c9-ada7-ed15d9f25743
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910182748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_ hw_sec_otp.2910182748
Directory	/workspace/46.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/46.flash_ctrl_otp_reset.2440197192
Short name	T936
Test name
Test status
Simulation time	41388800 ps
CPU time	135.14 seconds
Started	Jul 23 04:47:54 PM PDT 24
Finished	Jul 23 04:50:12 PM PDT 24
Peak memory	261128 kb
Host	smart-d1190a44-65cb-4ae5-8fe1-454216110785
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440197192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o tp_reset.2440197192
Directory	/workspace/46.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/46.flash_ctrl_sec_info_access.149852423
Short name	T477
Test name
Test status
Simulation time	530066600 ps
CPU time	66.53 seconds
Started	Jul 23 04:47:53 PM PDT 24
Finished	Jul 23 04:49:02 PM PDT 24
Peak memory	263032 kb
Host	smart-b8d051f7-4a59-478e-9efa-bbfc976272a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=149852423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.149852423
Directory	/workspace/46.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/46.flash_ctrl_smoke.1582899443
Short name	T757
Test name
Test status
Simulation time	38459900 ps
CPU time	193.09 seconds
Started	Jul 23 04:47:53 PM PDT 24
Finished	Jul 23 04:51:08 PM PDT 24
Peak memory	277900 kb
Host	smart-0b0abec0-49db-4d0b-a07b-e7a370c3918f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582899443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.1582899443
Directory	/workspace/46.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.flash_ctrl_alert_test.2192215143
Short name	T453
Test name
Test status
Simulation time	133181000 ps
CPU time	14.41 seconds
Started	Jul 23 04:48:00 PM PDT 24
Finished	Jul 23 04:48:17 PM PDT 24
Peak memory	265544 kb
Host	smart-7da73132-aaca-4047-ad8a-9f31755ab8e5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192215143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test. 2192215143
Directory	/workspace/47.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.flash_ctrl_connect.2251648106
Short name	T673
Test name
Test status
Simulation time	27801900 ps
CPU time	15.83 seconds
Started	Jul 23 04:47:54 PM PDT 24
Finished	Jul 23 04:48:12 PM PDT 24
Peak memory	274836 kb
Host	smart-e51f7495-961b-41c0-98dc-cbfe507a23fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2251648106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.2251648106
Directory	/workspace/47.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/47.flash_ctrl_disable.3077775789
Short name	T97
Test name
Test status
Simulation time	17365700 ps
CPU time	21.81 seconds
Started	Jul 23 04:47:56 PM PDT 24
Finished	Jul 23 04:48:20 PM PDT 24
Peak memory	273572 kb
Host	smart-2e33a580-a54d-45c5-aa2d-f23bd8b6d3c5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077775789 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_disable.3077775789
Directory	/workspace/47.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/47.flash_ctrl_hw_sec_otp.3916748809
Short name	T641
Test name
Test status
Simulation time	1451427100 ps
CPU time	127.28 seconds
Started	Jul 23 04:47:54 PM PDT 24
Finished	Jul 23 04:50:04 PM PDT 24
Peak memory	263108 kb
Host	smart-0d4d3b1c-b820-44d7-92e9-97db7edc62ef
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916748809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_ hw_sec_otp.3916748809
Directory	/workspace/47.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/47.flash_ctrl_otp_reset.563872697
Short name	T106
Test name
Test status
Simulation time	42225300 ps
CPU time	109.86 seconds
Started	Jul 23 04:47:54 PM PDT 24
Finished	Jul 23 04:49:45 PM PDT 24
Peak memory	260304 kb
Host	smart-29575cd9-9856-4279-90c8-880627af1c53
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563872697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_ot p_reset.563872697
Directory	/workspace/47.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/47.flash_ctrl_sec_info_access.3642927905
Short name	T555
Test name
Test status
Simulation time	5740803000 ps
CPU time	65.77 seconds
Started	Jul 23 04:47:53 PM PDT 24
Finished	Jul 23 04:49:00 PM PDT 24
Peak memory	263816 kb
Host	smart-822baf5c-eaa9-4f8b-a356-69a1679e9d85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3642927905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.3642927905
Directory	/workspace/47.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/47.flash_ctrl_smoke.3333193149
Short name	T1026
Test name
Test status
Simulation time	83375100 ps
CPU time	145.2 seconds
Started	Jul 23 04:47:54 PM PDT 24
Finished	Jul 23 04:50:22 PM PDT 24
Peak memory	278396 kb
Host	smart-7fbca807-84db-4ef9-ba26-0f7ce8f5b85c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3333193149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3333193149
Directory	/workspace/47.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.flash_ctrl_alert_test.1297499273
Short name	T544
Test name
Test status
Simulation time	219360900 ps
CPU time	13.54 seconds
Started	Jul 23 04:47:56 PM PDT 24
Finished	Jul 23 04:48:13 PM PDT 24
Peak memory	265232 kb
Host	smart-e1ac4aa5-58d0-42b8-bd7d-0c9f5012c22d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297499273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test. 1297499273
Directory	/workspace/48.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.flash_ctrl_connect.3685189120
Short name	T826
Test name
Test status
Simulation time	16177200 ps
CPU time	15.96 seconds
Started	Jul 23 04:47:55 PM PDT 24
Finished	Jul 23 04:48:14 PM PDT 24
Peak memory	274820 kb
Host	smart-77605ea6-9cc5-4b04-a66c-772c58e45eb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685189120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.3685189120
Directory	/workspace/48.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/48.flash_ctrl_disable.3314037651
Short name	T68
Test name
Test status
Simulation time	37498500 ps
CPU time	20.56 seconds
Started	Jul 23 04:47:54 PM PDT 24
Finished	Jul 23 04:48:17 PM PDT 24
Peak memory	273476 kb
Host	smart-c136b3db-991a-4997-9177-d2a77fe871ec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314037651 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_disable.3314037651
Directory	/workspace/48.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/48.flash_ctrl_hw_sec_otp.2457619392
Short name	T916
Test name
Test status
Simulation time	2894902900 ps
CPU time	98.64 seconds
Started	Jul 23 04:47:53 PM PDT 24
Finished	Jul 23 04:49:33 PM PDT 24
Peak memory	261084 kb
Host	smart-51cd14ad-0014-479f-b7f8-188dc0585b1a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457619392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_ hw_sec_otp.2457619392
Directory	/workspace/48.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/48.flash_ctrl_otp_reset.3142061341
Short name	T909
Test name
Test status
Simulation time	132323200 ps
CPU time	108.87 seconds
Started	Jul 23 04:47:54 PM PDT 24
Finished	Jul 23 04:49:45 PM PDT 24
Peak memory	260268 kb
Host	smart-78893057-3963-402d-94b7-de3c2207f03d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142061341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o tp_reset.3142061341
Directory	/workspace/48.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/48.flash_ctrl_smoke.79159053
Short name	T65
Test name
Test status
Simulation time	703961200 ps
CPU time	235.88 seconds
Started	Jul 23 04:47:56 PM PDT 24
Finished	Jul 23 04:51:55 PM PDT 24
Peak memory	281580 kb
Host	smart-753a79c1-8218-4137-a022-9abe5bbb57d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=79159053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.79159053
Directory	/workspace/48.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.flash_ctrl_alert_test.102001975
Short name	T530
Test name
Test status
Simulation time	65238400 ps
CPU time	13.83 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:48:25 PM PDT 24
Peak memory	265248 kb
Host	smart-23082ed3-db33-4e8e-8097-3b1f5259f7bc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102001975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.102001975
Directory	/workspace/49.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.flash_ctrl_connect.1613205069
Short name	T1062
Test name
Test status
Simulation time	67143400 ps
CPU time	13.46 seconds
Started	Jul 23 04:48:01 PM PDT 24
Finished	Jul 23 04:48:17 PM PDT 24
Peak memory	284412 kb
Host	smart-0d8603fb-a39d-465d-8eca-0966d078185d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1613205069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.1613205069
Directory	/workspace/49.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/49.flash_ctrl_disable.2594153632
Short name	T402
Test name
Test status
Simulation time	48417700 ps
CPU time	21.9 seconds
Started	Jul 23 04:48:05 PM PDT 24
Finished	Jul 23 04:48:34 PM PDT 24
Peak memory	273512 kb
Host	smart-f8aca03c-050c-4fdd-ad78-2fec555106fa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594153632 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_disable.2594153632
Directory	/workspace/49.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/49.flash_ctrl_hw_sec_otp.621940275
Short name	T950
Test name
Test status
Simulation time	42112051600 ps
CPU time	101.24 seconds
Started	Jul 23 04:48:01 PM PDT 24
Finished	Jul 23 04:49:45 PM PDT 24
Peak memory	260788 kb
Host	smart-5dd0ec05-10d5-45fe-b373-d1d38db22b24
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621940275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_h w_sec_otp.621940275
Directory	/workspace/49.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/49.flash_ctrl_otp_reset.3901780127
Short name	T658
Test name
Test status
Simulation time	267256000 ps
CPU time	111.67 seconds
Started	Jul 23 04:48:00 PM PDT 24
Finished	Jul 23 04:49:55 PM PDT 24
Peak memory	260908 kb
Host	smart-29d063e7-3c53-4fc6-9463-4f6dd89e76ad
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901780127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o tp_reset.3901780127
Directory	/workspace/49.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/49.flash_ctrl_sec_info_access.102600135
Short name	T21
Test name
Test status
Simulation time	2001861800 ps
CPU time	79.69 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:49:30 PM PDT 24
Peak memory	261000 kb
Host	smart-8e6d655b-137d-4491-9b16-134badf70472
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102600135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.102600135
Directory	/workspace/49.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/49.flash_ctrl_smoke.2146685719
Short name	T750
Test name
Test status
Simulation time	444846300 ps
CPU time	171.76 seconds
Started	Jul 23 04:47:55 PM PDT 24
Finished	Jul 23 04:50:49 PM PDT 24
Peak memory	269352 kb
Host	smart-c86e1769-d471-4986-bad3-7d6857a98acd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2146685719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.2146685719
Directory	/workspace/49.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_alert_test.3261683855
Short name	T852
Test name
Test status
Simulation time	104184700 ps
CPU time	13.7 seconds
Started	Jul 23 04:44:39 PM PDT 24
Finished	Jul 23 04:44:57 PM PDT 24
Peak memory	258116 kb
Host	smart-90472302-3180-45ee-95d6-949d2d316cfd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261683855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.3 261683855
Directory	/workspace/5.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.flash_ctrl_connect.3818547768
Short name	T1079
Test name
Test status
Simulation time	50800600 ps
CPU time	13.22 seconds
Started	Jul 23 04:44:34 PM PDT 24
Finished	Jul 23 04:44:53 PM PDT 24
Peak memory	274788 kb
Host	smart-21b363dc-95a6-47b2-8ce2-d0b4b0d42a94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3818547768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.3818547768
Directory	/workspace/5.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/5.flash_ctrl_disable.2002055153
Short name	T1097
Test name
Test status
Simulation time	43667500 ps
CPU time	21.47 seconds
Started	Jul 23 04:44:33 PM PDT 24
Finished	Jul 23 04:44:58 PM PDT 24
Peak memory	273632 kb
Host	smart-00eabba5-fa82-4d74-b71c-4751ed805d98
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002055153 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_disable.2002055153
Directory	/workspace/5.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_mp.802204685
Short name	T319
Test name
Test status
Simulation time	11941131800 ps
CPU time	2318.22 seconds
Started	Jul 23 04:44:34 PM PDT 24
Finished	Jul 23 05:23:18 PM PDT 24
Peak memory	262856 kb
Host	smart-5433930d-e1c6-4455-a2bb-baed82cacfc5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=802204685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.802204685
Directory	/workspace/5.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_prog_win.3090974410
Short name	T58
Test name
Test status
Simulation time	1107489700 ps
CPU time	953.56 seconds
Started	Jul 23 04:44:32 PM PDT 24
Finished	Jul 23 05:00:29 PM PDT 24
Peak memory	272836 kb
Host	smart-dc13baae-a814-4a99-ac08-9deaf83dfd38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3090974410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.3090974410
Directory	/workspace/5.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/5.flash_ctrl_fetch_code.788125442
Short name	T889
Test name
Test status
Simulation time	1586982600 ps
CPU time	27.62 seconds
Started	Jul 23 04:44:33 PM PDT 24
Finished	Jul 23 04:45:04 PM PDT 24
Peak memory	263564 kb
Host	smart-56d836e4-d09c-4e98-ba72-6b19a0047a8a
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788125442 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.788125442
Directory	/workspace/5.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.1286311801
Short name	T315
Test name
Test status
Simulation time	10012836400 ps
CPU time	295.67 seconds
Started	Jul 23 04:44:36 PM PDT 24
Finished	Jul 23 04:49:38 PM PDT 24
Peak memory	315028 kb
Host	smart-ca73f2d6-0f16-412b-8c4b-47d9e6314bce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286311801 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.1286311801
Directory	/workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.1268519591
Short name	T666
Test name
Test status
Simulation time	17129400 ps
CPU time	13.48 seconds
Started	Jul 23 04:44:33 PM PDT 24
Finished	Jul 23 04:44:51 PM PDT 24
Peak memory	258588 kb
Host	smart-5cfafc5e-e790-45ab-ba2a-8d036cec01f6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268519591 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.1268519591
Directory	/workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_rma_reset.2298288475
Short name	T344
Test name
Test status
Simulation time	160191805500 ps
CPU time	974.67 seconds
Started	Jul 23 04:44:31 PM PDT 24
Finished	Jul 23 05:00:49 PM PDT 24
Peak memory	261108 kb
Host	smart-e728b674-6cd0-4503-9b01-fe30314bb4e6
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298288475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 5.flash_ctrl_hw_rma_reset.2298288475
Directory	/workspace/5.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_sec_otp.2660418220
Short name	T680
Test name
Test status
Simulation time	2892837300 ps
CPU time	83.52 seconds
Started	Jul 23 04:44:36 PM PDT 24
Finished	Jul 23 04:46:06 PM PDT 24
Peak memory	263160 kb
Host	smart-01e54dcc-fab7-4a45-b4f9-d1ba6325c54e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660418220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h w_sec_otp.2660418220
Directory	/workspace/5.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd.2119379114
Short name	T924
Test name
Test status
Simulation time	5680181400 ps
CPU time	131.52 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 04:46:52 PM PDT 24
Peak memory	295472 kb
Host	smart-5de7d108-1c51-4a09-9665-690a1a791dfa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119379114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas h_ctrl_intr_rd.2119379114
Directory	/workspace/5.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.218588568
Short name	T499
Test name
Test status
Simulation time	12672297100 ps
CPU time	294.99 seconds
Started	Jul 23 04:44:36 PM PDT 24
Finished	Jul 23 04:49:36 PM PDT 24
Peak memory	290992 kb
Host	smart-55c93b0a-0812-48f9-a08b-2c9d7a54442a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218588568 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.218588568
Directory	/workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_wr.63517922
Short name	T983
Test name
Test status
Simulation time	2829814100 ps
CPU time	64.71 seconds
Started	Jul 23 04:44:36 PM PDT 24
Finished	Jul 23 04:45:46 PM PDT 24
Peak memory	260064 kb
Host	smart-a1838493-d8ce-420d-8f21-97d3b007420c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63517922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +U VM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 5.flash_ctrl_intr_wr.63517922
Directory	/workspace/5.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.4257009288
Short name	T28
Test name
Test status
Simulation time	154538087100 ps
CPU time	296.3 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 04:49:37 PM PDT 24
Peak memory	265336 kb
Host	smart-28ff0636-1b75-4e15-bffa-74cf8e213622
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425 7009288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.4257009288
Directory	/workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/5.flash_ctrl_invalid_op.3003204817
Short name	T1115
Test name
Test status
Simulation time	2185297600 ps
CPU time	69.36 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 04:45:50 PM PDT 24
Peak memory	263672 kb
Host	smart-d80bbae3-82de-4617-9c7c-92db4dbc7507
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003204817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.3003204817
Directory	/workspace/5.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/5.flash_ctrl_lcmgr_intg.962469864
Short name	T815
Test name
Test status
Simulation time	45641000 ps
CPU time	13.4 seconds
Started	Jul 23 04:44:36 PM PDT 24
Finished	Jul 23 04:44:56 PM PDT 24
Peak memory	264892 kb
Host	smart-2c2971d7-34c8-4f92-b834-73e53b5d81a7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962469864 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.962469864
Directory	/workspace/5.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/5.flash_ctrl_mp_regions.3876991311
Short name	T860
Test name
Test status
Simulation time	8650503000 ps
CPU time	670.41 seconds
Started	Jul 23 04:44:36 PM PDT 24
Finished	Jul 23 04:55:52 PM PDT 24
Peak memory	274688 kb
Host	smart-d2a38477-0f77-4742-b2db-91e79e002e79
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876991311 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.3876991311
Directory	/workspace/5.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/5.flash_ctrl_otp_reset.2088696722
Short name	T180
Test name
Test status
Simulation time	42006200 ps
CPU time	110.48 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 04:46:31 PM PDT 24
Peak memory	260220 kb
Host	smart-bba591c1-cf7d-4cd5-9b03-795464ae912c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088696722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot p_reset.2088696722
Directory	/workspace/5.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_phy_arb.3043693361
Short name	T167
Test name
Test status
Simulation time	780218200 ps
CPU time	195.11 seconds
Started	Jul 23 04:44:36 PM PDT 24
Finished	Jul 23 04:47:57 PM PDT 24
Peak memory	263176 kb
Host	smart-dfba5753-779c-45db-91ac-d0fd6038ac8d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3043693361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.3043693361
Directory	/workspace/5.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/5.flash_ctrl_prog_reset.3233062229
Short name	T802
Test name
Test status
Simulation time	9176159700 ps
CPU time	112.55 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 04:46:33 PM PDT 24
Peak memory	260540 kb
Host	smart-1b01fb8a-471a-46f2-9cd2-50b6a4ffcb11
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233062229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.flash_ctrl_prog_reset.3233062229
Directory	/workspace/5.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rand_ops.1404224799
Short name	T689
Test name
Test status
Simulation time	157214900 ps
CPU time	780.16 seconds
Started	Jul 23 04:44:36 PM PDT 24
Finished	Jul 23 04:57:42 PM PDT 24
Peak memory	283820 kb
Host	smart-7a4450ae-4665-493e-aae7-5dcbf922a66d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1404224799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.1404224799
Directory	/workspace/5.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro.3808649105
Short name	T884
Test name
Test status
Simulation time	3694634700 ps
CPU time	129.17 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 04:46:50 PM PDT 24
Peak memory	296844 kb
Host	smart-30312ce2-21af-407c-94a1-99f56dca59bd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808649105 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 5.flash_ctrl_ro.3808649105
Directory	/workspace/5.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_derr.3698878501
Short name	T992
Test name
Test status
Simulation time	655086600 ps
CPU time	168.42 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 04:47:29 PM PDT 24
Peak memory	281824 kb
Host	smart-818f0dc6-0465-40ae-a3cd-d1f3c0120c61
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3698878501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.3698878501
Directory	/workspace/5.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_serr.3654892793
Short name	T905
Test name
Test status
Simulation time	6432701300 ps
CPU time	128.3 seconds
Started	Jul 23 04:44:32 PM PDT 24
Finished	Jul 23 04:46:44 PM PDT 24
Peak memory	281672 kb
Host	smart-8b9d2b97-0ced-45ee-baef-4c9fa55d1c46
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654892793 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.3654892793
Directory	/workspace/5.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw.1455464252
Short name	T549
Test name
Test status
Simulation time	6425812800 ps
CPU time	664.7 seconds
Started	Jul 23 04:44:34 PM PDT 24
Finished	Jul 23 04:55:43 PM PDT 24
Peak memory	309560 kb
Host	smart-035d13c6-8717-4df5-95c5-db8812998414
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455464252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.flash_ctrl_rw.1455464252
Directory	/workspace/5.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_derr.2894127996
Short name	T1101
Test name
Test status
Simulation time	8558978800 ps
CPU time	589.01 seconds
Started	Jul 23 04:44:36 PM PDT 24
Finished	Jul 23 04:54:31 PM PDT 24
Peak memory	335840 kb
Host	smart-4c1fe129-55bc-4b0d-a61c-52e67c115338
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894127996 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 5.flash_ctrl_rw_derr.2894127996
Directory	/workspace/5.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_evict.2240197826
Short name	T474
Test name
Test status
Simulation time	44802100 ps
CPU time	31.26 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 04:45:12 PM PDT 24
Peak memory	275888 kb
Host	smart-6201744b-0278-4a65-a21a-6da2a8c6db60
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240197826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_rw_evict.2240197826
Directory	/workspace/5.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.670040032
Short name	T1085
Test name
Test status
Simulation time	43784100 ps
CPU time	31.27 seconds
Started	Jul 23 04:44:31 PM PDT 24
Finished	Jul 23 04:45:06 PM PDT 24
Peak memory	275532 kb
Host	smart-a1f4805f-2fb1-432e-b1f5-e75f961a027b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670040032 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.670040032
Directory	/workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/5.flash_ctrl_sec_info_access.1293964122
Short name	T252
Test name
Test status
Simulation time	7177320500 ps
CPU time	68.4 seconds
Started	Jul 23 04:44:31 PM PDT 24
Finished	Jul 23 04:45:43 PM PDT 24
Peak memory	263848 kb
Host	smart-13e2851c-a731-4438-ae1a-ccebf88ba17b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293964122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.1293964122
Directory	/workspace/5.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/5.flash_ctrl_smoke.2902948902
Short name	T647
Test name
Test status
Simulation time	32117100 ps
CPU time	95.4 seconds
Started	Jul 23 04:44:32 PM PDT 24
Finished	Jul 23 04:46:11 PM PDT 24
Peak memory	276392 kb
Host	smart-4a50915f-cfaa-4a56-8c46-d905556370b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902948902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2902948902
Directory	/workspace/5.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_wo.1711992586
Short name	T1043
Test name
Test status
Simulation time	2470342500 ps
CPU time	207.31 seconds
Started	Jul 23 04:44:34 PM PDT 24
Finished	Jul 23 04:48:06 PM PDT 24
Peak memory	261144 kb
Host	smart-b096be12-8229-4683-9000-65e404935dab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711992586 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.flash_ctrl_wo.1711992586
Directory	/workspace/5.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/50.flash_ctrl_connect.1627562373
Short name	T768
Test name
Test status
Simulation time	22839600 ps
CPU time	13.85 seconds
Started	Jul 23 04:48:01 PM PDT 24
Finished	Jul 23 04:48:18 PM PDT 24
Peak memory	275024 kb
Host	smart-ae653303-db11-4330-823f-8b5b7f57e686
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1627562373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.1627562373
Directory	/workspace/50.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/50.flash_ctrl_otp_reset.1157313337
Short name	T669
Test name
Test status
Simulation time	70387100 ps
CPU time	111.74 seconds
Started	Jul 23 04:48:01 PM PDT 24
Finished	Jul 23 04:49:56 PM PDT 24
Peak memory	265276 kb
Host	smart-c9c4a674-3ad8-4663-a9b3-4fc34d48286b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157313337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o tp_reset.1157313337
Directory	/workspace/50.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/51.flash_ctrl_connect.2823938073
Short name	T644
Test name
Test status
Simulation time	13056800 ps
CPU time	13.24 seconds
Started	Jul 23 04:48:06 PM PDT 24
Finished	Jul 23 04:48:27 PM PDT 24
Peak memory	274932 kb
Host	smart-8819440c-66e5-493d-81b2-a3859382a157
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2823938073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.2823938073
Directory	/workspace/51.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/51.flash_ctrl_otp_reset.2019444933
Short name	T184
Test name
Test status
Simulation time	72990800 ps
CPU time	130.74 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:50:22 PM PDT 24
Peak memory	259960 kb
Host	smart-0699fb1a-cdce-426d-b637-ff14f51d6e79
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019444933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o tp_reset.2019444933
Directory	/workspace/51.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/52.flash_ctrl_connect.343868969
Short name	T792
Test name
Test status
Simulation time	94657100 ps
CPU time	15.78 seconds
Started	Jul 23 04:48:00 PM PDT 24
Finished	Jul 23 04:48:18 PM PDT 24
Peak memory	274952 kb
Host	smart-5b9294e0-b2ad-406e-82f8-a6b3a8dc607e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=343868969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.343868969
Directory	/workspace/52.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/52.flash_ctrl_otp_reset.2097978829
Short name	T867
Test name
Test status
Simulation time	41571800 ps
CPU time	110.84 seconds
Started	Jul 23 04:48:06 PM PDT 24
Finished	Jul 23 04:50:05 PM PDT 24
Peak memory	259940 kb
Host	smart-dff2875f-61b3-4617-94f3-da01107032b7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097978829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o tp_reset.2097978829
Directory	/workspace/52.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/53.flash_ctrl_connect.1964660402
Short name	T677
Test name
Test status
Simulation time	198552700 ps
CPU time	16.26 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:48:27 PM PDT 24
Peak memory	274912 kb
Host	smart-bc0b223c-9194-4afe-8f6f-aedec73de087
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1964660402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.1964660402
Directory	/workspace/53.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/54.flash_ctrl_connect.3924678421
Short name	T896
Test name
Test status
Simulation time	47439600 ps
CPU time	15.56 seconds
Started	Jul 23 04:48:05 PM PDT 24
Finished	Jul 23 04:48:28 PM PDT 24
Peak memory	274912 kb
Host	smart-5bb07f24-c621-4ad0-bce8-5fb1e2b01776
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3924678421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.3924678421
Directory	/workspace/54.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/54.flash_ctrl_otp_reset.1521811810
Short name	T1000
Test name
Test status
Simulation time	75015700 ps
CPU time	109.7 seconds
Started	Jul 23 04:48:02 PM PDT 24
Finished	Jul 23 04:49:55 PM PDT 24
Peak memory	260304 kb
Host	smart-a473c047-980b-42af-836b-731969c3bef1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521811810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o tp_reset.1521811810
Directory	/workspace/54.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/55.flash_ctrl_connect.2159449089
Short name	T452
Test name
Test status
Simulation time	40567900 ps
CPU time	13.64 seconds
Started	Jul 23 04:48:05 PM PDT 24
Finished	Jul 23 04:48:26 PM PDT 24
Peak memory	284484 kb
Host	smart-20a58763-5766-4d7b-8ca2-61934b316349
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2159449089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.2159449089
Directory	/workspace/55.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/55.flash_ctrl_otp_reset.2221953919
Short name	T1040
Test name
Test status
Simulation time	136230200 ps
CPU time	131.09 seconds
Started	Jul 23 04:48:01 PM PDT 24
Finished	Jul 23 04:50:15 PM PDT 24
Peak memory	260100 kb
Host	smart-f88f4cc3-6a15-448c-a579-6d76ec2c85c3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221953919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o tp_reset.2221953919
Directory	/workspace/55.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/56.flash_ctrl_connect.138068120
Short name	T608
Test name
Test status
Simulation time	25404300 ps
CPU time	16.03 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:48:27 PM PDT 24
Peak memory	284372 kb
Host	smart-ebf0aca7-1deb-451f-b2f2-1188c860e8a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=138068120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.138068120
Directory	/workspace/56.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/56.flash_ctrl_otp_reset.3571262567
Short name	T982
Test name
Test status
Simulation time	43258700 ps
CPU time	111.03 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:50:01 PM PDT 24
Peak memory	260184 kb
Host	smart-de7b0c61-2e95-4c80-b6e9-e0254593801f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571262567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o tp_reset.3571262567
Directory	/workspace/56.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/57.flash_ctrl_connect.1809101220
Short name	T1045
Test name
Test status
Simulation time	12992100 ps
CPU time	15.56 seconds
Started	Jul 23 04:48:03 PM PDT 24
Finished	Jul 23 04:48:23 PM PDT 24
Peak memory	274956 kb
Host	smart-b7dde414-dcfb-4913-ad28-d6c598322dda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809101220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.1809101220
Directory	/workspace/57.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/57.flash_ctrl_otp_reset.675491487
Short name	T927
Test name
Test status
Simulation time	142088800 ps
CPU time	129.8 seconds
Started	Jul 23 04:48:02 PM PDT 24
Finished	Jul 23 04:50:17 PM PDT 24
Peak memory	261208 kb
Host	smart-ac42ac67-5b5a-4a0f-88ca-d5ba57f32ddf
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675491487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_ot p_reset.675491487
Directory	/workspace/57.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/58.flash_ctrl_connect.1978129655
Short name	T668
Test name
Test status
Simulation time	13336900 ps
CPU time	15.88 seconds
Started	Jul 23 04:48:02 PM PDT 24
Finished	Jul 23 04:48:22 PM PDT 24
Peak memory	284412 kb
Host	smart-c95985a2-ac5e-414b-8098-51a10503fbbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978129655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.1978129655
Directory	/workspace/58.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/58.flash_ctrl_otp_reset.3055264166
Short name	T187
Test name
Test status
Simulation time	42469800 ps
CPU time	133.11 seconds
Started	Jul 23 04:48:02 PM PDT 24
Finished	Jul 23 04:50:19 PM PDT 24
Peak memory	259944 kb
Host	smart-2cd4fc37-5f0e-485a-9e8f-6856e6fd7cb9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055264166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o tp_reset.3055264166
Directory	/workspace/58.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/59.flash_ctrl_otp_reset.456187197
Short name	T1059
Test name
Test status
Simulation time	148398300 ps
CPU time	130.84 seconds
Started	Jul 23 04:48:03 PM PDT 24
Finished	Jul 23 04:50:19 PM PDT 24
Peak memory	261192 kb
Host	smart-bebbc2f4-b711-472b-a60c-f9ecfcd4b1d4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456187197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_ot p_reset.456187197
Directory	/workspace/59.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_alert_test.252007040
Short name	T1082
Test name
Test status
Simulation time	77094600 ps
CPU time	14.12 seconds
Started	Jul 23 04:44:47 PM PDT 24
Finished	Jul 23 04:45:04 PM PDT 24
Peak memory	265260 kb
Host	smart-35542eba-714b-4236-ae4a-00184e2d35ea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252007040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.252007040
Directory	/workspace/6.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.flash_ctrl_connect.2828571107
Short name	T114
Test name
Test status
Simulation time	27948700 ps
CPU time	16.05 seconds
Started	Jul 23 04:44:39 PM PDT 24
Finished	Jul 23 04:45:00 PM PDT 24
Peak memory	274816 kb
Host	smart-75dc86fc-15b8-4224-a8ed-3c5149255eb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2828571107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.2828571107
Directory	/workspace/6.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/6.flash_ctrl_disable.272449104
Short name	T98
Test name
Test status
Simulation time	15162000 ps
CPU time	22.3 seconds
Started	Jul 23 04:44:39 PM PDT 24
Finished	Jul 23 04:45:06 PM PDT 24
Peak memory	273728 kb
Host	smart-1d602f60-8873-478f-94f6-640d5152b696
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272449104 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_disable.272449104
Directory	/workspace/6.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_mp.1718254378
Short name	T250
Test name
Test status
Simulation time	9117427600 ps
CPU time	2182.95 seconds
Started	Jul 23 04:44:41 PM PDT 24
Finished	Jul 23 05:21:08 PM PDT 24
Peak memory	262952 kb
Host	smart-ded9c6a7-a7dc-4147-a7de-b0a01b3b4490
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1718254378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.1718254378
Directory	/workspace/6.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_prog_win.2428056031
Short name	T734
Test name
Test status
Simulation time	936257100 ps
CPU time	853.91 seconds
Started	Jul 23 04:44:41 PM PDT 24
Finished	Jul 23 04:58:59 PM PDT 24
Peak memory	273456 kb
Host	smart-3e285695-387c-4130-9d13-bc04156b2d5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428056031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.2428056031
Directory	/workspace/6.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/6.flash_ctrl_fetch_code.1396768130
Short name	T540
Test name
Test status
Simulation time	595791400 ps
CPU time	30.48 seconds
Started	Jul 23 04:44:33 PM PDT 24
Finished	Jul 23 04:45:08 PM PDT 24
Peak memory	262480 kb
Host	smart-8bce6038-55f7-410e-a7a5-850da0db0930
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396768130 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.1396768130
Directory	/workspace/6.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.346689342
Short name	T887
Test name
Test status
Simulation time	10034675700 ps
CPU time	95.31 seconds
Started	Jul 23 04:44:39 PM PDT 24
Finished	Jul 23 04:46:19 PM PDT 24
Peak memory	265444 kb
Host	smart-beefe2e6-c2be-4a72-bf2a-0c4b8fee2c04
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346689342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.346689342
Directory	/workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.3275021385
Short name	T660
Test name
Test status
Simulation time	16650200 ps
CPU time	13.31 seconds
Started	Jul 23 04:44:39 PM PDT 24
Finished	Jul 23 04:44:57 PM PDT 24
Peak memory	260144 kb
Host	smart-a95e6004-3715-4358-af48-6e6d502ab660
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275021385 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.3275021385
Directory	/workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_rma_reset.2896956828
Short name	T198
Test name
Test status
Simulation time	80138807700 ps
CPU time	833.68 seconds
Started	Jul 23 04:44:39 PM PDT 24
Finished	Jul 23 04:58:37 PM PDT 24
Peak memory	264380 kb
Host	smart-6a2bec0e-fd01-4a3d-8025-a1bceb84fea1
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896956828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.flash_ctrl_hw_rma_reset.2896956828
Directory	/workspace/6.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_sec_otp.3760086289
Short name	T894
Test name
Test status
Simulation time	5316401600 ps
CPU time	205.6 seconds
Started	Jul 23 04:44:39 PM PDT 24
Finished	Jul 23 04:48:09 PM PDT 24
Peak memory	260908 kb
Host	smart-1bf892e6-d297-4ef6-ac1b-a70874a7d993
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760086289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h w_sec_otp.3760086289
Directory	/workspace/6.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd.1289813074
Short name	T493
Test name
Test status
Simulation time	6110988900 ps
CPU time	224.48 seconds
Started	Jul 23 04:44:40 PM PDT 24
Finished	Jul 23 04:48:28 PM PDT 24
Peak memory	284532 kb
Host	smart-2e19694a-cb6d-4d65-b2f6-d51cc045c59c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289813074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_intr_rd.1289813074
Directory	/workspace/6.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3756999777
Short name	T367
Test name
Test status
Simulation time	24385189300 ps
CPU time	141.58 seconds
Started	Jul 23 04:44:41 PM PDT 24
Finished	Jul 23 04:47:07 PM PDT 24
Peak memory	285452 kb
Host	smart-3a3c1ff0-80f5-4107-9442-d52575bcdf09
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756999777 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.3756999777
Directory	/workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr.2894981807
Short name	T758
Test name
Test status
Simulation time	3841348400 ps
CPU time	64.7 seconds
Started	Jul 23 04:44:40 PM PDT 24
Finished	Jul 23 04:45:49 PM PDT 24
Peak memory	260516 kb
Host	smart-9d172280-b7ee-4870-8229-aba8385afd8f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894981807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.flash_ctrl_intr_wr.2894981807
Directory	/workspace/6.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2445956735
Short name	T780
Test name
Test status
Simulation time	84769244500 ps
CPU time	179.08 seconds
Started	Jul 23 04:44:42 PM PDT 24
Finished	Jul 23 04:47:44 PM PDT 24
Peak memory	265264 kb
Host	smart-366c52c8-ffa0-4a8e-8047-337a82b26023
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244 5956735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.2445956735
Directory	/workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_invalid_op.633270541
Short name	T566
Test name
Test status
Simulation time	1710365400 ps
CPU time	66.27 seconds
Started	Jul 23 04:44:40 PM PDT 24
Finished	Jul 23 04:45:50 PM PDT 24
Peak memory	260592 kb
Host	smart-22560478-4ba1-4a6f-9667-68fac319aad2
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633270541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.633270541
Directory	/workspace/6.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/6.flash_ctrl_mp_regions.2520506449
Short name	T151
Test name
Test status
Simulation time	70636190400 ps
CPU time	346.55 seconds
Started	Jul 23 04:44:39 PM PDT 24
Finished	Jul 23 04:50:30 PM PDT 24
Peak memory	274992 kb
Host	smart-ce29cb8f-fe0e-4fde-a4ff-c15c656cb984
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520506449 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.2520506449
Directory	/workspace/6.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/6.flash_ctrl_phy_arb.2273642606
Short name	T67
Test name
Test status
Simulation time	1510973900 ps
CPU time	471.85 seconds
Started	Jul 23 04:44:34 PM PDT 24
Finished	Jul 23 04:52:32 PM PDT 24
Peak memory	263084 kb
Host	smart-e02fa4fb-32e1-4000-80d3-877c36959e9a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2273642606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.2273642606
Directory	/workspace/6.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/6.flash_ctrl_prog_reset.2295856449
Short name	T1055
Test name
Test status
Simulation time	67730400 ps
CPU time	13.45 seconds
Started	Jul 23 04:44:42 PM PDT 24
Finished	Jul 23 04:44:59 PM PDT 24
Peak memory	259108 kb
Host	smart-29efa942-b0bf-422e-aa6f-4d236b10df39
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295856449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.flash_ctrl_prog_reset.2295856449
Directory	/workspace/6.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rand_ops.768234854
Short name	T808
Test name
Test status
Simulation time	982888900 ps
CPU time	1200.59 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 05:04:41 PM PDT 24
Peak memory	291524 kb
Host	smart-352dba55-ed8b-4094-8d79-acbbcfa6b512
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768234854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.768234854
Directory	/workspace/6.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/6.flash_ctrl_re_evict.810550306
Short name	T1100
Test name
Test status
Simulation time	68545100 ps
CPU time	35.15 seconds
Started	Jul 23 04:44:41 PM PDT 24
Finished	Jul 23 04:45:20 PM PDT 24
Peak memory	275580 kb
Host	smart-c8cc6af7-452f-422e-8b48-444c5763f247
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810550306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_re_evict.810550306
Directory	/workspace/6.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro.3476513483
Short name	T741
Test name
Test status
Simulation time	1093822300 ps
CPU time	106.33 seconds
Started	Jul 23 04:44:40 PM PDT 24
Finished	Jul 23 04:46:31 PM PDT 24
Peak memory	291392 kb
Host	smart-e1b131a2-37ec-4f2c-81b6-e02ec7e0e28a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476513483 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 6.flash_ctrl_ro.3476513483
Directory	/workspace/6.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_serr.50126542
Short name	T899
Test name
Test status
Simulation time	650932900 ps
CPU time	134.23 seconds
Started	Jul 23 04:44:41 PM PDT 24
Finished	Jul 23 04:46:59 PM PDT 24
Peak memory	281716 kb
Host	smart-3bba3a4e-4bee-4341-bc37-b69bfb0d8a04
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50126542 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.50126542
Directory	/workspace/6.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.3956238732
Short name	T592
Test name
Test status
Simulation time	96540500 ps
CPU time	30.86 seconds
Started	Jul 23 04:44:38 PM PDT 24
Finished	Jul 23 04:45:14 PM PDT 24
Peak memory	268492 kb
Host	smart-ef1f523a-1290-47d1-86ed-db354fd91fe8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956238732 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.3956238732
Directory	/workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_serr.3896463797
Short name	T694
Test name
Test status
Simulation time	22121378600 ps
CPU time	603.11 seconds
Started	Jul 23 04:44:41 PM PDT 24
Finished	Jul 23 04:54:48 PM PDT 24
Peak memory	320668 kb
Host	smart-858c7952-e48f-4d1e-b140-cf0111f069b8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896463797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s err.3896463797
Directory	/workspace/6.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_sec_info_access.3637229870
Short name	T417
Test name
Test status
Simulation time	6912422200 ps
CPU time	95.45 seconds
Started	Jul 23 04:44:39 PM PDT 24
Finished	Jul 23 04:46:19 PM PDT 24
Peak memory	265064 kb
Host	smart-45634f0d-9ff9-4c9d-a4d5-af9b83e4ceab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3637229870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.3637229870
Directory	/workspace/6.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/6.flash_ctrl_smoke.3760465144
Short name	T957
Test name
Test status
Simulation time	336724400 ps
CPU time	149.63 seconds
Started	Jul 23 04:44:35 PM PDT 24
Finished	Jul 23 04:47:10 PM PDT 24
Peak memory	278292 kb
Host	smart-3c54960e-2474-4265-8f29-33b09cfd8658
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3760465144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.3760465144
Directory	/workspace/6.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.flash_ctrl_wo.3757346686
Short name	T120
Test name
Test status
Simulation time	30435363900 ps
CPU time	168.08 seconds
Started	Jul 23 04:44:40 PM PDT 24
Finished	Jul 23 04:47:32 PM PDT 24
Peak memory	259420 kb
Host	smart-a5ff8d5b-f4b3-4d04-b217-ffc8620e6893
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757346686 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.flash_ctrl_wo.3757346686
Directory	/workspace/6.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/60.flash_ctrl_connect.1714494279
Short name	T1084
Test name
Test status
Simulation time	52568100 ps
CPU time	15.77 seconds
Started	Jul 23 04:48:02 PM PDT 24
Finished	Jul 23 04:48:22 PM PDT 24
Peak memory	275020 kb
Host	smart-c7bbb0a1-506b-4cbf-9f57-2e3e10ee3b5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1714494279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.1714494279
Directory	/workspace/60.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/60.flash_ctrl_otp_reset.1848058422
Short name	T174
Test name
Test status
Simulation time	69438500 ps
CPU time	131.25 seconds
Started	Jul 23 04:48:03 PM PDT 24
Finished	Jul 23 04:50:19 PM PDT 24
Peak memory	260084 kb
Host	smart-8b4b4638-45d5-41f1-8584-a0b348bccf61
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848058422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o tp_reset.1848058422
Directory	/workspace/60.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/61.flash_ctrl_connect.249297407
Short name	T807
Test name
Test status
Simulation time	25082500 ps
CPU time	13.3 seconds
Started	Jul 23 04:48:05 PM PDT 24
Finished	Jul 23 04:48:26 PM PDT 24
Peak memory	274816 kb
Host	smart-5a71f706-1475-4e06-9c11-8398a1ef0ac7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=249297407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.249297407
Directory	/workspace/61.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/61.flash_ctrl_otp_reset.423852236
Short name	T1064
Test name
Test status
Simulation time	47596000 ps
CPU time	130.03 seconds
Started	Jul 23 04:48:05 PM PDT 24
Finished	Jul 23 04:50:24 PM PDT 24
Peak memory	265224 kb
Host	smart-e94a4529-87c9-4e4b-bb48-6c21d641aa9b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423852236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_ot p_reset.423852236
Directory	/workspace/61.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/62.flash_ctrl_connect.68653350
Short name	T548
Test name
Test status
Simulation time	16321400 ps
CPU time	13.46 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:48:24 PM PDT 24
Peak memory	284348 kb
Host	smart-0e0b1148-b905-4e28-8ad0-ca2a44d568a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68653350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.68653350
Directory	/workspace/62.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/62.flash_ctrl_otp_reset.547754967
Short name	T506
Test name
Test status
Simulation time	77186900 ps
CPU time	131.36 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:50:22 PM PDT 24
Peak memory	261204 kb
Host	smart-6d7203c5-0c38-4193-89f6-59aacb7313ea
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547754967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_ot p_reset.547754967
Directory	/workspace/62.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/63.flash_ctrl_connect.3304228506
Short name	T593
Test name
Test status
Simulation time	17027000 ps
CPU time	13.8 seconds
Started	Jul 23 04:48:02 PM PDT 24
Finished	Jul 23 04:48:20 PM PDT 24
Peak memory	275024 kb
Host	smart-d9562d6c-ba8d-4c36-a70e-f307503c2721
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3304228506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.3304228506
Directory	/workspace/63.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/63.flash_ctrl_otp_reset.546230277
Short name	T872
Test name
Test status
Simulation time	38913500 ps
CPU time	129.15 seconds
Started	Jul 23 04:48:01 PM PDT 24
Finished	Jul 23 04:50:13 PM PDT 24
Peak memory	265332 kb
Host	smart-e00fcc43-efba-4765-a681-188819665106
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546230277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_ot p_reset.546230277
Directory	/workspace/63.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/64.flash_ctrl_connect.3924757938
Short name	T449
Test name
Test status
Simulation time	14211300 ps
CPU time	16.26 seconds
Started	Jul 23 04:48:01 PM PDT 24
Finished	Jul 23 04:48:20 PM PDT 24
Peak memory	274964 kb
Host	smart-83d5dd84-29e9-4192-b82d-e97f7875487f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3924757938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.3924757938
Directory	/workspace/64.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/64.flash_ctrl_otp_reset.674211184
Short name	T1021
Test name
Test status
Simulation time	75982400 ps
CPU time	131.24 seconds
Started	Jul 23 04:48:03 PM PDT 24
Finished	Jul 23 04:50:20 PM PDT 24
Peak memory	262816 kb
Host	smart-6860d4ac-54f4-4a08-9d8b-d00d9dff63ae
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674211184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_ot p_reset.674211184
Directory	/workspace/64.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/65.flash_ctrl_connect.185254259
Short name	T1046
Test name
Test status
Simulation time	24885200 ps
CPU time	16.47 seconds
Started	Jul 23 04:48:05 PM PDT 24
Finished	Jul 23 04:48:28 PM PDT 24
Peak memory	284320 kb
Host	smart-d2787a27-1e35-49fb-b4f4-f14555bc54c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=185254259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.185254259
Directory	/workspace/65.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/65.flash_ctrl_otp_reset.3797714949
Short name	T840
Test name
Test status
Simulation time	40943300 ps
CPU time	110.4 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:50:02 PM PDT 24
Peak memory	263756 kb
Host	smart-39fbaf44-5bd1-49a0-ba42-9691de263963
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797714949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o tp_reset.3797714949
Directory	/workspace/65.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/66.flash_ctrl_connect.514806499
Short name	T754
Test name
Test status
Simulation time	51197100 ps
CPU time	13.42 seconds
Started	Jul 23 04:48:01 PM PDT 24
Finished	Jul 23 04:48:17 PM PDT 24
Peak memory	274864 kb
Host	smart-a7054acf-8695-47c1-9bb4-9381e264555a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=514806499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.514806499
Directory	/workspace/66.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/66.flash_ctrl_otp_reset.38964693
Short name	T456
Test name
Test status
Simulation time	78271500 ps
CPU time	130.88 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:50:21 PM PDT 24
Peak memory	260340 kb
Host	smart-1aa9ecba-5b25-460c-a18e-c6238e7b7ef3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38964693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_otp _reset.38964693
Directory	/workspace/66.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/67.flash_ctrl_connect.1823890339
Short name	T577
Test name
Test status
Simulation time	13724500 ps
CPU time	15.53 seconds
Started	Jul 23 04:48:05 PM PDT 24
Finished	Jul 23 04:48:28 PM PDT 24
Peak memory	284444 kb
Host	smart-da7105a6-0c7c-4900-8e79-c1f068a9c69e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1823890339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.1823890339
Directory	/workspace/67.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/67.flash_ctrl_otp_reset.4244015060
Short name	T343
Test name
Test status
Simulation time	132188400 ps
CPU time	109.59 seconds
Started	Jul 23 04:48:05 PM PDT 24
Finished	Jul 23 04:50:03 PM PDT 24
Peak memory	260220 kb
Host	smart-b4032a77-a4cc-4d4e-bbde-4ba04e2f7e66
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244015060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o tp_reset.4244015060
Directory	/workspace/67.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/68.flash_ctrl_connect.3691938423
Short name	T626
Test name
Test status
Simulation time	18461000 ps
CPU time	15.85 seconds
Started	Jul 23 04:48:03 PM PDT 24
Finished	Jul 23 04:48:24 PM PDT 24
Peak memory	274836 kb
Host	smart-090a6bf6-616b-4eda-9ace-2314225123de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691938423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.3691938423
Directory	/workspace/68.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/68.flash_ctrl_otp_reset.3914821063
Short name	T672
Test name
Test status
Simulation time	37458600 ps
CPU time	133.73 seconds
Started	Jul 23 04:48:05 PM PDT 24
Finished	Jul 23 04:50:26 PM PDT 24
Peak memory	260244 kb
Host	smart-878988e6-42dc-4ed6-8511-350911b65541
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914821063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o tp_reset.3914821063
Directory	/workspace/68.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/69.flash_ctrl_connect.2333203672
Short name	T444
Test name
Test status
Simulation time	114998800 ps
CPU time	13.31 seconds
Started	Jul 23 04:48:03 PM PDT 24
Finished	Jul 23 04:48:21 PM PDT 24
Peak memory	284360 kb
Host	smart-b826c3be-2251-479d-8df7-236e826c784d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2333203672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.2333203672
Directory	/workspace/69.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/69.flash_ctrl_otp_reset.1719722752
Short name	T777
Test name
Test status
Simulation time	65410700 ps
CPU time	131.55 seconds
Started	Jul 23 04:48:02 PM PDT 24
Finished	Jul 23 04:50:18 PM PDT 24
Peak memory	260104 kb
Host	smart-4a0aab22-f684-4b79-b07d-3454264701dd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719722752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o tp_reset.1719722752
Directory	/workspace/69.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_alert_test.1675052641
Short name	T844
Test name
Test status
Simulation time	115129200 ps
CPU time	13.5 seconds
Started	Jul 23 04:44:52 PM PDT 24
Finished	Jul 23 04:45:09 PM PDT 24
Peak memory	265288 kb
Host	smart-25d88e00-db6d-4ed9-8e6a-1109458065c9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675052641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.1 675052641
Directory	/workspace/7.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.flash_ctrl_connect.2094897172
Short name	T142
Test name
Test status
Simulation time	43151100 ps
CPU time	16.3 seconds
Started	Jul 23 04:44:49 PM PDT 24
Finished	Jul 23 04:45:09 PM PDT 24
Peak memory	274988 kb
Host	smart-da51d188-6d51-4a6c-b39c-dac6aa61a5a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2094897172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.2094897172
Directory	/workspace/7.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/7.flash_ctrl_disable.1185526595
Short name	T970
Test name
Test status
Simulation time	81134800 ps
CPU time	20.44 seconds
Started	Jul 23 04:44:49 PM PDT 24
Finished	Jul 23 04:45:13 PM PDT 24
Peak memory	273740 kb
Host	smart-37b7fb21-3e28-42ec-aa00-d8bc99e67504
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185526595 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_disable.1185526595
Directory	/workspace/7.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_mp.3775783987
Short name	T1076
Test name
Test status
Simulation time	6258183100 ps
CPU time	2182.35 seconds
Started	Jul 23 04:44:49 PM PDT 24
Finished	Jul 23 05:21:15 PM PDT 24
Peak memory	265236 kb
Host	smart-9bbf4b3c-bd1d-466a-b92b-0b253d6d3f1c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3775783987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.3775783987
Directory	/workspace/7.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_prog_win.1062812328
Short name	T1088
Test name
Test status
Simulation time	2633435200 ps
CPU time	698.26 seconds
Started	Jul 23 04:44:52 PM PDT 24
Finished	Jul 23 04:56:34 PM PDT 24
Peak memory	265028 kb
Host	smart-0a1cedc6-0571-4032-8b2f-0dfa3ca061b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1062812328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.1062812328
Directory	/workspace/7.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/7.flash_ctrl_fetch_code.564088042
Short name	T41
Test name
Test status
Simulation time	391240500 ps
CPU time	22.18 seconds
Started	Jul 23 04:44:50 PM PDT 24
Finished	Jul 23 04:45:16 PM PDT 24
Peak memory	262604 kb
Host	smart-cf8111e8-9c04-46ca-a569-aa34829191d4
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564088042 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.564088042
Directory	/workspace/7.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.100745190
Short name	T313
Test name
Test status
Simulation time	10040556600 ps
CPU time	54.87 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 04:45:46 PM PDT 24
Peak memory	268860 kb
Host	smart-12e74985-e952-4977-953b-82bc0d450e74
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100745190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.100745190
Directory	/workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.381219393
Short name	T1050
Test name
Test status
Simulation time	15747600 ps
CPU time	13.39 seconds
Started	Jul 23 04:44:49 PM PDT 24
Finished	Jul 23 04:45:07 PM PDT 24
Peak memory	258580 kb
Host	smart-8b943a8b-5092-4807-98b0-9088c469d7c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381219393 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.381219393
Directory	/workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_rma_reset.440890925
Short name	T197
Test name
Test status
Simulation time	90155714300 ps
CPU time	964.02 seconds
Started	Jul 23 04:44:47 PM PDT 24
Finished	Jul 23 05:00:53 PM PDT 24
Peak memory	260864 kb
Host	smart-5956af15-4616-42f7-8b4d-f248116e7984
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440890925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.flash_ctrl_hw_rma_reset.440890925
Directory	/workspace/7.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1763021015
Short name	T95
Test name
Test status
Simulation time	13758298000 ps
CPU time	137.38 seconds
Started	Jul 23 04:44:52 PM PDT 24
Finished	Jul 23 04:47:13 PM PDT 24
Peak memory	259956 kb
Host	smart-e0036995-eb71-46fb-bb31-1bef30e63d4e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763021015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h w_sec_otp.1763021015
Directory	/workspace/7.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.86996548
Short name	T471
Test name
Test status
Simulation time	25144880300 ps
CPU time	128.57 seconds
Started	Jul 23 04:44:49 PM PDT 24
Finished	Jul 23 04:47:01 PM PDT 24
Peak memory	292556 kb
Host	smart-38a40a78-5898-4236-8830-3f69e308f64d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86996548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.86996548
Directory	/workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr.1610724530
Short name	T827
Test name
Test status
Simulation time	2112790100 ps
CPU time	68.62 seconds
Started	Jul 23 04:44:50 PM PDT 24
Finished	Jul 23 04:46:03 PM PDT 24
Peak memory	260672 kb
Host	smart-e0ae5e15-0a2c-4197-8e4c-8d1b6b9952b1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610724530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.flash_ctrl_intr_wr.1610724530
Directory	/workspace/7.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.3200851760
Short name	T562
Test name
Test status
Simulation time	22213228900 ps
CPU time	175.52 seconds
Started	Jul 23 04:44:49 PM PDT 24
Finished	Jul 23 04:47:49 PM PDT 24
Peak memory	265324 kb
Host	smart-edd91c5b-918f-429a-a289-f451062f357b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320 0851760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.3200851760
Directory	/workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/7.flash_ctrl_invalid_op.769798456
Short name	T134
Test name
Test status
Simulation time	8087503000 ps
CPU time	64.74 seconds
Started	Jul 23 04:44:50 PM PDT 24
Finished	Jul 23 04:45:59 PM PDT 24
Peak memory	262660 kb
Host	smart-f75e12a9-360b-4a44-a30f-e42590a7ac58
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769798456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.769798456
Directory	/workspace/7.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/7.flash_ctrl_lcmgr_intg.3649817139
Short name	T776
Test name
Test status
Simulation time	47610400 ps
CPU time	13.29 seconds
Started	Jul 23 04:44:49 PM PDT 24
Finished	Jul 23 04:45:07 PM PDT 24
Peak memory	259944 kb
Host	smart-8f53c3a3-806c-401f-8c63-89e0ece8e50f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649817139 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.3649817139
Directory	/workspace/7.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/7.flash_ctrl_mp_regions.582390949
Short name	T879
Test name
Test status
Simulation time	78180535100 ps
CPU time	1187.13 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 05:04:39 PM PDT 24
Peak memory	274824 kb
Host	smart-9237e047-5382-4144-907c-4a7d0838795d
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582390949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.582390949
Directory	/workspace/7.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/7.flash_ctrl_otp_reset.597584196
Short name	T781
Test name
Test status
Simulation time	391460200 ps
CPU time	110.19 seconds
Started	Jul 23 04:44:47 PM PDT 24
Finished	Jul 23 04:46:39 PM PDT 24
Peak memory	261228 kb
Host	smart-9e975e44-f7c0-4407-93e9-f519fe68f012
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597584196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp _reset.597584196
Directory	/workspace/7.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_phy_arb.1199745590
Short name	T1094
Test name
Test status
Simulation time	1443843800 ps
CPU time	283.74 seconds
Started	Jul 23 04:44:52 PM PDT 24
Finished	Jul 23 04:49:40 PM PDT 24
Peak memory	263112 kb
Host	smart-6ad3eab8-4dcc-4c04-bb2f-e0eb410fb5c5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1199745590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.1199745590
Directory	/workspace/7.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/7.flash_ctrl_prog_reset.2984692985
Short name	T956
Test name
Test status
Simulation time	57207400 ps
CPU time	13.51 seconds
Started	Jul 23 04:44:49 PM PDT 24
Finished	Jul 23 04:45:06 PM PDT 24
Peak memory	259096 kb
Host	smart-fe84654f-a156-4349-99fb-b9d3f564fdeb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984692985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.flash_ctrl_prog_reset.2984692985
Directory	/workspace/7.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rand_ops.749755497
Short name	T865
Test name
Test status
Simulation time	117013600 ps
CPU time	697.84 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 04:56:29 PM PDT 24
Peak memory	285644 kb
Host	smart-0799eabc-fc86-4a9b-a8ac-2dc05409d80c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=749755497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.749755497
Directory	/workspace/7.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/7.flash_ctrl_re_evict.3446107077
Short name	T604
Test name
Test status
Simulation time	69061500 ps
CPU time	34.64 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 04:45:25 PM PDT 24
Peak memory	273560 kb
Host	smart-c5b2e466-e9b5-40f6-b32a-2af547061812
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446107077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_re_evict.3446107077
Directory	/workspace/7.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro.1818730771
Short name	T960
Test name
Test status
Simulation time	836108200 ps
CPU time	110.92 seconds
Started	Jul 23 04:44:50 PM PDT 24
Finished	Jul 23 04:46:45 PM PDT 24
Peak memory	289932 kb
Host	smart-57b97e97-461b-4f47-9d25-2e062fa8682e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818730771 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.flash_ctrl_ro.1818730771
Directory	/workspace/7.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro_derr.1577909177
Short name	T240
Test name
Test status
Simulation time	5097925900 ps
CPU time	129.08 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 04:47:00 PM PDT 24
Peak memory	281744 kb
Host	smart-d401da39-f08d-4ecc-a092-d499a5f95763
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1577909177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.1577909177
Directory	/workspace/7.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro_serr.1739875012
Short name	T94
Test name
Test status
Simulation time	1048124300 ps
CPU time	121.03 seconds
Started	Jul 23 04:44:50 PM PDT 24
Finished	Jul 23 04:46:55 PM PDT 24
Peak memory	281756 kb
Host	smart-fe739049-c7ca-4cfc-89ce-39f1d02f34c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739875012 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.1739875012
Directory	/workspace/7.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw.1892823491
Short name	T945
Test name
Test status
Simulation time	4533573500 ps
CPU time	516.31 seconds
Started	Jul 23 04:44:49 PM PDT 24
Finished	Jul 23 04:53:29 PM PDT 24
Peak memory	314432 kb
Host	smart-fd46f3f7-d48e-4992-9a91-b7a4842f43f0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892823491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.flash_ctrl_rw.1892823491
Directory	/workspace/7.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_derr.2593150714
Short name	T271
Test name
Test status
Simulation time	97436000300 ps
CPU time	753.54 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 04:57:24 PM PDT 24
Peak memory	347544 kb
Host	smart-1fe8a75c-f253-48f2-9164-f5113b1c3a56
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593150714 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.flash_ctrl_rw_derr.2593150714
Directory	/workspace/7.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_evict.2855550125
Short name	T225
Test name
Test status
Simulation time	75681400 ps
CPU time	29.16 seconds
Started	Jul 23 04:44:47 PM PDT 24
Finished	Jul 23 04:45:17 PM PDT 24
Peak memory	269376 kb
Host	smart-6ce5d2d2-3319-413b-a224-e3e17b600235
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855550125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_rw_evict.2855550125
Directory	/workspace/7.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.19913189
Short name	T300
Test name
Test status
Simulation time	43823700 ps
CPU time	30.54 seconds
Started	Jul 23 04:44:47 PM PDT 24
Finished	Jul 23 04:45:19 PM PDT 24
Peak memory	275668 kb
Host	smart-6f92f1d4-98d1-44cc-8980-ca9f32b3e9ee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19913189 -assert nopostproc +UVM_TESTNAME=fl ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.19913189
Directory	/workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/7.flash_ctrl_sec_info_access.1056573345
Short name	T1116
Test name
Test status
Simulation time	2297721700 ps
CPU time	75.3 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 04:46:06 PM PDT 24
Peak memory	263200 kb
Host	smart-d3c07f79-e9d8-459e-abab-c6dcd88405b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1056573345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.1056573345
Directory	/workspace/7.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/7.flash_ctrl_smoke.1187888472
Short name	T904
Test name
Test status
Simulation time	192220500 ps
CPU time	120.94 seconds
Started	Jul 23 04:44:50 PM PDT 24
Finished	Jul 23 04:46:55 PM PDT 24
Peak memory	276096 kb
Host	smart-e4ec4712-fbd1-495a-bdac-fff60bea2b72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1187888472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.1187888472
Directory	/workspace/7.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.flash_ctrl_wo.3928093157
Short name	T902
Test name
Test status
Simulation time	3984764500 ps
CPU time	141.38 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 04:47:12 PM PDT 24
Peak memory	259408 kb
Host	smart-97aeda16-dd94-4823-8a77-324c2362e5e9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928093157 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.flash_ctrl_wo.3928093157
Directory	/workspace/7.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/70.flash_ctrl_connect.4036238498
Short name	T591
Test name
Test status
Simulation time	15015800 ps
CPU time	15.48 seconds
Started	Jul 23 04:48:06 PM PDT 24
Finished	Jul 23 04:48:29 PM PDT 24
Peak memory	274888 kb
Host	smart-12dd6682-3d28-40da-a0e7-62d6ed24f0db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4036238498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.4036238498
Directory	/workspace/70.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/70.flash_ctrl_otp_reset.1272975849
Short name	T599
Test name
Test status
Simulation time	113024800 ps
CPU time	132.14 seconds
Started	Jul 23 04:48:05 PM PDT 24
Finished	Jul 23 04:50:25 PM PDT 24
Peak memory	260160 kb
Host	smart-f389de90-7a85-4abc-8451-9abcaaa382fa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272975849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o tp_reset.1272975849
Directory	/workspace/70.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/71.flash_ctrl_connect.2749474452
Short name	T618
Test name
Test status
Simulation time	53123800 ps
CPU time	15.67 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:48:27 PM PDT 24
Peak memory	275020 kb
Host	smart-2f41ed44-52eb-411e-92fe-cbde4aec6015
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2749474452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.2749474452
Directory	/workspace/71.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/71.flash_ctrl_otp_reset.4146658461
Short name	T948
Test name
Test status
Simulation time	85406600 ps
CPU time	110.06 seconds
Started	Jul 23 04:48:05 PM PDT 24
Finished	Jul 23 04:50:04 PM PDT 24
Peak memory	264216 kb
Host	smart-89ec886d-d59a-4475-948b-8874c77087ba
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146658461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o tp_reset.4146658461
Directory	/workspace/71.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/72.flash_ctrl_connect.3679246391
Short name	T476
Test name
Test status
Simulation time	26854200 ps
CPU time	16.16 seconds
Started	Jul 23 04:48:03 PM PDT 24
Finished	Jul 23 04:48:25 PM PDT 24
Peak memory	284372 kb
Host	smart-12cd4719-6555-42ac-9451-6a596abb7539
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679246391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.3679246391
Directory	/workspace/72.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/72.flash_ctrl_otp_reset.1141517162
Short name	T347
Test name
Test status
Simulation time	71850500 ps
CPU time	111.02 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:50:02 PM PDT 24
Peak memory	264372 kb
Host	smart-2dd5c0b7-15c5-4c96-8747-8fe6402c4109
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141517162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o tp_reset.1141517162
Directory	/workspace/72.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/73.flash_ctrl_connect.2871073505
Short name	T615
Test name
Test status
Simulation time	46829500 ps
CPU time	16.06 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:48:26 PM PDT 24
Peak memory	275000 kb
Host	smart-fb093dd1-10bd-4887-a73d-3c376eb44814
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2871073505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.2871073505
Directory	/workspace/73.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/73.flash_ctrl_otp_reset.1501521713
Short name	T1109
Test name
Test status
Simulation time	42505500 ps
CPU time	130.24 seconds
Started	Jul 23 04:48:05 PM PDT 24
Finished	Jul 23 04:50:23 PM PDT 24
Peak memory	260168 kb
Host	smart-5df01ddd-6282-44a6-a7ea-2c9e71a68afe
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501521713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o tp_reset.1501521713
Directory	/workspace/73.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/74.flash_ctrl_connect.217604294
Short name	T1078
Test name
Test status
Simulation time	14013600 ps
CPU time	13.29 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:48:23 PM PDT 24
Peak memory	275120 kb
Host	smart-0198af26-337b-4740-8aa7-9ed8f7221178
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=217604294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.217604294
Directory	/workspace/74.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/74.flash_ctrl_otp_reset.3881294626
Short name	T619
Test name
Test status
Simulation time	40258800 ps
CPU time	130.78 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:50:21 PM PDT 24
Peak memory	265328 kb
Host	smart-d8fa5d93-7864-4a8e-b253-ba5975dfd76e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881294626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o tp_reset.3881294626
Directory	/workspace/74.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/75.flash_ctrl_connect.2992269222
Short name	T664
Test name
Test status
Simulation time	44827200 ps
CPU time	13.32 seconds
Started	Jul 23 04:48:05 PM PDT 24
Finished	Jul 23 04:48:25 PM PDT 24
Peak memory	275024 kb
Host	smart-a6b79002-4677-40ff-b7f1-8e9b1ad44417
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2992269222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.2992269222
Directory	/workspace/75.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/75.flash_ctrl_otp_reset.2445579319
Short name	T569
Test name
Test status
Simulation time	46877200 ps
CPU time	130.34 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:50:21 PM PDT 24
Peak memory	260460 kb
Host	smart-cd2e1d0f-6b00-4f65-a59c-3fa0d69d8b47
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445579319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o tp_reset.2445579319
Directory	/workspace/75.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/76.flash_ctrl_connect.1117180422
Short name	T472
Test name
Test status
Simulation time	16446000 ps
CPU time	15.19 seconds
Started	Jul 23 04:48:01 PM PDT 24
Finished	Jul 23 04:48:20 PM PDT 24
Peak memory	274996 kb
Host	smart-523e24c9-81a2-4e6b-b171-03e32ec430dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1117180422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.1117180422
Directory	/workspace/76.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/76.flash_ctrl_otp_reset.1182645263
Short name	T771
Test name
Test status
Simulation time	65540400 ps
CPU time	132 seconds
Started	Jul 23 04:48:04 PM PDT 24
Finished	Jul 23 04:50:23 PM PDT 24
Peak memory	264620 kb
Host	smart-71c8e968-7584-4594-a646-d48172ebe813
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182645263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o tp_reset.1182645263
Directory	/workspace/76.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/77.flash_ctrl_connect.2398257221
Short name	T962
Test name
Test status
Simulation time	21535600 ps
CPU time	13.35 seconds
Started	Jul 23 04:48:12 PM PDT 24
Finished	Jul 23 04:48:31 PM PDT 24
Peak memory	275028 kb
Host	smart-8e3ab637-1c9b-466a-b284-a47ff1bb6d9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2398257221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.2398257221
Directory	/workspace/77.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/77.flash_ctrl_otp_reset.2105471025
Short name	T1041
Test name
Test status
Simulation time	356674000 ps
CPU time	127.23 seconds
Started	Jul 23 04:48:02 PM PDT 24
Finished	Jul 23 04:50:12 PM PDT 24
Peak memory	260128 kb
Host	smart-c4eaf3da-a2c6-47cf-88bd-f910987bdfaa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105471025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o tp_reset.2105471025
Directory	/workspace/77.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/78.flash_ctrl_connect.2279843670
Short name	T1086
Test name
Test status
Simulation time	71801600 ps
CPU time	15.75 seconds
Started	Jul 23 04:48:10 PM PDT 24
Finished	Jul 23 04:48:32 PM PDT 24
Peak memory	274808 kb
Host	smart-64653e6e-c868-46b9-a0be-a6fee2d49418
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279843670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.2279843670
Directory	/workspace/78.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/79.flash_ctrl_connect.291555838
Short name	T450
Test name
Test status
Simulation time	16628600 ps
CPU time	16.23 seconds
Started	Jul 23 04:48:11 PM PDT 24
Finished	Jul 23 04:48:33 PM PDT 24
Peak memory	274876 kb
Host	smart-3e76022b-1bb9-4aae-8b9a-177629f55c1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=291555838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.291555838
Directory	/workspace/79.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/79.flash_ctrl_otp_reset.2496125879
Short name	T400
Test name
Test status
Simulation time	104346600 ps
CPU time	133.64 seconds
Started	Jul 23 04:48:10 PM PDT 24
Finished	Jul 23 04:50:30 PM PDT 24
Peak memory	264880 kb
Host	smart-5ed096ac-c2c0-4e51-861a-b474b06a5dbd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496125879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o tp_reset.2496125879
Directory	/workspace/79.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_alert_test.344657282
Short name	T898
Test name
Test status
Simulation time	121889600 ps
CPU time	13.81 seconds
Started	Jul 23 04:44:56 PM PDT 24
Finished	Jul 23 04:45:13 PM PDT 24
Peak memory	265220 kb
Host	smart-23118211-927a-4647-b4d1-5d8d5cf8879e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344657282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.344657282
Directory	/workspace/8.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.flash_ctrl_connect.3908069515
Short name	T621
Test name
Test status
Simulation time	14446700 ps
CPU time	16.04 seconds
Started	Jul 23 04:44:57 PM PDT 24
Finished	Jul 23 04:45:17 PM PDT 24
Peak memory	274912 kb
Host	smart-fbd569fd-e260-46bb-83fc-70479c20106c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3908069515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.3908069515
Directory	/workspace/8.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/8.flash_ctrl_disable.3943119197
Short name	T100
Test name
Test status
Simulation time	16077000 ps
CPU time	22.11 seconds
Started	Jul 23 04:44:58 PM PDT 24
Finished	Jul 23 04:45:24 PM PDT 24
Peak memory	273644 kb
Host	smart-0b7394bf-fe41-4ec7-9325-b481c8b6d9a6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943119197 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_disable.3943119197
Directory	/workspace/8.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_mp.3002016154
Short name	T602
Test name
Test status
Simulation time	19801526200 ps
CPU time	2218.57 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 05:21:50 PM PDT 24
Peak memory	265128 kb
Host	smart-ca93f799-a7b2-44fc-b9d6-1b76150e3165
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3002016154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.3002016154
Directory	/workspace/8.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_prog_win.1619131909
Short name	T835
Test name
Test status
Simulation time	2305438200 ps
CPU time	747.58 seconds
Started	Jul 23 04:44:49 PM PDT 24
Finished	Jul 23 04:57:20 PM PDT 24
Peak memory	272840 kb
Host	smart-f5d3f7cb-a600-4f69-b519-10b01cfe2be4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619131909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.1619131909
Directory	/workspace/8.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/8.flash_ctrl_fetch_code.4194996218
Short name	T888
Test name
Test status
Simulation time	1646523200 ps
CPU time	27.85 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 04:45:20 PM PDT 24
Peak memory	262580 kb
Host	smart-eebaf609-3330-4315-8607-39086cc97e3c
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194996218 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.4194996218
Directory	/workspace/8.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.2572857052
Short name	T311
Test name
Test status
Simulation time	10032263700 ps
CPU time	54.56 seconds
Started	Jul 23 04:44:56 PM PDT 24
Finished	Jul 23 04:45:55 PM PDT 24
Peak memory	272168 kb
Host	smart-04adc09a-e694-4f10-bb74-b27f0d9a0700
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572857052 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.2572857052
Directory	/workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.594441657
Short name	T733
Test name
Test status
Simulation time	20971200 ps
CPU time	13.47 seconds
Started	Jul 23 04:44:56 PM PDT 24
Finished	Jul 23 04:45:14 PM PDT 24
Peak memory	258332 kb
Host	smart-4198c876-c2ee-4924-9fd0-0a8a6f654b2c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594441657 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.594441657
Directory	/workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_sec_otp.89469623
Short name	T96
Test name
Test status
Simulation time	4860718200 ps
CPU time	97.33 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 04:46:29 PM PDT 24
Peak memory	261048 kb
Host	smart-06c73c5d-b024-4e1e-bdf7-55e9f5d79520
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89469623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_ sec_otp.89469623
Directory	/workspace/8.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd.2372974085
Short name	T152
Test name
Test status
Simulation time	3572752500 ps
CPU time	208.18 seconds
Started	Jul 23 04:44:51 PM PDT 24
Finished	Jul 23 04:48:23 PM PDT 24
Peak memory	284740 kb
Host	smart-95f54f9d-9013-4abc-bb23-359c366ef09c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372974085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas h_ctrl_intr_rd.2372974085
Directory	/workspace/8.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.3146718837
Short name	T828
Test name
Test status
Simulation time	51484021900 ps
CPU time	288.87 seconds
Started	Jul 23 04:44:55 PM PDT 24
Finished	Jul 23 04:49:47 PM PDT 24
Peak memory	285116 kb
Host	smart-01e7fa8e-d707-408e-85aa-b88c9d515980
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146718837 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.3146718837
Directory	/workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr.4179320235
Short name	T1051
Test name
Test status
Simulation time	2890253800 ps
CPU time	63.45 seconds
Started	Jul 23 04:44:52 PM PDT 24
Finished	Jul 23 04:45:59 PM PDT 24
Peak memory	260648 kb
Host	smart-8143701c-7b70-4032-8dbe-5bed0156fd99
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179320235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.flash_ctrl_intr_wr.4179320235
Directory	/workspace/8.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.1961865515
Short name	T26
Test name
Test status
Simulation time	100263467300 ps
CPU time	199.12 seconds
Started	Jul 23 04:44:57 PM PDT 24
Finished	Jul 23 04:48:20 PM PDT 24
Peak memory	265360 kb
Host	smart-9a430cec-a6b6-427d-a4db-7ab7c94d8a7a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196 1865515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.1961865515
Directory	/workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/8.flash_ctrl_invalid_op.1935659827
Short name	T420
Test name
Test status
Simulation time	19406091100 ps
CPU time	76.11 seconds
Started	Jul 23 04:44:51 PM PDT 24
Finished	Jul 23 04:46:11 PM PDT 24
Peak memory	263544 kb
Host	smart-2b5d7ee1-a3b3-4bc8-85c0-389b07cd8e2a
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935659827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.1935659827
Directory	/workspace/8.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/8.flash_ctrl_lcmgr_intg.2665354171
Short name	T1015
Test name
Test status
Simulation time	47568000 ps
CPU time	13.69 seconds
Started	Jul 23 04:44:56 PM PDT 24
Finished	Jul 23 04:45:13 PM PDT 24
Peak memory	260892 kb
Host	smart-2e78b1e8-1b56-4abf-b737-7f193a836599
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665354171 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.2665354171
Directory	/workspace/8.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/8.flash_ctrl_mp_regions.4126794368
Short name	T772
Test name
Test status
Simulation time	11268853400 ps
CPU time	150.21 seconds
Started	Jul 23 04:44:50 PM PDT 24
Finished	Jul 23 04:47:24 PM PDT 24
Peak memory	265304 kb
Host	smart-fcce36c5-53e0-4829-88f5-49bf0d1ce100
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126794368 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.4126794368
Directory	/workspace/8.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/8.flash_ctrl_otp_reset.714059574
Short name	T567
Test name
Test status
Simulation time	107464200 ps
CPU time	110.18 seconds
Started	Jul 23 04:44:50 PM PDT 24
Finished	Jul 23 04:46:44 PM PDT 24
Peak memory	260232 kb
Host	smart-111a84e2-be4a-492e-8310-ce337403ad2e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714059574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp _reset.714059574
Directory	/workspace/8.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_phy_arb.416496330
Short name	T1071
Test name
Test status
Simulation time	5737399200 ps
CPU time	469.2 seconds
Started	Jul 23 04:44:50 PM PDT 24
Finished	Jul 23 04:52:43 PM PDT 24
Peak memory	263188 kb
Host	smart-daa5d8d8-6cc2-4254-8700-d67140f0003a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=416496330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.416496330
Directory	/workspace/8.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/8.flash_ctrl_prog_reset.2443921367
Short name	T831
Test name
Test status
Simulation time	4428176000 ps
CPU time	185.62 seconds
Started	Jul 23 04:44:56 PM PDT 24
Finished	Jul 23 04:48:05 PM PDT 24
Peak memory	260740 kb
Host	smart-d7c0fda3-0f65-4369-9ce6-6fe1c1f81c3f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443921367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.flash_ctrl_prog_reset.2443921367
Directory	/workspace/8.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rand_ops.3139419292
Short name	T510
Test name
Test status
Simulation time	24900500 ps
CPU time	55.62 seconds
Started	Jul 23 04:44:52 PM PDT 24
Finished	Jul 23 04:45:51 PM PDT 24
Peak memory	262952 kb
Host	smart-30d95de6-db3b-4233-a6ff-a45055467222
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3139419292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3139419292
Directory	/workspace/8.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/8.flash_ctrl_re_evict.3465852649
Short name	T430
Test name
Test status
Simulation time	110887900 ps
CPU time	34.3 seconds
Started	Jul 23 04:44:56 PM PDT 24
Finished	Jul 23 04:45:34 PM PDT 24
Peak memory	268412 kb
Host	smart-9118aec1-f3c1-4e4a-bbaf-ca4218076b32
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465852649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla sh_ctrl_re_evict.3465852649
Directory	/workspace/8.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_derr.2268197041
Short name	T804
Test name
Test status
Simulation time	2389947800 ps
CPU time	132.9 seconds
Started	Jul 23 04:44:47 PM PDT 24
Finished	Jul 23 04:47:01 PM PDT 24
Peak memory	281808 kb
Host	smart-6d126507-51c5-430b-8aac-20ea07c69923
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2268197041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.2268197041
Directory	/workspace/8.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_serr.3284846627
Short name	T308
Test name
Test status
Simulation time	661781600 ps
CPU time	130.77 seconds
Started	Jul 23 04:44:49 PM PDT 24
Finished	Jul 23 04:47:04 PM PDT 24
Peak memory	295292 kb
Host	smart-7094ac9c-787d-489f-85b4-05bbf8076e70
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284846627 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.3284846627
Directory	/workspace/8.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw.835915345
Short name	T1004
Test name
Test status
Simulation time	3395521100 ps
CPU time	517.09 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 04:53:29 PM PDT 24
Peak memory	318804 kb
Host	smart-b6790c96-fe5b-421d-9be9-0b3f5cdcf978
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835915345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw.835915345
Directory	/workspace/8.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_derr.2619008073
Short name	T834
Test name
Test status
Simulation time	3878704600 ps
CPU time	644.36 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 04:55:35 PM PDT 24
Peak memory	334884 kb
Host	smart-52252e4b-caa8-469e-b4ef-b8105bc9541c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619008073 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_rw_derr.2619008073
Directory	/workspace/8.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict.1372337635
Short name	T571
Test name
Test status
Simulation time	69689900 ps
CPU time	31.58 seconds
Started	Jul 23 04:45:01 PM PDT 24
Finished	Jul 23 04:45:35 PM PDT 24
Peak memory	273608 kb
Host	smart-d32545f1-7f67-4b64-9077-ace2462c5f9e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372337635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla sh_ctrl_rw_evict.1372337635
Directory	/workspace/8.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.2684230018
Short name	T597
Test name
Test status
Simulation time	154968900 ps
CPU time	29.25 seconds
Started	Jul 23 04:44:59 PM PDT 24
Finished	Jul 23 04:45:32 PM PDT 24
Peak memory	268412 kb
Host	smart-50277228-c0a6-49e5-924f-9d0968173744
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684230018 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.2684230018
Directory	/workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/8.flash_ctrl_sec_info_access.1884519126
Short name	T678
Test name
Test status
Simulation time	1332906100 ps
CPU time	63.31 seconds
Started	Jul 23 04:44:57 PM PDT 24
Finished	Jul 23 04:46:04 PM PDT 24
Peak memory	263760 kb
Host	smart-08f9ec5e-8058-4ad0-ae29-21ac8acabb15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1884519126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.1884519126
Directory	/workspace/8.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/8.flash_ctrl_smoke.3052847959
Short name	T534
Test name
Test status
Simulation time	55885100 ps
CPU time	168.57 seconds
Started	Jul 23 04:44:47 PM PDT 24
Finished	Jul 23 04:47:37 PM PDT 24
Peak memory	281636 kb
Host	smart-58a90dab-1da3-4c2f-aba4-45467dc86fd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3052847959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.3052847959
Directory	/workspace/8.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.flash_ctrl_wo.2811338315
Short name	T744
Test name
Test status
Simulation time	4981567400 ps
CPU time	179.43 seconds
Started	Jul 23 04:44:48 PM PDT 24
Finished	Jul 23 04:47:51 PM PDT 24
Peak memory	259848 kb
Host	smart-fab84337-b3ef-4d56-9d9f-078b9e709300
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811338315 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.flash_ctrl_wo.2811338315
Directory	/workspace/8.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/9.flash_ctrl_alert_test.4197406472
Short name	T917
Test name
Test status
Simulation time	74097300 ps
CPU time	13.58 seconds
Started	Jul 23 04:45:07 PM PDT 24
Finished	Jul 23 04:45:23 PM PDT 24
Peak memory	265236 kb
Host	smart-f94bc6b3-c4d0-4309-8bd2-4dc24c40153e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197406472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.4 197406472
Directory	/workspace/9.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.flash_ctrl_connect.980723635
Short name	T138
Test name
Test status
Simulation time	53775600 ps
CPU time	16.09 seconds
Started	Jul 23 04:45:06 PM PDT 24
Finished	Jul 23 04:45:23 PM PDT 24
Peak memory	274816 kb
Host	smart-d5f9378c-3c4a-48d6-82be-53b1f6a07d7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980723635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.980723635
Directory	/workspace/9.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/9.flash_ctrl_disable.2024942897
Short name	T1011
Test name
Test status
Simulation time	31989800 ps
CPU time	21.76 seconds
Started	Jul 23 04:45:06 PM PDT 24
Finished	Jul 23 04:45:30 PM PDT 24
Peak memory	273604 kb
Host	smart-83854583-1620-4547-9a27-b510943b3f78
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024942897 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_disable.2024942897
Directory	/workspace/9.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_mp.2321439019
Short name	T486
Test name
Test status
Simulation time	25589176500 ps
CPU time	2571.26 seconds
Started	Jul 23 04:45:01 PM PDT 24
Finished	Jul 23 05:27:55 PM PDT 24
Peak memory	262940 kb
Host	smart-ad18cd00-062a-42ff-9353-7550fceb66a0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2321439019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.2321439019
Directory	/workspace/9.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_prog_win.1967885585
Short name	T613
Test name
Test status
Simulation time	4362144000 ps
CPU time	959.16 seconds
Started	Jul 23 04:44:56 PM PDT 24
Finished	Jul 23 05:00:58 PM PDT 24
Peak memory	272852 kb
Host	smart-0086e5f9-abe2-48c1-b995-6082fbd0c1da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967885585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.1967885585
Directory	/workspace/9.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/9.flash_ctrl_fetch_code.2547026848
Short name	T42
Test name
Test status
Simulation time	1200536800 ps
CPU time	25.51 seconds
Started	Jul 23 04:44:57 PM PDT 24
Finished	Jul 23 04:45:27 PM PDT 24
Peak memory	262536 kb
Host	smart-fb46d088-7ade-44fa-aa54-7a8038fe13f2
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547026848 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.2547026848
Directory	/workspace/9.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.3820251282
Short name	T312
Test name
Test status
Simulation time	10018367400 ps
CPU time	88.83 seconds
Started	Jul 23 04:45:08 PM PDT 24
Finished	Jul 23 04:46:39 PM PDT 24
Peak memory	297684 kb
Host	smart-ed505234-f86f-4994-afe3-d7af622e2f88
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820251282 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.3820251282
Directory	/workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.2099537092
Short name	T682
Test name
Test status
Simulation time	47929300 ps
CPU time	13.59 seconds
Started	Jul 23 04:45:08 PM PDT 24
Finished	Jul 23 04:45:24 PM PDT 24
Peak memory	260176 kb
Host	smart-7d0cab44-1a38-460b-bb60-17702eb795d3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099537092 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.2099537092
Directory	/workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_rma_reset.2611746890
Short name	T762
Test name
Test status
Simulation time	230216858200 ps
CPU time	1136.83 seconds
Started	Jul 23 04:44:57 PM PDT 24
Finished	Jul 23 05:03:58 PM PDT 24
Peak memory	261044 kb
Host	smart-8612c3ea-cdcb-4c0f-adb4-7bb03fb6a3e1
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611746890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 9.flash_ctrl_hw_rma_reset.2611746890
Directory	/workspace/9.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_sec_otp.2321698340
Short name	T265
Test name
Test status
Simulation time	1011763900 ps
CPU time	43.44 seconds
Started	Jul 23 04:44:56 PM PDT 24
Finished	Jul 23 04:45:44 PM PDT 24
Peak memory	260968 kb
Host	smart-9cbc3557-f77d-4206-bae9-85e60617581e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321698340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h w_sec_otp.2321698340
Directory	/workspace/9.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd.2837784072
Short name	T639
Test name
Test status
Simulation time	642818800 ps
CPU time	134.66 seconds
Started	Jul 23 04:44:59 PM PDT 24
Finished	Jul 23 04:47:17 PM PDT 24
Peak memory	285376 kb
Host	smart-79c7570f-e436-4ca8-8dc0-ed2553250621
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837784072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas h_ctrl_intr_rd.2837784072
Directory	/workspace/9.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.1408002439
Short name	T1036
Test name
Test status
Simulation time	5797380000 ps
CPU time	141 seconds
Started	Jul 23 04:44:57 PM PDT 24
Finished	Jul 23 04:47:22 PM PDT 24
Peak memory	291872 kb
Host	smart-3cf192fe-341c-4c62-be21-07ef0ec0c02d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408002439 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.1408002439
Directory	/workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr.3308804832
Short name	T846
Test name
Test status
Simulation time	12546950700 ps
CPU time	72.19 seconds
Started	Jul 23 04:44:59 PM PDT 24
Finished	Jul 23 04:46:15 PM PDT 24
Peak memory	260592 kb
Host	smart-2a908e2d-bd15-4363-a943-ab3d2f19b3b6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308804832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.flash_ctrl_intr_wr.3308804832
Directory	/workspace/9.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3459391457
Short name	T27
Test name
Test status
Simulation time	27239536400 ps
CPU time	188.23 seconds
Started	Jul 23 04:44:59 PM PDT 24
Finished	Jul 23 04:48:11 PM PDT 24
Peak memory	260508 kb
Host	smart-6c1c93ff-bd0c-439e-b948-491d96577306
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345 9391457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.3459391457
Directory	/workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_invalid_op.3314238449
Short name	T933
Test name
Test status
Simulation time	14829879500 ps
CPU time	62.61 seconds
Started	Jul 23 04:44:58 PM PDT 24
Finished	Jul 23 04:46:05 PM PDT 24
Peak memory	263124 kb
Host	smart-92068cc4-43f6-4838-a03e-32ff0ffcf981
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314238449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.3314238449
Directory	/workspace/9.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/9.flash_ctrl_lcmgr_intg.2275748674
Short name	T612
Test name
Test status
Simulation time	15215600 ps
CPU time	13.43 seconds
Started	Jul 23 04:45:08 PM PDT 24
Finished	Jul 23 04:45:24 PM PDT 24
Peak memory	260740 kb
Host	smart-9874c835-b179-42f8-beb6-5460f6a3e12f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275748674 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.2275748674
Directory	/workspace/9.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/9.flash_ctrl_mp_regions.15351236
Short name	T703
Test name
Test status
Simulation time	4675772700 ps
CPU time	122.87 seconds
Started	Jul 23 04:44:57 PM PDT 24
Finished	Jul 23 04:47:04 PM PDT 24
Peak memory	265220 kb
Host	smart-ebe9fb22-f046-44ff-b1ca-4ae6aca53410
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15351236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.15351236
Directory	/workspace/9.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/9.flash_ctrl_otp_reset.4184578504
Short name	T185
Test name
Test status
Simulation time	83894900 ps
CPU time	129.09 seconds
Started	Jul 23 04:44:57 PM PDT 24
Finished	Jul 23 04:47:10 PM PDT 24
Peak memory	264936 kb
Host	smart-4e8b5332-e738-4afb-a51f-dfa5be8bb436
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184578504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot p_reset.4184578504
Directory	/workspace/9.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_phy_arb.1866155603
Short name	T951
Test name
Test status
Simulation time	210034900 ps
CPU time	110.78 seconds
Started	Jul 23 04:44:56 PM PDT 24
Finished	Jul 23 04:46:50 PM PDT 24
Peak memory	263156 kb
Host	smart-fe62b6ed-bf25-4ce5-a26c-b2ef179da50e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1866155603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.1866155603
Directory	/workspace/9.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/9.flash_ctrl_prog_reset.1970950377
Short name	T392
Test name
Test status
Simulation time	38252200 ps
CPU time	13.88 seconds
Started	Jul 23 04:44:59 PM PDT 24
Finished	Jul 23 04:45:17 PM PDT 24
Peak memory	265160 kb
Host	smart-4b70ca31-ab77-4edb-b417-06e540765842
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970950377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.flash_ctrl_prog_reset.1970950377
Directory	/workspace/9.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rand_ops.2172927054
Short name	T795
Test name
Test status
Simulation time	500291200 ps
CPU time	1044.43 seconds
Started	Jul 23 04:44:56 PM PDT 24
Finished	Jul 23 05:02:24 PM PDT 24
Peak memory	286808 kb
Host	smart-b12d328b-9585-4f5d-b81d-0ca43d63063c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172927054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.2172927054
Directory	/workspace/9.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/9.flash_ctrl_re_evict.3061372129
Short name	T893
Test name
Test status
Simulation time	123801300 ps
CPU time	35.46 seconds
Started	Jul 23 04:45:06 PM PDT 24
Finished	Jul 23 04:45:42 PM PDT 24
Peak memory	275680 kb
Host	smart-bdd0c8b2-21bf-4d7b-b586-e00ace36ded9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061372129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla sh_ctrl_re_evict.3061372129
Directory	/workspace/9.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro.1389528750
Short name	T915
Test name
Test status
Simulation time	671072800 ps
CPU time	128.31 seconds
Started	Jul 23 04:44:55 PM PDT 24
Finished	Jul 23 04:47:07 PM PDT 24
Peak memory	289984 kb
Host	smart-b89cee03-cc02-44d9-9f77-37b4eae2e77a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389528750 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 9.flash_ctrl_ro.1389528750
Directory	/workspace/9.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_derr.4004315642
Short name	T814
Test name
Test status
Simulation time	2333971400 ps
CPU time	147.23 seconds
Started	Jul 23 04:44:58 PM PDT 24
Finished	Jul 23 04:47:29 PM PDT 24
Peak memory	281784 kb
Host	smart-dd4b311d-15ae-4638-a6b4-bccecbd205c4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4004315642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.4004315642
Directory	/workspace/9.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_serr.859893752
Short name	T19
Test name
Test status
Simulation time	2573265900 ps
CPU time	129.2 seconds
Started	Jul 23 04:44:57 PM PDT 24
Finished	Jul 23 04:47:10 PM PDT 24
Peak memory	295040 kb
Host	smart-c210a9c9-a9c3-40e5-88c1-2411dc27f941
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859893752 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.859893752
Directory	/workspace/9.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw.2783359152
Short name	T243
Test name
Test status
Simulation time	3894479600 ps
CPU time	641.33 seconds
Started	Jul 23 04:44:56 PM PDT 24
Finished	Jul 23 04:55:40 PM PDT 24
Peak memory	314320 kb
Host	smart-b47575b2-d637-496c-ac0d-e998fb9faeb2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783359152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.flash_ctrl_rw.2783359152
Directory	/workspace/9.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_derr.1102630935
Short name	T1105
Test name
Test status
Simulation time	3574955900 ps
CPU time	673.81 seconds
Started	Jul 23 04:45:01 PM PDT 24
Finished	Jul 23 04:56:18 PM PDT 24
Peak memory	331364 kb
Host	smart-836a93d2-4dff-4953-904a-aec1d74a72a5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102630935 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 9.flash_ctrl_rw_derr.1102630935
Directory	/workspace/9.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_evict.1908510007
Short name	T1002
Test name
Test status
Simulation time	68889400 ps
CPU time	31.63 seconds
Started	Jul 23 04:45:21 PM PDT 24
Finished	Jul 23 04:45:54 PM PDT 24
Peak memory	275724 kb
Host	smart-459b087c-f33b-4b17-b34e-e0a6031a8352
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908510007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla sh_ctrl_rw_evict.1908510007
Directory	/workspace/9.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.2290374239
Short name	T437
Test name
Test status
Simulation time	99519100 ps
CPU time	28.38 seconds
Started	Jul 23 04:45:07 PM PDT 24
Finished	Jul 23 04:45:37 PM PDT 24
Peak memory	268548 kb
Host	smart-4cfe84e3-636c-49ef-a04c-39368df1a487
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290374239 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.2290374239
Directory	/workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_serr.3557116191
Short name	T1018
Test name
Test status
Simulation time	4397538100 ps
CPU time	673.88 seconds
Started	Jul 23 04:44:57 PM PDT 24
Finished	Jul 23 04:56:15 PM PDT 24
Peak memory	320796 kb
Host	smart-f2cfa132-3765-48b2-b32a-53d022f3f1ae
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557116191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_s err.3557116191
Directory	/workspace/9.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_sec_info_access.1943606966
Short name	T408
Test name
Test status
Simulation time	27063309200 ps
CPU time	81.41 seconds
Started	Jul 23 04:45:07 PM PDT 24
Finished	Jul 23 04:46:30 PM PDT 24
Peak memory	263744 kb
Host	smart-238a1dc5-6e2d-4afd-ad13-edc1a12284b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1943606966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.1943606966
Directory	/workspace/9.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/9.flash_ctrl_smoke.2766216235
Short name	T1001
Test name
Test status
Simulation time	49749800 ps
CPU time	98.7 seconds
Started	Jul 23 04:44:57 PM PDT 24
Finished	Jul 23 04:46:39 PM PDT 24
Peak memory	277144 kb
Host	smart-e87b5ae1-a3f9-4663-8878-f9295683c624
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2766216235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.2766216235
Directory	/workspace/9.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.flash_ctrl_wo.1460093023
Short name	T1039
Test name
Test status
Simulation time	5683384800 ps
CPU time	196.94 seconds
Started	Jul 23 04:44:57 PM PDT 24
Finished	Jul 23 04:48:18 PM PDT 24
Peak memory	265564 kb
Host	smart-01fdcedb-b7bf-4381-b707-6914a57d5881
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460093023 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 9.flash_ctrl_wo.1460093023
Directory	/workspace/9.flash_ctrl_wo/latest

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