SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 26264546 | 1 | T1 | 339911 | T2 | 5494 | T3 | 7792 | |||
auto[1] | 5258253 | 1 | T1 | 18149 | T2 | 1408 | T3 | 1369 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 31522607 | 1 | T1 | 358060 | T2 | 6902 | T3 | 9161 | |||
values[1] | 18 | 1 | T205 | 2 | T206 | 1 | T262 | 1 | |||
values[2] | 2 | 1 | T342 | 1 | T343 | 1 | - | - | |||
values[3] | 86 | 1 | T203 | 1 | T205 | 7 | T206 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 31522617 | 1 | T1 | 358060 | T2 | 6902 | T3 | 9161 | |||
values[1] | 19 | 1 | T205 | 2 | T206 | 1 | T344 | 3 | |||
values[2] | 7 | 1 | T203 | 1 | T205 | 1 | T345 | 3 | |||
values[3] | 82 | 1 | T203 | 2 | T205 | 3 | T206 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 31522519 | 1 | T1 | 358060 | T2 | 6902 | T3 | 9161 | |||
auto[TlIntgErrCmd] | 98 | 1 | T203 | 2 | T205 | 8 | T206 | 8 | |||
auto[TlIntgErrData] | 88 | 1 | T203 | 6 | T205 | 6 | T206 | 8 | |||
auto[TlIntgErrBoth] | 94 | 1 | T203 | 2 | T205 | 6 | T206 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | |||
auto[1] | 3918741 | 0 | T5 | 16467 | T6 | 16807 | T21 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3918569 | 1 | T5 | 16467 | T6 | 16807 | T21 | 24 | |||
values[1] | 18 | 1 | T203 | 2 | T205 | 1 | T206 | 2 | |||
values[2] | 2 | 1 | T267 | 1 | T346 | 1 | - | - | |||
values[3] | 87 | 1 | T203 | 1 | T205 | 6 | T206 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3918562 | 1 | T5 | 16467 | T6 | 16807 | T21 | 24 | |||
values[1] | 14 | 1 | T205 | 1 | T206 | 3 | T345 | 1 | |||
values[2] | 10 | 1 | T203 | 2 | T206 | 1 | T270 | 2 | |||
values[3] | 90 | 1 | T203 | 3 | T205 | 11 | T206 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3918477 | 1 | T5 | 16467 | T6 | 16807 | T21 | 24 | |||
auto[TlIntgErrCmd] | 85 | 1 | T203 | 1 | T205 | 4 | T206 | 5 | |||
auto[TlIntgErrData] | 92 | 1 | T203 | 6 | T205 | 7 | T206 | 6 | |||
auto[TlIntgErrBoth] | 87 | 1 | T203 | 3 | T205 | 9 | T206 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 82320 | 0 | T67 | 116 | T68 | 183 | T69 | 334 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 82125 | 1 | T67 | 116 | T68 | 183 | T69 | 334 | |||
values[1] | 21 | 1 | T205 | 2 | T344 | 1 | T262 | 2 | |||
values[2] | 2 | 1 | T203 | 1 | T205 | 1 | - | - | |||
values[3] | 94 | 1 | T203 | 3 | T205 | 6 | T206 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 82138 | 1 | T67 | 116 | T68 | 183 | T69 | 334 | |||
values[1] | 18 | 1 | T203 | 1 | T345 | 1 | T344 | 1 | |||
values[2] | 10 | 1 | T205 | 2 | T262 | 1 | T347 | 1 | |||
values[3] | 87 | 1 | T203 | 4 | T205 | 7 | T206 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 82040 | 1 | T67 | 116 | T68 | 183 | T69 | 334 | |||
auto[TlIntgErrCmd] | 98 | 1 | T203 | 3 | T205 | 8 | T206 | 4 | |||
auto[TlIntgErrData] | 85 | 1 | T203 | 5 | T205 | 5 | T206 | 10 | |||
auto[TlIntgErrBoth] | 97 | 1 | T203 | 2 | T205 | 7 | T206 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |