Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23710295	1		T1	332461		T2	3854		T3	4071
full_word	7812504	1		T1	25599		T2	3048		T3	5090

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31522519	1		T1	358060		T2	6902		T3	9161
auto[TlIntgErrCmd]	98	1		T203	2		T205	8		T206	8
auto[TlIntgErrData]	88	1		T203	6		T205	6		T206	8
auto[TlIntgErrBoth]	94	1		T203	2		T205	6		T206	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27048038	1		T1	341834		T2	4669		T3	3674
auto[1]	4474761	1		T1	16226		T2	2233		T3	5487

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22992556	1		T1	331176		T2	3558		T3	3672
auto[TlIntgErrNone]	partial	auto[1]	717485	1		T1	1285		T2	296		T3	399
auto[TlIntgErrNone]	full_word	auto[0]	4055357	1		T1	10658		T2	1111		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	3757121	1		T1	14941		T2	1937		T3	5088
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T203	1		T205	3		T206	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T203	1		T205	5		T206	7
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T270	1		T267	1		T348	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T345	1		T270	2		T349	1
auto[TlIntgErrData]	partial	auto[0]	32	1		T203	4		T205	1		T206	3
auto[TlIntgErrData]	partial	auto[1]	49	1		T203	2		T205	5		T206	5
auto[TlIntgErrData]	full_word	auto[0]	4	1		T262	1		T267	1		T342	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T270	1		T267	1		T348	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1		T203	1		T205	5		T206	3
auto[TlIntgErrBoth]	partial	auto[1]	43	1		T203	1		T345	2		T344	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T205	1		T344	1		T260	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T206	1		T344	1		T346	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19400	1		T67	16		T68	60		T69	77
full_word	3899341	1		T5	16467		T6	16807		T21	24

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3918477	1		T5	16467		T6	16807		T21	24
auto[TlIntgErrCmd]	85	1		T203	1		T205	4		T206	5
auto[TlIntgErrData]	92	1		T203	6		T205	7		T206	6
auto[TlIntgErrBoth]	87	1		T203	3		T205	9		T206	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3894702	1		T5	16467		T6	16807		T21	24
auto[1]	24039	1		T67	25		T68	68		T69	122

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1252	1		T68	5		T69	5		T202	36
auto[TlIntgErrNone]	partial	auto[1]	17906	1		T67	16		T68	55		T69	72
auto[TlIntgErrNone]	full_word	auto[0]	3893351	1		T5	16467		T6	16807		T21	24
auto[TlIntgErrNone]	full_word	auto[1]	5968	1		T67	9		T68	13		T69	50
auto[TlIntgErrCmd]	partial	auto[0]	26	1		T206	1		T347	2		T260	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T205	3		T206	3		T345	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T206	1		T343	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T203	1		T205	1		T347	1
auto[TlIntgErrData]	partial	auto[0]	40	1		T203	2		T205	2		T206	3
auto[TlIntgErrData]	partial	auto[1]	45	1		T203	3		T205	5		T206	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T203	1		T206	1		T345	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T206	1		T262	1		T342	1
auto[TlIntgErrBoth]	partial	auto[0]	26	1		T203	1		T205	4		T206	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1		T203	2		T205	4		T206	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T205	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T206	1		T345	1		T349	1