Line Coverage for Module :
flash_phy_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
54 |
1 |
1 |
55 |
1 |
1 |
|
|
|
MISSING_ELSE |
61 |
1 |
1 |
62 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
116 |
|
unreachable |
117 |
|
unreachable |
118 |
|
unreachable |
Cond Coverage for Module :
flash_phy_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T5 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T5 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T5 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T23,T24,T61 |
1 | 1 | Covered | T1,T2,T5 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T5 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T23,T24,T61 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Module :
flash_phy_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T5 |
LineNo. Expression
-1-: 72 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T5 |
LineNo. Expression
-1-: 51 if (wr_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 54 if (rd_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 79 if (fin_cnt_incr)
-3-: 82 if (fin_cnt_decr)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T5 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T2,T5 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
768221548 |
6804445 |
0 |
0 |
T1 |
1434296 |
4820 |
0 |
0 |
T2 |
157046 |
984 |
0 |
0 |
T3 |
130614 |
0 |
0 |
0 |
T4 |
3356 |
0 |
0 |
0 |
T5 |
284492 |
42771 |
0 |
0 |
T6 |
363812 |
42759 |
0 |
0 |
T7 |
0 |
16775 |
0 |
0 |
T11 |
7090 |
0 |
0 |
0 |
T19 |
15598 |
174 |
0 |
0 |
T20 |
2750 |
0 |
0 |
0 |
T21 |
12356 |
186 |
0 |
0 |
T22 |
0 |
21517 |
0 |
0 |
T41 |
0 |
45741 |
0 |
0 |
T46 |
0 |
19 |
0 |
0 |
T47 |
0 |
199 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
768221548 |
766507944 |
0 |
0 |
T1 |
1434296 |
1434136 |
0 |
0 |
T2 |
157046 |
150822 |
0 |
0 |
T3 |
130614 |
130468 |
0 |
0 |
T4 |
3356 |
3086 |
0 |
0 |
T5 |
284492 |
284186 |
0 |
0 |
T6 |
363812 |
363422 |
0 |
0 |
T11 |
7090 |
5578 |
0 |
0 |
T19 |
15598 |
15436 |
0 |
0 |
T20 |
2750 |
2600 |
0 |
0 |
T21 |
12356 |
12034 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
768221548 |
6804449 |
0 |
0 |
T1 |
1434296 |
4820 |
0 |
0 |
T2 |
157046 |
984 |
0 |
0 |
T3 |
130614 |
0 |
0 |
0 |
T4 |
3356 |
0 |
0 |
0 |
T5 |
284492 |
42771 |
0 |
0 |
T6 |
363812 |
42759 |
0 |
0 |
T7 |
0 |
16775 |
0 |
0 |
T11 |
7090 |
0 |
0 |
0 |
T19 |
15598 |
174 |
0 |
0 |
T20 |
2750 |
0 |
0 |
0 |
T21 |
12356 |
186 |
0 |
0 |
T22 |
0 |
21517 |
0 |
0 |
T41 |
0 |
45741 |
0 |
0 |
T46 |
0 |
19 |
0 |
0 |
T47 |
0 |
199 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
768221549 |
16198322 |
0 |
0 |
T1 |
1434296 |
4852 |
0 |
0 |
T2 |
157046 |
2296 |
0 |
0 |
T3 |
130614 |
32 |
0 |
0 |
T4 |
3356 |
64 |
0 |
0 |
T5 |
284492 |
42835 |
0 |
0 |
T6 |
363812 |
42823 |
0 |
0 |
T7 |
0 |
8436 |
0 |
0 |
T11 |
7090 |
137 |
0 |
0 |
T19 |
15598 |
206 |
0 |
0 |
T20 |
2750 |
32 |
0 |
0 |
T21 |
12356 |
250 |
0 |
0 |
T22 |
0 |
11071 |
0 |
0 |
T41 |
0 |
22428 |
0 |
0 |
T46 |
0 |
19 |
0 |
0 |
T47 |
0 |
114 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
54 |
1 |
1 |
55 |
1 |
1 |
|
|
|
MISSING_ELSE |
61 |
1 |
1 |
62 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
116 |
|
unreachable |
117 |
|
unreachable |
118 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T5 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T5 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T5 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T23,T24,T61 |
1 | 1 | Covered | T1,T2,T5 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T5 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T23,T24,T61 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T5 |
LineNo. Expression
-1-: 72 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T5 |
LineNo. Expression
-1-: 51 if (wr_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 54 if (rd_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 79 if (fin_cnt_incr)
-3-: 82 if (fin_cnt_decr)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T5 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T2,T5 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
3480348 |
0 |
0 |
T1 |
717148 |
4669 |
0 |
0 |
T2 |
78523 |
984 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
20028 |
0 |
0 |
T6 |
181906 |
21961 |
0 |
0 |
T7 |
0 |
8339 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
98 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
133 |
0 |
0 |
T22 |
0 |
10446 |
0 |
0 |
T41 |
0 |
23313 |
0 |
0 |
T47 |
0 |
85 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
383253972 |
0 |
0 |
T1 |
717148 |
717068 |
0 |
0 |
T2 |
78523 |
75411 |
0 |
0 |
T3 |
65307 |
65234 |
0 |
0 |
T4 |
1678 |
1543 |
0 |
0 |
T5 |
142246 |
142093 |
0 |
0 |
T6 |
181906 |
181711 |
0 |
0 |
T11 |
3545 |
2789 |
0 |
0 |
T19 |
7799 |
7718 |
0 |
0 |
T20 |
1375 |
1300 |
0 |
0 |
T21 |
6178 |
6017 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
3480351 |
0 |
0 |
T1 |
717148 |
4669 |
0 |
0 |
T2 |
78523 |
984 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
20028 |
0 |
0 |
T6 |
181906 |
21961 |
0 |
0 |
T7 |
0 |
8339 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
98 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
133 |
0 |
0 |
T22 |
0 |
10446 |
0 |
0 |
T41 |
0 |
23313 |
0 |
0 |
T47 |
0 |
85 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110775 |
8416232 |
0 |
0 |
T1 |
717148 |
4701 |
0 |
0 |
T2 |
78523 |
2296 |
0 |
0 |
T3 |
65307 |
32 |
0 |
0 |
T4 |
1678 |
64 |
0 |
0 |
T5 |
142246 |
20092 |
0 |
0 |
T6 |
181906 |
22025 |
0 |
0 |
T11 |
3545 |
137 |
0 |
0 |
T19 |
7799 |
130 |
0 |
0 |
T20 |
1375 |
32 |
0 |
0 |
T21 |
6178 |
197 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
54 |
1 |
1 |
55 |
1 |
1 |
|
|
|
MISSING_ELSE |
61 |
1 |
1 |
62 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
116 |
|
unreachable |
117 |
|
unreachable |
118 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T13,T15,T110 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T23,T24,T66 |
1 | 1 | Covered | T1,T5,T6 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T23,T24,T66 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T5,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T6 |
LineNo. Expression
-1-: 72 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T6 |
LineNo. Expression
-1-: 51 if (wr_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 54 if (rd_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 79 if (fin_cnt_incr)
-3-: 82 if (fin_cnt_decr)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T5,T6 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
3324097 |
0 |
0 |
T1 |
717148 |
151 |
0 |
0 |
T2 |
78523 |
0 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
22743 |
0 |
0 |
T6 |
181906 |
20798 |
0 |
0 |
T7 |
0 |
8436 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
76 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
53 |
0 |
0 |
T22 |
0 |
11071 |
0 |
0 |
T41 |
0 |
22428 |
0 |
0 |
T46 |
0 |
19 |
0 |
0 |
T47 |
0 |
114 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
383253972 |
0 |
0 |
T1 |
717148 |
717068 |
0 |
0 |
T2 |
78523 |
75411 |
0 |
0 |
T3 |
65307 |
65234 |
0 |
0 |
T4 |
1678 |
1543 |
0 |
0 |
T5 |
142246 |
142093 |
0 |
0 |
T6 |
181906 |
181711 |
0 |
0 |
T11 |
3545 |
2789 |
0 |
0 |
T19 |
7799 |
7718 |
0 |
0 |
T20 |
1375 |
1300 |
0 |
0 |
T21 |
6178 |
6017 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
3324098 |
0 |
0 |
T1 |
717148 |
151 |
0 |
0 |
T2 |
78523 |
0 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
22743 |
0 |
0 |
T6 |
181906 |
20798 |
0 |
0 |
T7 |
0 |
8436 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
76 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
53 |
0 |
0 |
T22 |
0 |
11071 |
0 |
0 |
T41 |
0 |
22428 |
0 |
0 |
T46 |
0 |
19 |
0 |
0 |
T47 |
0 |
114 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
7782090 |
0 |
0 |
T1 |
717148 |
151 |
0 |
0 |
T2 |
78523 |
0 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
22743 |
0 |
0 |
T6 |
181906 |
20798 |
0 |
0 |
T7 |
0 |
8436 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
76 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
53 |
0 |
0 |
T22 |
0 |
11071 |
0 |
0 |
T41 |
0 |
22428 |
0 |
0 |
T46 |
0 |
19 |
0 |
0 |
T47 |
0 |
114 |
0 |
0 |