Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T21
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T21
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T21

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1536443096	1533015888	0	0
CheckNGreaterZero_A	4160	4160	0	0
GntImpliesReady_A	1536443096	406304054	0	0
GntImpliesValid_A	1536443096	406304054	0	0
GrantKnown_A	1536443096	1533015888	0	0
IdxKnown_A	1536443096	1533015888	0	0
IndexIsCorrect_A	1536443096	406304054	0	0
NoReadyValidNoGrant_A	1536443096	178717700	0	0
Priority_A	1536443096	430256038	0	0
ReadyAndValidImplyGrant_A	1536443096	406304054	0	0
ReqAndReadyImplyGrant_A	1536443096	406304054	0	0
ReqImpliesValid_A	1536443096	430256038	0	0
ValidKnown_A	1536443096	1533015888	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536443096	1533015888	0	0
T1	2868592	2868272	0	0
T2	314092	301644	0	0
T3	261228	260936	0	0
T4	6712	6172	0	0
T5	568984	568372	0	0
T6	727624	726844	0	0
T11	14180	11156	0	0
T19	31196	30872	0	0
T20	5500	5200	0	0
T21	24712	24068	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4160	4160	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T11	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536443096	406304054	0	0
T1	2868592	1278442	0	0
T2	314092	46704	0	0
T3	261228	40780	0	0
T4	6712	150	0	0
T5	568984	85670	0	0
T6	727624	85646	0	0
T7	0	16872	0	0
T11	14180	286	0	0
T19	31196	10862	0	0
T20	5500	64	0	0
T21	24712	8300	0	0
T26	0	233136	0	0
T41	0	244206	0	0
T46	0	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536443096	406304054	0	0
T1	2868592	1278442	0	0
T2	314092	46704	0	0
T3	261228	40780	0	0
T4	6712	150	0	0
T5	568984	85670	0	0
T6	727624	85646	0	0
T7	0	16872	0	0
T11	14180	286	0	0
T19	31196	10862	0	0
T20	5500	64	0	0
T21	24712	8300	0	0
T26	0	233136	0	0
T41	0	244206	0	0
T46	0	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536443096	1533015888	0	0
T1	2868592	2868272	0	0
T2	314092	301644	0	0
T3	261228	260936	0	0
T4	6712	6172	0	0
T5	568984	568372	0	0
T6	727624	726844	0	0
T11	14180	11156	0	0
T19	31196	30872	0	0
T20	5500	5200	0	0
T21	24712	24068	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536443096	1533015888	0	0
T1	2868592	2868272	0	0
T2	314092	301644	0	0
T3	261228	260936	0	0
T4	6712	6172	0	0
T5	568984	568372	0	0
T6	727624	726844	0	0
T11	14180	11156	0	0
T19	31196	30872	0	0
T20	5500	5200	0	0
T21	24712	24068	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536443096	406304054	0	0
T1	2868592	1278442	0	0
T2	314092	46704	0	0
T3	261228	40780	0	0
T4	6712	150	0	0
T5	568984	85670	0	0
T6	727624	85646	0	0
T7	0	16872	0	0
T11	14180	286	0	0
T19	31196	10862	0	0
T20	5500	64	0	0
T21	24712	8300	0	0
T26	0	233136	0	0
T41	0	244206	0	0
T46	0	38	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536443096	178717700	0	0
T1	2868592	14744	0	0
T2	314092	15272	0	0
T3	261228	256	0	0
T4	6712	512	0	0
T5	568984	142638	0	0
T6	727624	232984	0	0
T7	0	574704	0	0
T11	14180	1096	0	0
T19	31196	800	0	0
T20	5500	256	0	0
T21	24712	1222	0	0
T22	0	27846	0	0
T41	0	171492	0	0
T46	0	60	0	0
T47	0	360	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536443096	430256038	0	0
T1	2868592	1278442	0	0
T2	314092	46704	0	0
T3	261228	40780	0	0
T4	6712	150	0	0
T5	568984	96696	0	0
T6	727624	89578	0	0
T7	0	294272	0	0
T11	14180	286	0	0
T19	31196	10862	0	0
T20	5500	64	0	0
T21	24712	8300	0	0
T26	0	233136	0	0
T41	0	297526	0	0
T46	0	38	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536443096	406304054	0	0
T1	2868592	1278442	0	0
T2	314092	46704	0	0
T3	261228	40780	0	0
T4	6712	150	0	0
T5	568984	85670	0	0
T6	727624	85646	0	0
T7	0	16872	0	0
T11	14180	286	0	0
T19	31196	10862	0	0
T20	5500	64	0	0
T21	24712	8300	0	0
T26	0	233136	0	0
T41	0	244206	0	0
T46	0	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536443096	406304054	0	0
T1	2868592	1278442	0	0
T2	314092	46704	0	0
T3	261228	40780	0	0
T4	6712	150	0	0
T5	568984	85670	0	0
T6	727624	85646	0	0
T7	0	16872	0	0
T11	14180	286	0	0
T19	31196	10862	0	0
T20	5500	64	0	0
T21	24712	8300	0	0
T26	0	233136	0	0
T41	0	244206	0	0
T46	0	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536443096	430256038	0	0
T1	2868592	1278442	0	0
T2	314092	46704	0	0
T3	261228	40780	0	0
T4	6712	150	0	0
T5	568984	96696	0	0
T6	727624	89578	0	0
T7	0	294272	0	0
T11	14180	286	0	0
T19	31196	10862	0	0
T20	5500	64	0	0
T21	24712	8300	0	0
T26	0	233136	0	0
T41	0	297526	0	0
T46	0	38	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536443096	1533015888	0	0
T1	2868592	2868272	0	0
T2	314092	301644	0	0
T3	261228	260936	0	0
T4	6712	6172	0	0
T5	568984	568372	0	0
T6	727624	726844	0	0
T11	14180	11156	0	0
T19	31196	30872	0	0
T20	5500	5200	0	0
T21	24712	24068	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T21
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384110774	383253972	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	384110774	104552416	0	0
GntImpliesValid_A	384110774	104552416	0	0
GrantKnown_A	384110774	383253972	0	0
IdxKnown_A	384110774	383253972	0	0
IndexIsCorrect_A	384110774	104552416	0	0
NoReadyValidNoGrant_A	384110774	45816090	0	0
Priority_A	384110774	110476153	0	0
ReadyAndValidImplyGrant_A	384110774	104552416	0	0
ReqAndReadyImplyGrant_A	384110774	104552416	0	0
ReqImpliesValid_A	384110774	110476153	0	0
ValidKnown_A	384110774	383253972	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	104552416	0	0
T1	717148	591465	0	0
T2	78523	23352	0	0
T3	65307	11515	0	0
T4	1678	75	0	0
T5	142246	20092	0	0
T6	181906	22025	0	0
T11	3545	143	0	0
T19	7799	1800	0	0
T20	1375	32	0	0
T21	6178	3317	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	104552416	0	0
T1	717148	591465	0	0
T2	78523	23352	0	0
T3	65307	11515	0	0
T4	1678	75	0	0
T5	142246	20092	0	0
T6	181906	22025	0	0
T11	3545	143	0	0
T19	7799	1800	0	0
T20	1375	32	0	0
T21	6178	3317	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	104552416	0	0
T1	717148	591465	0	0
T2	78523	23352	0	0
T3	65307	11515	0	0
T4	1678	75	0	0
T5	142246	20092	0	0
T6	181906	22025	0	0
T11	3545	143	0	0
T19	7799	1800	0	0
T20	1375	32	0	0
T21	6178	3317	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	45816090	0	0
T1	717148	7136	0	0
T2	78523	7636	0	0
T3	65307	128	0	0
T4	1678	256	0	0
T5	142246	31344	0	0
T6	181906	59894	0	0
T11	3545	548	0	0
T19	7799	279	0	0
T20	1375	128	0	0
T21	6178	513	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	110476153	0	0
T1	717148	591465	0	0
T2	78523	23352	0	0
T3	65307	11515	0	0
T4	1678	75	0	0
T5	142246	22940	0	0
T6	181906	22803	0	0
T11	3545	143	0	0
T19	7799	1800	0	0
T20	1375	32	0	0
T21	6178	3317	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	104552416	0	0
T1	717148	591465	0	0
T2	78523	23352	0	0
T3	65307	11515	0	0
T4	1678	75	0	0
T5	142246	20092	0	0
T6	181906	22025	0	0
T11	3545	143	0	0
T19	7799	1800	0	0
T20	1375	32	0	0
T21	6178	3317	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	104552416	0	0
T1	717148	591465	0	0
T2	78523	23352	0	0
T3	65307	11515	0	0
T4	1678	75	0	0
T5	142246	20092	0	0
T6	181906	22025	0	0
T11	3545	143	0	0
T19	7799	1800	0	0
T20	1375	32	0	0
T21	6178	3317	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	110476153	0	0
T1	717148	591465	0	0
T2	78523	23352	0	0
T3	65307	11515	0	0
T4	1678	75	0	0
T5	142246	22940	0	0
T6	181906	22803	0	0
T11	3545	143	0	0
T19	7799	1800	0	0
T20	1375	32	0	0
T21	6178	3317	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T21
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384110774	383253972	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	384110774	104552416	0	0
GntImpliesValid_A	384110774	104552416	0	0
GrantKnown_A	384110774	383253972	0	0
IdxKnown_A	384110774	383253972	0	0
IndexIsCorrect_A	384110774	104552416	0	0
NoReadyValidNoGrant_A	384110774	45816090	0	0
Priority_A	384110774	110476153	0	0
ReadyAndValidImplyGrant_A	384110774	104552416	0	0
ReqAndReadyImplyGrant_A	384110774	104552416	0	0
ReqImpliesValid_A	384110774	110476153	0	0
ValidKnown_A	384110774	383253972	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	104552416	0	0
T1	717148	591465	0	0
T2	78523	23352	0	0
T3	65307	11515	0	0
T4	1678	75	0	0
T5	142246	20092	0	0
T6	181906	22025	0	0
T11	3545	143	0	0
T19	7799	1800	0	0
T20	1375	32	0	0
T21	6178	3317	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	104552416	0	0
T1	717148	591465	0	0
T2	78523	23352	0	0
T3	65307	11515	0	0
T4	1678	75	0	0
T5	142246	20092	0	0
T6	181906	22025	0	0
T11	3545	143	0	0
T19	7799	1800	0	0
T20	1375	32	0	0
T21	6178	3317	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	104552416	0	0
T1	717148	591465	0	0
T2	78523	23352	0	0
T3	65307	11515	0	0
T4	1678	75	0	0
T5	142246	20092	0	0
T6	181906	22025	0	0
T11	3545	143	0	0
T19	7799	1800	0	0
T20	1375	32	0	0
T21	6178	3317	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	45816090	0	0
T1	717148	7136	0	0
T2	78523	7636	0	0
T3	65307	128	0	0
T4	1678	256	0	0
T5	142246	31344	0	0
T6	181906	59894	0	0
T11	3545	548	0	0
T19	7799	279	0	0
T20	1375	128	0	0
T21	6178	513	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	110476153	0	0
T1	717148	591465	0	0
T2	78523	23352	0	0
T3	65307	11515	0	0
T4	1678	75	0	0
T5	142246	22940	0	0
T6	181906	22803	0	0
T11	3545	143	0	0
T19	7799	1800	0	0
T20	1375	32	0	0
T21	6178	3317	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	104552416	0	0
T1	717148	591465	0	0
T2	78523	23352	0	0
T3	65307	11515	0	0
T4	1678	75	0	0
T5	142246	20092	0	0
T6	181906	22025	0	0
T11	3545	143	0	0
T19	7799	1800	0	0
T20	1375	32	0	0
T21	6178	3317	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	104552416	0	0
T1	717148	591465	0	0
T2	78523	23352	0	0
T3	65307	11515	0	0
T4	1678	75	0	0
T5	142246	20092	0	0
T6	181906	22025	0	0
T11	3545	143	0	0
T19	7799	1800	0	0
T20	1375	32	0	0
T21	6178	3317	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	110476153	0	0
T1	717148	591465	0	0
T2	78523	23352	0	0
T3	65307	11515	0	0
T4	1678	75	0	0
T5	142246	22940	0	0
T6	181906	22803	0	0
T11	3545	143	0	0
T19	7799	1800	0	0
T20	1375	32	0	0
T21	6178	3317	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T5,T6,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T21
1	0	Covered	T1,T3,T5
1	1	Covered	T5,T6,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T21
1	1	Covered	T1,T3,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T21
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384110774	383253972	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	384110774	98599677	0	0
GntImpliesValid_A	384110774	98599677	0	0
GrantKnown_A	384110774	383253972	0	0
IdxKnown_A	384110774	383253972	0	0
IndexIsCorrect_A	384110774	98599677	0	0
NoReadyValidNoGrant_A	384110774	43542759	0	0
Priority_A	384110774	104651933	0	0
ReadyAndValidImplyGrant_A	384110774	98599677	0	0
ReqAndReadyImplyGrant_A	384110774	98599677	0	0
ReqImpliesValid_A	384110774	104651933	0	0
ValidKnown_A	384110774	383253972	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	98599677	0	0
T1	717148	47756	0	0
T2	78523	0	0	0
T3	65307	8875	0	0
T4	1678	0	0	0
T5	142246	22743	0	0
T6	181906	20798	0	0
T7	0	8436	0	0
T11	3545	0	0	0
T19	7799	3631	0	0
T20	1375	0	0	0
T21	6178	833	0	0
T26	0	116568	0	0
T41	0	122103	0	0
T46	0	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	98599677	0	0
T1	717148	47756	0	0
T2	78523	0	0	0
T3	65307	8875	0	0
T4	1678	0	0	0
T5	142246	22743	0	0
T6	181906	20798	0	0
T7	0	8436	0	0
T11	3545	0	0	0
T19	7799	3631	0	0
T20	1375	0	0	0
T21	6178	833	0	0
T26	0	116568	0	0
T41	0	122103	0	0
T46	0	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	98599677	0	0
T1	717148	47756	0	0
T2	78523	0	0	0
T3	65307	8875	0	0
T4	1678	0	0	0
T5	142246	22743	0	0
T6	181906	20798	0	0
T7	0	8436	0	0
T11	3545	0	0	0
T19	7799	3631	0	0
T20	1375	0	0	0
T21	6178	833	0	0
T26	0	116568	0	0
T41	0	122103	0	0
T46	0	19	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	43542759	0	0
T1	717148	236	0	0
T2	78523	0	0	0
T3	65307	0	0	0
T4	1678	0	0	0
T5	142246	39975	0	0
T6	181906	56598	0	0
T7	0	287352	0	0
T11	3545	0	0	0
T19	7799	121	0	0
T20	1375	0	0	0
T21	6178	98	0	0
T22	0	13923	0	0
T41	0	85746	0	0
T46	0	30	0	0
T47	0	180	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	104651933	0	0
T1	717148	47756	0	0
T2	78523	0	0	0
T3	65307	8875	0	0
T4	1678	0	0	0
T5	142246	25408	0	0
T6	181906	21986	0	0
T7	0	147136	0	0
T11	3545	0	0	0
T19	7799	3631	0	0
T20	1375	0	0	0
T21	6178	833	0	0
T26	0	116568	0	0
T41	0	148763	0	0
T46	0	19	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	98599677	0	0
T1	717148	47756	0	0
T2	78523	0	0	0
T3	65307	8875	0	0
T4	1678	0	0	0
T5	142246	22743	0	0
T6	181906	20798	0	0
T7	0	8436	0	0
T11	3545	0	0	0
T19	7799	3631	0	0
T20	1375	0	0	0
T21	6178	833	0	0
T26	0	116568	0	0
T41	0	122103	0	0
T46	0	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	98599677	0	0
T1	717148	47756	0	0
T2	78523	0	0	0
T3	65307	8875	0	0
T4	1678	0	0	0
T5	142246	22743	0	0
T6	181906	20798	0	0
T7	0	8436	0	0
T11	3545	0	0	0
T19	7799	3631	0	0
T20	1375	0	0	0
T21	6178	833	0	0
T26	0	116568	0	0
T41	0	122103	0	0
T46	0	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	104651933	0	0
T1	717148	47756	0	0
T2	78523	0	0	0
T3	65307	8875	0	0
T4	1678	0	0	0
T5	142246	25408	0	0
T6	181906	21986	0	0
T7	0	147136	0	0
T11	3545	0	0	0
T19	7799	3631	0	0
T20	1375	0	0	0
T21	6178	833	0	0
T26	0	116568	0	0
T41	0	148763	0	0
T46	0	19	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T5,T6,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T21
1	0	Covered	T1,T3,T5
1	1	Covered	T5,T6,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T21
1	1	Covered	T1,T3,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T21
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384110774	383253972	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	384110774	98599545	0	0
GntImpliesValid_A	384110774	98599545	0	0
GrantKnown_A	384110774	383253972	0	0
IdxKnown_A	384110774	383253972	0	0
IndexIsCorrect_A	384110774	98599545	0	0
NoReadyValidNoGrant_A	384110774	43542761	0	0
Priority_A	384110774	104651799	0	0
ReadyAndValidImplyGrant_A	384110774	98599545	0	0
ReqAndReadyImplyGrant_A	384110774	98599545	0	0
ReqImpliesValid_A	384110774	104651799	0	0
ValidKnown_A	384110774	383253972	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	98599545	0	0
T1	717148	47756	0	0
T2	78523	0	0	0
T3	65307	8875	0	0
T4	1678	0	0	0
T5	142246	22743	0	0
T6	181906	20798	0	0
T7	0	8436	0	0
T11	3545	0	0	0
T19	7799	3631	0	0
T20	1375	0	0	0
T21	6178	833	0	0
T26	0	116568	0	0
T41	0	122103	0	0
T46	0	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	98599545	0	0
T1	717148	47756	0	0
T2	78523	0	0	0
T3	65307	8875	0	0
T4	1678	0	0	0
T5	142246	22743	0	0
T6	181906	20798	0	0
T7	0	8436	0	0
T11	3545	0	0	0
T19	7799	3631	0	0
T20	1375	0	0	0
T21	6178	833	0	0
T26	0	116568	0	0
T41	0	122103	0	0
T46	0	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	98599545	0	0
T1	717148	47756	0	0
T2	78523	0	0	0
T3	65307	8875	0	0
T4	1678	0	0	0
T5	142246	22743	0	0
T6	181906	20798	0	0
T7	0	8436	0	0
T11	3545	0	0	0
T19	7799	3631	0	0
T20	1375	0	0	0
T21	6178	833	0	0
T26	0	116568	0	0
T41	0	122103	0	0
T46	0	19	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	43542761	0	0
T1	717148	236	0	0
T2	78523	0	0	0
T3	65307	0	0	0
T4	1678	0	0	0
T5	142246	39975	0	0
T6	181906	56598	0	0
T7	0	287352	0	0
T11	3545	0	0	0
T19	7799	121	0	0
T20	1375	0	0	0
T21	6178	98	0	0
T22	0	13923	0	0
T41	0	85746	0	0
T46	0	30	0	0
T47	0	180	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	104651799	0	0
T1	717148	47756	0	0
T2	78523	0	0	0
T3	65307	8875	0	0
T4	1678	0	0	0
T5	142246	25408	0	0
T6	181906	21986	0	0
T7	0	147136	0	0
T11	3545	0	0	0
T19	7799	3631	0	0
T20	1375	0	0	0
T21	6178	833	0	0
T26	0	116568	0	0
T41	0	148763	0	0
T46	0	19	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	98599545	0	0
T1	717148	47756	0	0
T2	78523	0	0	0
T3	65307	8875	0	0
T4	1678	0	0	0
T5	142246	22743	0	0
T6	181906	20798	0	0
T7	0	8436	0	0
T11	3545	0	0	0
T19	7799	3631	0	0
T20	1375	0	0	0
T21	6178	833	0	0
T26	0	116568	0	0
T41	0	122103	0	0
T46	0	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	98599545	0	0
T1	717148	47756	0	0
T2	78523	0	0	0
T3	65307	8875	0	0
T4	1678	0	0	0
T5	142246	22743	0	0
T6	181906	20798	0	0
T7	0	8436	0	0
T11	3545	0	0	0
T19	7799	3631	0	0
T20	1375	0	0	0
T21	6178	833	0	0
T26	0	116568	0	0
T41	0	122103	0	0
T46	0	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	104651799	0	0
T1	717148	47756	0	0
T2	78523	0	0	0
T3	65307	8875	0	0
T4	1678	0	0	0
T5	142246	25408	0	0
T6	181906	21986	0	0
T7	0	147136	0	0
T11	3545	0	0	0
T19	7799	3631	0	0
T20	1375	0	0	0
T21	6178	833	0	0
T26	0	116568	0	0
T41	0	148763	0	0
T46	0	19	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110774	383253972	0	0
T1	717148	717068	0	0
T2	78523	75411	0	0
T3	65307	65234	0	0
T4	1678	1543	0	0
T5	142246	142093	0	0
T6	181906	181711	0	0
T11	3545	2789	0	0
T19	7799	7718	0	0
T20	1375	1300	0	0
T21	6178	6017	0	0