Line Coverage for Module :
flash_phy_rd_buffers
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
flash_phy_rd_buffers
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T78,T79,T71 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T21 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Module :
flash_phy_rd_buffers
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T78,T79,T71 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T2,T21 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T5 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_rd_buffers
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
5169993 |
0 |
0 |
T1 |
5737184 |
2424 |
0 |
0 |
T2 |
628184 |
468 |
0 |
0 |
T3 |
522456 |
0 |
0 |
0 |
T4 |
13424 |
0 |
0 |
0 |
T5 |
1137968 |
30155 |
0 |
0 |
T6 |
1455248 |
30337 |
0 |
0 |
T7 |
0 |
16775 |
0 |
0 |
T11 |
28360 |
0 |
0 |
0 |
T19 |
62392 |
98 |
0 |
0 |
T20 |
11000 |
0 |
0 |
0 |
T21 |
49424 |
103 |
0 |
0 |
T22 |
0 |
19442 |
0 |
0 |
T41 |
0 |
43649 |
0 |
0 |
T46 |
0 |
11 |
0 |
0 |
T47 |
0 |
114 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
5169989 |
0 |
0 |
T1 |
5737184 |
2424 |
0 |
0 |
T2 |
628184 |
468 |
0 |
0 |
T3 |
522456 |
0 |
0 |
0 |
T4 |
13424 |
0 |
0 |
0 |
T5 |
1137968 |
30155 |
0 |
0 |
T6 |
1455248 |
30337 |
0 |
0 |
T7 |
0 |
16775 |
0 |
0 |
T11 |
28360 |
0 |
0 |
0 |
T19 |
62392 |
98 |
0 |
0 |
T20 |
11000 |
0 |
0 |
0 |
T21 |
49424 |
103 |
0 |
0 |
T22 |
0 |
19442 |
0 |
0 |
T41 |
0 |
43649 |
0 |
0 |
T46 |
0 |
11 |
0 |
0 |
T47 |
0 |
114 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T79,T71,T80 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T21 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T79,T71,T80 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T2,T21 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T5 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
656864 |
0 |
0 |
T1 |
717148 |
585 |
0 |
0 |
T2 |
78523 |
117 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3597 |
0 |
0 |
T6 |
181906 |
3861 |
0 |
0 |
T7 |
0 |
2085 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
14 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
19 |
0 |
0 |
T22 |
0 |
2360 |
0 |
0 |
T41 |
0 |
5556 |
0 |
0 |
T47 |
0 |
12 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
656862 |
0 |
0 |
T1 |
717148 |
585 |
0 |
0 |
T2 |
78523 |
117 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3597 |
0 |
0 |
T6 |
181906 |
3861 |
0 |
0 |
T7 |
0 |
2085 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
14 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
19 |
0 |
0 |
T22 |
0 |
2360 |
0 |
0 |
T41 |
0 |
5556 |
0 |
0 |
T47 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T79,T71,T80 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T21 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T79,T71,T80 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T2,T21 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T5 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
656517 |
0 |
0 |
T1 |
717148 |
585 |
0 |
0 |
T2 |
78523 |
117 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3597 |
0 |
0 |
T6 |
181906 |
3845 |
0 |
0 |
T7 |
0 |
2085 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
13 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
18 |
0 |
0 |
T22 |
0 |
2355 |
0 |
0 |
T41 |
0 |
5557 |
0 |
0 |
T47 |
0 |
12 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
656517 |
0 |
0 |
T1 |
717148 |
585 |
0 |
0 |
T2 |
78523 |
117 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3597 |
0 |
0 |
T6 |
181906 |
3845 |
0 |
0 |
T7 |
0 |
2085 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
13 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
18 |
0 |
0 |
T22 |
0 |
2355 |
0 |
0 |
T41 |
0 |
5557 |
0 |
0 |
T47 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T71,T80,T81 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T21 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T71,T80,T81 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T2,T21 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T5 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
656672 |
0 |
0 |
T1 |
717148 |
585 |
0 |
0 |
T2 |
78523 |
117 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3599 |
0 |
0 |
T6 |
181906 |
3848 |
0 |
0 |
T7 |
0 |
2085 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
13 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
17 |
0 |
0 |
T22 |
0 |
2355 |
0 |
0 |
T41 |
0 |
5554 |
0 |
0 |
T47 |
0 |
12 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
656671 |
0 |
0 |
T1 |
717148 |
585 |
0 |
0 |
T2 |
78523 |
117 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3599 |
0 |
0 |
T6 |
181906 |
3848 |
0 |
0 |
T7 |
0 |
2085 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
13 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
17 |
0 |
0 |
T22 |
0 |
2355 |
0 |
0 |
T41 |
0 |
5554 |
0 |
0 |
T47 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T71,T80,T82 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T21 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T71,T80,T82 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T2,T21 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T5 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
656054 |
0 |
0 |
T1 |
717148 |
584 |
0 |
0 |
T2 |
78523 |
117 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3594 |
0 |
0 |
T6 |
181906 |
3844 |
0 |
0 |
T7 |
0 |
2084 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
13 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
18 |
0 |
0 |
T22 |
0 |
2350 |
0 |
0 |
T41 |
0 |
5561 |
0 |
0 |
T47 |
0 |
12 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
656054 |
0 |
0 |
T1 |
717148 |
584 |
0 |
0 |
T2 |
78523 |
117 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3594 |
0 |
0 |
T6 |
181906 |
3844 |
0 |
0 |
T7 |
0 |
2084 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
13 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
18 |
0 |
0 |
T22 |
0 |
2350 |
0 |
0 |
T41 |
0 |
5561 |
0 |
0 |
T47 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T78,T71,T82 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T5,T6 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T83,T84,T70 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T5,T6 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T5,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T78,T71,T82 |
0 |
0 |
1 |
- |
- |
Covered |
T83,T84,T70 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T5,T6 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
635845 |
0 |
0 |
T1 |
717148 |
22 |
0 |
0 |
T2 |
78523 |
0 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3942 |
0 |
0 |
T6 |
181906 |
3736 |
0 |
0 |
T7 |
0 |
2109 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
12 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
8 |
0 |
0 |
T22 |
0 |
2500 |
0 |
0 |
T41 |
0 |
5360 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T47 |
0 |
17 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
635844 |
0 |
0 |
T1 |
717148 |
22 |
0 |
0 |
T2 |
78523 |
0 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3942 |
0 |
0 |
T6 |
181906 |
3736 |
0 |
0 |
T7 |
0 |
2109 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
12 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
8 |
0 |
0 |
T22 |
0 |
2500 |
0 |
0 |
T41 |
0 |
5360 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T47 |
0 |
17 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T78,T71,T82 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T5,T6 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T28,T83,T84 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T5,T6 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T5,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T78,T71,T82 |
0 |
0 |
1 |
- |
- |
Covered |
T28,T83,T84 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T5,T6 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
636322 |
0 |
0 |
T1 |
717148 |
21 |
0 |
0 |
T2 |
78523 |
0 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3944 |
0 |
0 |
T6 |
181906 |
3734 |
0 |
0 |
T7 |
0 |
2109 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
11 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
7 |
0 |
0 |
T22 |
0 |
2514 |
0 |
0 |
T41 |
0 |
5355 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T47 |
0 |
17 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
636322 |
0 |
0 |
T1 |
717148 |
21 |
0 |
0 |
T2 |
78523 |
0 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3944 |
0 |
0 |
T6 |
181906 |
3734 |
0 |
0 |
T7 |
0 |
2109 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
11 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
7 |
0 |
0 |
T22 |
0 |
2514 |
0 |
0 |
T41 |
0 |
5355 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T47 |
0 |
17 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T78,T71,T82 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T5,T6 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T83,T31,T84 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T5,T6 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T5,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T78,T71,T82 |
0 |
0 |
1 |
- |
- |
Covered |
T83,T31,T84 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T5,T6 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
636127 |
0 |
0 |
T1 |
717148 |
21 |
0 |
0 |
T2 |
78523 |
0 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3940 |
0 |
0 |
T6 |
181906 |
3735 |
0 |
0 |
T7 |
0 |
2109 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
11 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
7 |
0 |
0 |
T22 |
0 |
2510 |
0 |
0 |
T41 |
0 |
5358 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T47 |
0 |
16 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
636127 |
0 |
0 |
T1 |
717148 |
21 |
0 |
0 |
T2 |
78523 |
0 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3940 |
0 |
0 |
T6 |
181906 |
3735 |
0 |
0 |
T7 |
0 |
2109 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
11 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
7 |
0 |
0 |
T22 |
0 |
2510 |
0 |
0 |
T41 |
0 |
5358 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T47 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T78,T71,T82 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T5,T6 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T21,T83,T84 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T5,T6 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T5,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T78,T71,T82 |
0 |
0 |
1 |
- |
- |
Covered |
T21,T83,T84 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T5,T6 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
635592 |
0 |
0 |
T1 |
717148 |
21 |
0 |
0 |
T2 |
78523 |
0 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3942 |
0 |
0 |
T6 |
181906 |
3734 |
0 |
0 |
T7 |
0 |
2109 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
11 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
9 |
0 |
0 |
T22 |
0 |
2498 |
0 |
0 |
T41 |
0 |
5348 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T47 |
0 |
16 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110774 |
635592 |
0 |
0 |
T1 |
717148 |
21 |
0 |
0 |
T2 |
78523 |
0 |
0 |
0 |
T3 |
65307 |
0 |
0 |
0 |
T4 |
1678 |
0 |
0 |
0 |
T5 |
142246 |
3942 |
0 |
0 |
T6 |
181906 |
3734 |
0 |
0 |
T7 |
0 |
2109 |
0 |
0 |
T11 |
3545 |
0 |
0 |
0 |
T19 |
7799 |
11 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
6178 |
9 |
0 |
0 |
T22 |
0 |
2498 |
0 |
0 |
T41 |
0 |
5348 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T47 |
0 |
16 |
0 |
0 |