SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 8320 | 8320 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 2147483647 | 166695206 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 8320 | 8320 | 0 | 0 |
T1 | 8 | 8 | 0 | 0 |
T2 | 8 | 8 | 0 | 0 |
T3 | 8 | 8 | 0 | 0 |
T4 | 8 | 8 | 0 | 0 |
T5 | 8 | 8 | 0 | 0 |
T6 | 8 | 8 | 0 | 0 |
T11 | 8 | 8 | 0 | 0 |
T19 | 8 | 8 | 0 | 0 |
T20 | 8 | 8 | 0 | 0 |
T21 | 8 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 166695206 | 0 | 0 |
T1 | 5020036 | 1624714 | 0 | 0 |
T2 | 549661 | 24168 | 0 | 0 |
T3 | 457149 | 0 | 0 | 0 |
T4 | 11746 | 0 | 0 | 0 |
T5 | 995722 | 0 | 0 | 0 |
T6 | 1273342 | 0 | 0 | 0 |
T11 | 24815 | 3 | 0 | 0 |
T12 | 0 | 3 | 0 | 0 |
T19 | 54593 | 400 | 0 | 0 |
T20 | 9625 | 0 | 0 | 0 |
T21 | 43246 | 512 | 0 | 0 |
T26 | 0 | 10400 | 0 | 0 |
T34 | 0 | 1048576 | 0 | 0 |
T41 | 0 | 8850 | 0 | 0 |
T43 | 0 | 400 | 0 | 0 |
T44 | 2672 | 0 | 0 | 0 |
T47 | 0 | 1456 | 0 | 0 |
T66 | 0 | 400 | 0 | 0 |
T102 | 831 | 0 | 0 | 0 |
T106 | 0 | 3 | 0 | 0 |
T116 | 189012 | 0 | 0 | 0 |
T117 | 113217 | 0 | 0 | 0 |
T118 | 171936 | 0 | 0 | 0 |
T119 | 997 | 0 | 0 | 0 |
T120 | 375329 | 0 | 0 | 0 |
T121 | 2907 | 0 | 0 | 0 |
T122 | 105511 | 720896 | 0 | 0 |
T123 | 2957 | 0 | 0 | 0 |
T124 | 0 | 262144 | 0 | 0 |
T125 | 0 | 458752 | 0 | 0 |
T126 | 0 | 393216 | 0 | 0 |
T127 | 0 | 65536 | 0 | 0 |
T128 | 0 | 589824 | 0 | 0 |
T129 | 0 | 12800 | 0 | 0 |
T130 | 0 | 12800 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T3,T19 |
1 | 0 | Covered | T1,T3,T5 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1040 | 1040 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 384110774 | 58762975 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 384110774 | 58762975 | 0 | 0 |
T1 | 717148 | 529816 | 0 | 0 |
T2 | 78523 | 0 | 0 | 0 |
T3 | 65307 | 12500 | 0 | 0 |
T4 | 1678 | 0 | 0 | 0 |
T5 | 142246 | 0 | 0 | 0 |
T6 | 181906 | 0 | 0 | 0 |
T11 | 3545 | 0 | 0 | 0 |
T19 | 7799 | 1168 | 0 | 0 |
T20 | 1375 | 0 | 0 | 0 |
T21 | 6178 | 2560 | 0 | 0 |
T23 | 0 | 1000 | 0 | 0 |
T26 | 0 | 65200 | 0 | 0 |
T41 | 0 | 96750 | 0 | 0 |
T46 | 0 | 600 | 0 | 0 |
T47 | 0 | 1062 | 0 | 0 |
T87 | 0 | 23040 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T19 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1040 | 1040 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 384110774 | 15237979 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 384110774 | 15237979 | 0 | 0 |
T1 | 717148 | 575838 | 0 | 0 |
T2 | 78523 | 24168 | 0 | 0 |
T3 | 65307 | 0 | 0 | 0 |
T4 | 1678 | 0 | 0 | 0 |
T5 | 142246 | 0 | 0 | 0 |
T6 | 181906 | 0 | 0 | 0 |
T11 | 3545 | 3 | 0 | 0 |
T12 | 0 | 3 | 0 | 0 |
T19 | 7799 | 400 | 0 | 0 |
T20 | 1375 | 0 | 0 | 0 |
T21 | 6178 | 512 | 0 | 0 |
T26 | 0 | 10250 | 0 | 0 |
T41 | 0 | 8750 | 0 | 0 |
T47 | 0 | 1456 | 0 | 0 |
T106 | 0 | 3 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T34,T122 |
1 | 0 | Covered | T19,T22,T47 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1040 | 1040 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 384110774 | 5006336 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 384110774 | 5006336 | 0 | 0 |
T1 | 717148 | 524288 | 0 | 0 |
T2 | 78523 | 0 | 0 | 0 |
T3 | 65307 | 0 | 0 | 0 |
T4 | 1678 | 0 | 0 | 0 |
T5 | 142246 | 0 | 0 | 0 |
T6 | 181906 | 0 | 0 | 0 |
T11 | 3545 | 0 | 0 | 0 |
T19 | 7799 | 0 | 0 | 0 |
T20 | 1375 | 0 | 0 | 0 |
T21 | 6178 | 0 | 0 | 0 |
T34 | 0 | 524288 | 0 | 0 |
T122 | 0 | 720896 | 0 | 0 |
T124 | 0 | 262144 | 0 | 0 |
T125 | 0 | 458752 | 0 | 0 |
T126 | 0 | 393216 | 0 | 0 |
T127 | 0 | 65536 | 0 | 0 |
T128 | 0 | 589824 | 0 | 0 |
T129 | 0 | 12800 | 0 | 0 |
T130 | 0 | 12800 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T41,T26 |
1 | 0 | Covered | T1,T41,T26 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1040 | 1040 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 384110774 | 5126373 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 384110774 | 5126373 | 0 | 0 |
T1 | 717148 | 524588 | 0 | 0 |
T2 | 78523 | 0 | 0 | 0 |
T3 | 65307 | 0 | 0 | 0 |
T4 | 1678 | 0 | 0 | 0 |
T5 | 142246 | 0 | 0 | 0 |
T6 | 181906 | 0 | 0 | 0 |
T11 | 3545 | 0 | 0 | 0 |
T19 | 7799 | 0 | 0 | 0 |
T20 | 1375 | 0 | 0 | 0 |
T21 | 6178 | 0 | 0 | 0 |
T26 | 0 | 150 | 0 | 0 |
T32 | 0 | 11500 | 0 | 0 |
T33 | 0 | 19000 | 0 | 0 |
T34 | 0 | 524288 | 0 | 0 |
T41 | 0 | 100 | 0 | 0 |
T43 | 0 | 400 | 0 | 0 |
T66 | 0 | 400 | 0 | 0 |
T131 | 0 | 450 | 0 | 0 |
T132 | 0 | 1400 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T3,T19 |
1 | 0 | Covered | T1,T3,T5 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1040 | 1040 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 384110774 | 64893833 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 384110774 | 64893833 | 0 | 0 |
T1 | 717148 | 4398 | 0 | 0 |
T2 | 78523 | 0 | 0 | 0 |
T3 | 65307 | 9650 | 0 | 0 |
T4 | 1678 | 0 | 0 | 0 |
T5 | 142246 | 0 | 0 | 0 |
T6 | 181906 | 0 | 0 | 0 |
T11 | 3545 | 0 | 0 | 0 |
T19 | 7799 | 1912 | 0 | 0 |
T20 | 1375 | 0 | 0 | 0 |
T21 | 6178 | 768 | 0 | 0 |
T26 | 0 | 99000 | 0 | 0 |
T28 | 0 | 256 | 0 | 0 |
T41 | 0 | 117350 | 0 | 0 |
T43 | 0 | 83400 | 0 | 0 |
T47 | 0 | 750 | 0 | 0 |
T50 | 0 | 1300 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T19,T47 |
1 | 0 | Covered | T1,T19,T47 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1040 | 1040 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 384110774 | 6792028 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 384110774 | 6792028 | 0 | 0 |
T1 | 717148 | 39000 | 0 | 0 |
T2 | 78523 | 0 | 0 | 0 |
T3 | 65307 | 0 | 0 | 0 |
T4 | 1678 | 0 | 0 | 0 |
T5 | 142246 | 0 | 0 | 0 |
T6 | 181906 | 0 | 0 | 0 |
T11 | 3545 | 0 | 0 | 0 |
T19 | 7799 | 600 | 0 | 0 |
T20 | 1375 | 0 | 0 | 0 |
T21 | 6178 | 0 | 0 | 0 |
T27 | 0 | 50 | 0 | 0 |
T28 | 0 | 256 | 0 | 0 |
T47 | 0 | 856 | 0 | 0 |
T70 | 0 | 750 | 0 | 0 |
T72 | 0 | 350 | 0 | 0 |
T84 | 0 | 1518 | 0 | 0 |
T133 | 0 | 300 | 0 | 0 |
T134 | 0 | 1750 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T116,T125,T135 |
1 | 0 | Covered | T19,T47,T133 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1040 | 1040 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 384110774 | 5413464 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 384110774 | 5413464 | 0 | 0 |
T44 | 2672 | 0 | 0 | 0 |
T102 | 831 | 0 | 0 | 0 |
T116 | 189012 | 506 | 0 | 0 |
T117 | 113217 | 0 | 0 | 0 |
T118 | 171936 | 0 | 0 | 0 |
T119 | 997 | 0 | 0 | 0 |
T120 | 375329 | 0 | 0 | 0 |
T121 | 2907 | 0 | 0 | 0 |
T122 | 105511 | 0 | 0 | 0 |
T123 | 2957 | 0 | 0 | 0 |
T125 | 0 | 524288 | 0 | 0 |
T128 | 0 | 458752 | 0 | 0 |
T135 | 0 | 393216 | 0 | 0 |
T136 | 0 | 12800 | 0 | 0 |
T137 | 0 | 524288 | 0 | 0 |
T138 | 0 | 12800 | 0 | 0 |
T139 | 0 | 12800 | 0 | 0 |
T140 | 0 | 589824 | 0 | 0 |
T141 | 0 | 458752 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T19,T47 |
1 | 0 | Covered | T1,T19,T47 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1040 | 1040 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 384110774 | 5462218 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 384110774 | 5462218 | 0 | 0 |
T1 | 717148 | 300 | 0 | 0 |
T2 | 78523 | 0 | 0 | 0 |
T3 | 65307 | 0 | 0 | 0 |
T4 | 1678 | 0 | 0 | 0 |
T5 | 142246 | 0 | 0 | 0 |
T6 | 181906 | 0 | 0 | 0 |
T11 | 3545 | 0 | 0 | 0 |
T19 | 7799 | 750 | 0 | 0 |
T20 | 1375 | 0 | 0 | 0 |
T21 | 6178 | 0 | 0 | 0 |
T34 | 0 | 250 | 0 | 0 |
T47 | 0 | 100 | 0 | 0 |
T70 | 0 | 550 | 0 | 0 |
T125 | 0 | 524288 | 0 | 0 |
T133 | 0 | 500 | 0 | 0 |
T134 | 0 | 500 | 0 | 0 |
T142 | 0 | 506 | 0 | 0 |
T143 | 0 | 50 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |