Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
2147483647 |
2147483647 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
8605776 |
8604816 |
0 |
0 |
T2 |
942276 |
904932 |
0 |
0 |
T3 |
783684 |
782808 |
0 |
0 |
T4 |
20136 |
18516 |
0 |
0 |
T5 |
1706952 |
1705116 |
0 |
0 |
T6 |
2182872 |
2180532 |
0 |
0 |
T11 |
42540 |
33468 |
0 |
0 |
T19 |
93588 |
92616 |
0 |
0 |
T20 |
16500 |
15600 |
0 |
0 |
T21 |
74136 |
72204 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
384110818 |
383254016 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110818 |
383254016 |
0 |
0 |
T1 |
717148 |
717068 |
0 |
0 |
T2 |
78523 |
75411 |
0 |
0 |
T3 |
65307 |
65234 |
0 |
0 |
T4 |
1678 |
1543 |
0 |
0 |
T5 |
142246 |
142093 |
0 |
0 |
T6 |
181906 |
181711 |
0 |
0 |
T11 |
3545 |
2789 |
0 |
0 |
T19 |
7799 |
7718 |
0 |
0 |
T20 |
1375 |
1300 |
0 |
0 |
T21 |
6178 |
6017 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
384110818 |
383254016 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110818 |
383254016 |
0 |
0 |
T1 |
717148 |
717068 |
0 |
0 |
T2 |
78523 |
75411 |
0 |
0 |
T3 |
65307 |
65234 |
0 |
0 |
T4 |
1678 |
1543 |
0 |
0 |
T5 |
142246 |
142093 |
0 |
0 |
T6 |
181906 |
181711 |
0 |
0 |
T11 |
3545 |
2789 |
0 |
0 |
T19 |
7799 |
7718 |
0 |
0 |
T20 |
1375 |
1300 |
0 |
0 |
T21 |
6178 |
6017 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
384110818 |
383254016 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110818 |
383254016 |
0 |
0 |
T1 |
717148 |
717068 |
0 |
0 |
T2 |
78523 |
75411 |
0 |
0 |
T3 |
65307 |
65234 |
0 |
0 |
T4 |
1678 |
1543 |
0 |
0 |
T5 |
142246 |
142093 |
0 |
0 |
T6 |
181906 |
181711 |
0 |
0 |
T11 |
3545 |
2789 |
0 |
0 |
T19 |
7799 |
7718 |
0 |
0 |
T20 |
1375 |
1300 |
0 |
0 |
T21 |
6178 |
6017 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
384110818 |
383254016 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110818 |
383254016 |
0 |
0 |
T1 |
717148 |
717068 |
0 |
0 |
T2 |
78523 |
75411 |
0 |
0 |
T3 |
65307 |
65234 |
0 |
0 |
T4 |
1678 |
1543 |
0 |
0 |
T5 |
142246 |
142093 |
0 |
0 |
T6 |
181906 |
181711 |
0 |
0 |
T11 |
3545 |
2789 |
0 |
0 |
T19 |
7799 |
7718 |
0 |
0 |
T20 |
1375 |
1300 |
0 |
0 |
T21 |
6178 |
6017 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
384110818 |
383254016 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110818 |
383254016 |
0 |
0 |
T1 |
717148 |
717068 |
0 |
0 |
T2 |
78523 |
75411 |
0 |
0 |
T3 |
65307 |
65234 |
0 |
0 |
T4 |
1678 |
1543 |
0 |
0 |
T5 |
142246 |
142093 |
0 |
0 |
T6 |
181906 |
181711 |
0 |
0 |
T11 |
3545 |
2789 |
0 |
0 |
T19 |
7799 |
7718 |
0 |
0 |
T20 |
1375 |
1300 |
0 |
0 |
T21 |
6178 |
6017 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
384110818 |
383254016 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110818 |
383254016 |
0 |
0 |
T1 |
717148 |
717068 |
0 |
0 |
T2 |
78523 |
75411 |
0 |
0 |
T3 |
65307 |
65234 |
0 |
0 |
T4 |
1678 |
1543 |
0 |
0 |
T5 |
142246 |
142093 |
0 |
0 |
T6 |
181906 |
181711 |
0 |
0 |
T11 |
3545 |
2789 |
0 |
0 |
T19 |
7799 |
7718 |
0 |
0 |
T20 |
1375 |
1300 |
0 |
0 |
T21 |
6178 |
6017 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
384110818 |
383254016 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110818 |
383254016 |
0 |
0 |
T1 |
717148 |
717068 |
0 |
0 |
T2 |
78523 |
75411 |
0 |
0 |
T3 |
65307 |
65234 |
0 |
0 |
T4 |
1678 |
1543 |
0 |
0 |
T5 |
142246 |
142093 |
0 |
0 |
T6 |
181906 |
181711 |
0 |
0 |
T11 |
3545 |
2789 |
0 |
0 |
T19 |
7799 |
7718 |
0 |
0 |
T20 |
1375 |
1300 |
0 |
0 |
T21 |
6178 |
6017 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
384110818 |
383254016 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110818 |
383254016 |
0 |
0 |
T1 |
717148 |
717068 |
0 |
0 |
T2 |
78523 |
75411 |
0 |
0 |
T3 |
65307 |
65234 |
0 |
0 |
T4 |
1678 |
1543 |
0 |
0 |
T5 |
142246 |
142093 |
0 |
0 |
T6 |
181906 |
181711 |
0 |
0 |
T11 |
3545 |
2789 |
0 |
0 |
T19 |
7799 |
7718 |
0 |
0 |
T20 |
1375 |
1300 |
0 |
0 |
T21 |
6178 |
6017 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
384110818 |
383254016 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110818 |
383254016 |
0 |
0 |
T1 |
717148 |
717068 |
0 |
0 |
T2 |
78523 |
75411 |
0 |
0 |
T3 |
65307 |
65234 |
0 |
0 |
T4 |
1678 |
1543 |
0 |
0 |
T5 |
142246 |
142093 |
0 |
0 |
T6 |
181906 |
181711 |
0 |
0 |
T11 |
3545 |
2789 |
0 |
0 |
T19 |
7799 |
7718 |
0 |
0 |
T20 |
1375 |
1300 |
0 |
0 |
T21 |
6178 |
6017 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
384110818 |
383254016 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110818 |
383254016 |
0 |
0 |
T1 |
717148 |
717068 |
0 |
0 |
T2 |
78523 |
75411 |
0 |
0 |
T3 |
65307 |
65234 |
0 |
0 |
T4 |
1678 |
1543 |
0 |
0 |
T5 |
142246 |
142093 |
0 |
0 |
T6 |
181906 |
181711 |
0 |
0 |
T11 |
3545 |
2789 |
0 |
0 |
T19 |
7799 |
7718 |
0 |
0 |
T20 |
1375 |
1300 |
0 |
0 |
T21 |
6178 |
6017 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
384110818 |
383254016 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110818 |
383254016 |
0 |
0 |
T1 |
717148 |
717068 |
0 |
0 |
T2 |
78523 |
75411 |
0 |
0 |
T3 |
65307 |
65234 |
0 |
0 |
T4 |
1678 |
1543 |
0 |
0 |
T5 |
142246 |
142093 |
0 |
0 |
T6 |
181906 |
181711 |
0 |
0 |
T11 |
3545 |
2789 |
0 |
0 |
T19 |
7799 |
7718 |
0 |
0 |
T20 |
1375 |
1300 |
0 |
0 |
T21 |
6178 |
6017 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
384110818 |
383254016 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110818 |
383254016 |
0 |
0 |
T1 |
717148 |
717068 |
0 |
0 |
T2 |
78523 |
75411 |
0 |
0 |
T3 |
65307 |
65234 |
0 |
0 |
T4 |
1678 |
1543 |
0 |
0 |
T5 |
142246 |
142093 |
0 |
0 |
T6 |
181906 |
181711 |
0 |
0 |
T11 |
3545 |
2789 |
0 |
0 |
T19 |
7799 |
7718 |
0 |
0 |
T20 |
1375 |
1300 |
0 |
0 |
T21 |
6178 |
6017 |
0 |
0 |