SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_seed_hw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_flash_hw_if.u_sync_rma_req | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prog_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_escalation_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.u_lc_nvm_debug_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.85 | 97.12 | 94.40 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.96 | 100.00 | 93.75 | 92.11 | 98.94 | 100.00 | u_flash_hw_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.37 | 100.00 | 88.89 | 57.14 | 95.83 | 50.00 | u_prog_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.85 | 97.12 | 94.40 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
80.60 | 100.00 | 100.00 | 57.14 | 95.83 | 50.00 | u_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.56 | 97.67 | 86.00 | 100.00 | u_eflash |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 10400 | 10400 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 21570 |
gen_no_flops.OutputDelay_A | 756207414 | 754493810 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10400 | 10400 | 0 | 0 |
T1 | 10 | 10 | 0 | 0 |
T2 | 10 | 10 | 0 | 0 |
T3 | 10 | 10 | 0 | 0 |
T4 | 10 | 10 | 0 | 0 |
T5 | 10 | 10 | 0 | 0 |
T6 | 10 | 10 | 0 | 0 |
T11 | 10 | 10 | 0 | 0 |
T19 | 10 | 10 | 0 | 0 |
T20 | 10 | 10 | 0 | 0 |
T21 | 10 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 7171480 | 7170680 | 0 | 0 |
T2 | 785230 | 754110 | 0 | 0 |
T3 | 653070 | 652340 | 0 | 0 |
T4 | 16780 | 15430 | 0 | 0 |
T5 | 1422460 | 1420930 | 0 | 0 |
T6 | 1819060 | 1817110 | 0 | 0 |
T11 | 35450 | 27890 | 0 | 0 |
T19 | 77990 | 77180 | 0 | 0 |
T20 | 4070 | 3320 | 0 | 0 |
T21 | 61780 | 60170 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 21570 |
T1 | 5737184 | 5736520 | 0 | 24 |
T2 | 628184 | 602304 | 0 | 24 |
T3 | 522456 | 521848 | 0 | 24 |
T4 | 13424 | 12296 | 0 | 24 |
T5 | 1137968 | 1136696 | 0 | 24 |
T6 | 1455248 | 1453640 | 0 | 24 |
T7 | 0 | 0 | 0 | 24 |
T11 | 28360 | 22096 | 0 | 24 |
T19 | 62392 | 61720 | 0 | 24 |
T20 | 3256 | 2656 | 0 | 0 |
T21 | 49424 | 48088 | 0 | 24 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 756207414 | 754493810 | 0 | 0 |
T1 | 1434296 | 1434136 | 0 | 0 |
T2 | 157046 | 150822 | 0 | 0 |
T3 | 130614 | 130468 | 0 | 0 |
T4 | 3356 | 3086 | 0 | 0 |
T5 | 284492 | 284186 | 0 | 0 |
T6 | 363812 | 363422 | 0 | 0 |
T11 | 7090 | 5578 | 0 | 0 |
T19 | 15598 | 15436 | 0 | 0 |
T20 | 814 | 664 | 0 | 0 |
T21 | 12356 | 12034 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1040 | 1040 | 0 | 0 |
OutputsKnown_A | 378103751 | 377246949 | 0 | 0 |
gen_flops.OutputDelay_A | 378103751 | 377213022 | 0 | 2715 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103751 | 377246949 | 0 | 0 |
T1 | 717148 | 717068 | 0 | 0 |
T2 | 78523 | 75411 | 0 | 0 |
T3 | 65307 | 65234 | 0 | 0 |
T4 | 1678 | 1543 | 0 | 0 |
T5 | 142246 | 142093 | 0 | 0 |
T6 | 181906 | 181711 | 0 | 0 |
T11 | 3545 | 2789 | 0 | 0 |
T19 | 7799 | 7718 | 0 | 0 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6017 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103751 | 377213022 | 0 | 2715 |
T1 | 717148 | 717065 | 0 | 3 |
T2 | 78523 | 75288 | 0 | 3 |
T3 | 65307 | 65231 | 0 | 3 |
T4 | 1678 | 1537 | 0 | 3 |
T5 | 142246 | 142087 | 0 | 3 |
T6 | 181906 | 181705 | 0 | 3 |
T7 | 0 | 0 | 0 | 3 |
T11 | 3545 | 2762 | 0 | 3 |
T19 | 7799 | 7715 | 0 | 3 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6011 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1040 | 1040 | 0 | 0 |
OutputsKnown_A | 378103751 | 377246949 | 0 | 0 |
gen_flops.OutputDelay_A | 378103751 | 377213022 | 0 | 2715 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103751 | 377246949 | 0 | 0 |
T1 | 717148 | 717068 | 0 | 0 |
T2 | 78523 | 75411 | 0 | 0 |
T3 | 65307 | 65234 | 0 | 0 |
T4 | 1678 | 1543 | 0 | 0 |
T5 | 142246 | 142093 | 0 | 0 |
T6 | 181906 | 181711 | 0 | 0 |
T11 | 3545 | 2789 | 0 | 0 |
T19 | 7799 | 7718 | 0 | 0 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6017 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103751 | 377213022 | 0 | 2715 |
T1 | 717148 | 717065 | 0 | 3 |
T2 | 78523 | 75288 | 0 | 3 |
T3 | 65307 | 65231 | 0 | 3 |
T4 | 1678 | 1537 | 0 | 3 |
T5 | 142246 | 142087 | 0 | 3 |
T6 | 181906 | 181705 | 0 | 3 |
T7 | 0 | 0 | 0 | 3 |
T11 | 3545 | 2762 | 0 | 3 |
T19 | 7799 | 7715 | 0 | 3 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6011 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1040 | 1040 | 0 | 0 |
OutputsKnown_A | 378103751 | 377246949 | 0 | 0 |
gen_flops.OutputDelay_A | 378103751 | 377213022 | 0 | 2715 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103751 | 377246949 | 0 | 0 |
T1 | 717148 | 717068 | 0 | 0 |
T2 | 78523 | 75411 | 0 | 0 |
T3 | 65307 | 65234 | 0 | 0 |
T4 | 1678 | 1543 | 0 | 0 |
T5 | 142246 | 142093 | 0 | 0 |
T6 | 181906 | 181711 | 0 | 0 |
T11 | 3545 | 2789 | 0 | 0 |
T19 | 7799 | 7718 | 0 | 0 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6017 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103751 | 377213022 | 0 | 2715 |
T1 | 717148 | 717065 | 0 | 3 |
T2 | 78523 | 75288 | 0 | 3 |
T3 | 65307 | 65231 | 0 | 3 |
T4 | 1678 | 1537 | 0 | 3 |
T5 | 142246 | 142087 | 0 | 3 |
T6 | 181906 | 181705 | 0 | 3 |
T7 | 0 | 0 | 0 | 3 |
T11 | 3545 | 2762 | 0 | 3 |
T19 | 7799 | 7715 | 0 | 3 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6011 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1040 | 1040 | 0 | 0 |
OutputsKnown_A | 378103751 | 377246949 | 0 | 0 |
gen_flops.OutputDelay_A | 378103751 | 377213022 | 0 | 2715 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103751 | 377246949 | 0 | 0 |
T1 | 717148 | 717068 | 0 | 0 |
T2 | 78523 | 75411 | 0 | 0 |
T3 | 65307 | 65234 | 0 | 0 |
T4 | 1678 | 1543 | 0 | 0 |
T5 | 142246 | 142093 | 0 | 0 |
T6 | 181906 | 181711 | 0 | 0 |
T11 | 3545 | 2789 | 0 | 0 |
T19 | 7799 | 7718 | 0 | 0 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6017 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103751 | 377213022 | 0 | 2715 |
T1 | 717148 | 717065 | 0 | 3 |
T2 | 78523 | 75288 | 0 | 3 |
T3 | 65307 | 65231 | 0 | 3 |
T4 | 1678 | 1537 | 0 | 3 |
T5 | 142246 | 142087 | 0 | 3 |
T6 | 181906 | 181705 | 0 | 3 |
T7 | 0 | 0 | 0 | 3 |
T11 | 3545 | 2762 | 0 | 3 |
T19 | 7799 | 7715 | 0 | 3 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6011 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1040 | 1040 | 0 | 0 |
OutputsKnown_A | 378103751 | 377246949 | 0 | 0 |
gen_flops.OutputDelay_A | 378103751 | 377213022 | 0 | 2715 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103751 | 377246949 | 0 | 0 |
T1 | 717148 | 717068 | 0 | 0 |
T2 | 78523 | 75411 | 0 | 0 |
T3 | 65307 | 65234 | 0 | 0 |
T4 | 1678 | 1543 | 0 | 0 |
T5 | 142246 | 142093 | 0 | 0 |
T6 | 181906 | 181711 | 0 | 0 |
T11 | 3545 | 2789 | 0 | 0 |
T19 | 7799 | 7718 | 0 | 0 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6017 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103751 | 377213022 | 0 | 2715 |
T1 | 717148 | 717065 | 0 | 3 |
T2 | 78523 | 75288 | 0 | 3 |
T3 | 65307 | 65231 | 0 | 3 |
T4 | 1678 | 1537 | 0 | 3 |
T5 | 142246 | 142087 | 0 | 3 |
T6 | 181906 | 181705 | 0 | 3 |
T7 | 0 | 0 | 0 | 3 |
T11 | 3545 | 2762 | 0 | 3 |
T19 | 7799 | 7715 | 0 | 3 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6011 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1040 | 1040 | 0 | 0 |
OutputsKnown_A | 378103751 | 377246949 | 0 | 0 |
gen_flops.OutputDelay_A | 378103751 | 377213022 | 0 | 2715 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103751 | 377246949 | 0 | 0 |
T1 | 717148 | 717068 | 0 | 0 |
T2 | 78523 | 75411 | 0 | 0 |
T3 | 65307 | 65234 | 0 | 0 |
T4 | 1678 | 1543 | 0 | 0 |
T5 | 142246 | 142093 | 0 | 0 |
T6 | 181906 | 181711 | 0 | 0 |
T11 | 3545 | 2789 | 0 | 0 |
T19 | 7799 | 7718 | 0 | 0 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6017 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103751 | 377213022 | 0 | 2715 |
T1 | 717148 | 717065 | 0 | 3 |
T2 | 78523 | 75288 | 0 | 3 |
T3 | 65307 | 65231 | 0 | 3 |
T4 | 1678 | 1537 | 0 | 3 |
T5 | 142246 | 142087 | 0 | 3 |
T6 | 181906 | 181705 | 0 | 3 |
T7 | 0 | 0 | 0 | 3 |
T11 | 3545 | 2762 | 0 | 3 |
T19 | 7799 | 7715 | 0 | 3 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6011 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1040 | 1040 | 0 | 0 |
OutputsKnown_A | 378103707 | 377246905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 378103707 | 377246905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103707 | 377246905 | 0 | 0 |
T1 | 717148 | 717068 | 0 | 0 |
T2 | 78523 | 75411 | 0 | 0 |
T3 | 65307 | 65234 | 0 | 0 |
T4 | 1678 | 1543 | 0 | 0 |
T5 | 142246 | 142093 | 0 | 0 |
T6 | 181906 | 181711 | 0 | 0 |
T11 | 3545 | 2789 | 0 | 0 |
T19 | 7799 | 7718 | 0 | 0 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6017 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103707 | 377246905 | 0 | 0 |
T1 | 717148 | 717068 | 0 | 0 |
T2 | 78523 | 75411 | 0 | 0 |
T3 | 65307 | 65234 | 0 | 0 |
T4 | 1678 | 1543 | 0 | 0 |
T5 | 142246 | 142093 | 0 | 0 |
T6 | 181906 | 181711 | 0 | 0 |
T11 | 3545 | 2789 | 0 | 0 |
T19 | 7799 | 7718 | 0 | 0 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6017 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1040 | 1040 | 0 | 0 |
OutputsKnown_A | 378081092 | 377224290 | 0 | 0 |
gen_flops.OutputDelay_A | 378081092 | 377190513 | 0 | 2565 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378081092 | 377224290 | 0 | 0 |
T1 | 717148 | 717068 | 0 | 0 |
T2 | 78523 | 75411 | 0 | 0 |
T3 | 65307 | 65234 | 0 | 0 |
T4 | 1678 | 1543 | 0 | 0 |
T5 | 142246 | 142093 | 0 | 0 |
T6 | 181906 | 181711 | 0 | 0 |
T11 | 3545 | 2789 | 0 | 0 |
T19 | 7799 | 7718 | 0 | 0 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6017 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378081092 | 377190513 | 0 | 2565 |
T1 | 717148 | 717065 | 0 | 3 |
T2 | 78523 | 75288 | 0 | 3 |
T3 | 65307 | 65231 | 0 | 3 |
T4 | 1678 | 1537 | 0 | 3 |
T5 | 142246 | 142087 | 0 | 3 |
T6 | 181906 | 181705 | 0 | 3 |
T7 | 0 | 0 | 0 | 3 |
T11 | 3545 | 2762 | 0 | 3 |
T19 | 7799 | 7715 | 0 | 3 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6011 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1040 | 1040 | 0 | 0 |
OutputsKnown_A | 378103707 | 377246905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 378103707 | 377246905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103707 | 377246905 | 0 | 0 |
T1 | 717148 | 717068 | 0 | 0 |
T2 | 78523 | 75411 | 0 | 0 |
T3 | 65307 | 65234 | 0 | 0 |
T4 | 1678 | 1543 | 0 | 0 |
T5 | 142246 | 142093 | 0 | 0 |
T6 | 181906 | 181711 | 0 | 0 |
T11 | 3545 | 2789 | 0 | 0 |
T19 | 7799 | 7718 | 0 | 0 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6017 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103707 | 377246905 | 0 | 0 |
T1 | 717148 | 717068 | 0 | 0 |
T2 | 78523 | 75411 | 0 | 0 |
T3 | 65307 | 65234 | 0 | 0 |
T4 | 1678 | 1543 | 0 | 0 |
T5 | 142246 | 142093 | 0 | 0 |
T6 | 181906 | 181711 | 0 | 0 |
T11 | 3545 | 2789 | 0 | 0 |
T19 | 7799 | 7718 | 0 | 0 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6017 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1040 | 1040 | 0 | 0 |
OutputsKnown_A | 378103707 | 377246905 | 0 | 0 |
gen_flops.OutputDelay_A | 378103707 | 377212993 | 0 | 2715 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1040 | 1040 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103707 | 377246905 | 0 | 0 |
T1 | 717148 | 717068 | 0 | 0 |
T2 | 78523 | 75411 | 0 | 0 |
T3 | 65307 | 65234 | 0 | 0 |
T4 | 1678 | 1543 | 0 | 0 |
T5 | 142246 | 142093 | 0 | 0 |
T6 | 181906 | 181711 | 0 | 0 |
T11 | 3545 | 2789 | 0 | 0 |
T19 | 7799 | 7718 | 0 | 0 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6017 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378103707 | 377212993 | 0 | 2715 |
T1 | 717148 | 717065 | 0 | 3 |
T2 | 78523 | 75288 | 0 | 3 |
T3 | 65307 | 65231 | 0 | 3 |
T4 | 1678 | 1537 | 0 | 3 |
T5 | 142246 | 142087 | 0 | 3 |
T6 | 181906 | 181705 | 0 | 3 |
T7 | 0 | 0 | 0 | 3 |
T11 | 3545 | 2762 | 0 | 3 |
T19 | 7799 | 7715 | 0 | 3 |
T20 | 407 | 332 | 0 | 0 |
T21 | 6178 | 6011 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |