Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	267510	1		T1	1		T2	1		T3	3451
all_values[1]	267510	1		T1	1		T2	1		T3	3451
all_values[2]	267510	1		T1	1		T2	1		T3	3451
all_values[3]	267510	1		T1	1		T2	1		T3	3451
all_values[4]	267510	1		T1	1		T2	1		T3	3451
all_values[5]	267510	1		T1	1		T2	1		T3	3451

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	541100	1		T1	6		T2	6		T3	6906
auto[1]	1063960	1		T3	13800		T16	6120		T6	15280

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	784230	1		T1	4		T2	4		T3	10354
auto[1]	820830	1		T1	2		T2	2		T3	10352

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	267355	1		T1	1		T2	1		T3	3451
all_values[0]	auto[1]	auto[1]	155	1		T245	5		T246	4		T247	4
all_values[1]	auto[0]	auto[1]	267352	1		T1	1		T2	1		T3	3451
all_values[1]	auto[1]	auto[1]	158	1		T245	8		T246	2		T247	1
all_values[2]	auto[0]	auto[0]	1547	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	53	1		T245	2		T246	3		T312	1
all_values[2]	auto[1]	auto[0]	265855	1		T3	3450		T16	1530		T6	3820
all_values[2]	auto[1]	auto[1]	55	1		T245	1		T246	1		T247	1
all_values[3]	auto[0]	auto[0]	1546	1		T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	55	1		T245	2		T246	1		T312	1
all_values[3]	auto[1]	auto[0]	84375	1		T3	1725		T16	1530		T6	67
all_values[3]	auto[1]	auto[1]	181534	1		T3	1725		T6	3753		T33	216
all_values[4]	auto[0]	auto[0]	1110	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	485	1		T4	1		T26	1		T20	1
all_values[4]	auto[1]	auto[0]	162467	1		T3	1725		T16	1		T6	3289
all_values[4]	auto[1]	auto[1]	103448	1		T3	1725		T16	1529		T6	531
all_values[5]	auto[0]	auto[0]	1487	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	110	1		T35	1		T36	1		T37	1
all_values[5]	auto[1]	auto[0]	265843	1		T3	3450		T16	1530		T6	3820
all_values[5]	auto[1]	auto[1]	70	1		T245	3		T246	1		T247	2