Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmEflashReqFifoRptrCheck_A	0	0	395323925	0	0	0
tb.dut.FpvSecCmEflashReqFifoWptrCheck_A	0	0	395323925	0	0	0
tb.dut.FpvSecCmEflashRspFifoRptrCheck_A	0	0	395323925	0	0	0
tb.dut.FpvSecCmEflashRspFifoWptrCheck_A	0	0	395323925	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoRptrCheck_A	0	0	395323925	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoWptrCheck_A	0	0	395323925	0	0	0
tb.dut.FpvSecCmRdReqFifoRptrCheck_A	0	0	395323925	0	0	0
tb.dut.FpvSecCmRdReqFifoWptrCheck_A	0	0	395323925	0	0	0
tb.dut.FpvSecCmRdSramReqFifoRptrCheck_A	0	0	395323925	0	0	0
tb.dut.FpvSecCmRdSramReqFifoWptrCheck_A	0	0	395323925	0	0	0
tb.dut.PrimRspPayLoad_A	0	0	395323925	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	395323925	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	395323925	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	395323925	0	0	1037
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	395323925	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	395323925	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	395323925	0	0	1037
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	395323925	0	0	1037
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	395323925	0	0	1037
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	395323925	0	0	1037
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	395323925	0	0	1037
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	395323925	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	395323925	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	395323925	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	395323925	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	395323925	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	395323925	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	395323925	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	395323925	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	1042	1042	0	0
tb.dut.FlashAddrKnown_A	0	0	395323925	264627682	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	395323925	394485667	0	0
tb.dut.FlashKnownO_A	0	0	395323925	394485667	0	0
tb.dut.FlashProgKnown_A	0	0	395323925	158175575	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	395323925	394485667	0	0
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	395323925	50	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	395323925	50	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	395323925	50	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	395323925	50	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	395323925	50	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	395323925	50	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	395323925	50	0	0
tb.dut.FpvSecCmRdRspFifoRptrCheck_A	0	0	395323925	50	0	0
tb.dut.FpvSecCmRdRspFifoWptrCheck_A	0	0	395323925	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	395323925	50	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	395323925	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	395323925	50	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	395323925	50	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	395323925	50	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	395323925	50	0	0
tb.dut.IntrErrO_A	0	0	395323925	394485667	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	395323925	394485667	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	395323925	394485667	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	395323925	394485667	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	395323925	394485667	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	395323925	394485667	0	0
tb.dut.MemRspPayLoad_A	0	0	395323925	5348526	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	395323925	394485667	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	395323925	394485667	0	0
tb.dut.MemTlDValidKnownO_A	0	0	395323925	394485667	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	395323925	394485667	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	395323925	394485667	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	395323925	394485667	0	0
tb.dut.RspPayLoad_A	0	0	395116005	41852686	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	395323925	394485667	0	0
tb.dut.TdoEnIsOne_A	0	0	395323925	394485667	0	0
tb.dut.TdoKnown_A	0	0	395323925	394485667	0	0
tb.dut.TlAReadyKnownO_A	0	0	395323925	394485667	0	0
tb.dut.TlDValidKnownO_A	0	0	395323925	394485667	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	398102096	4388	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	398102096	2955	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	398102096	4014	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	398102096	3807	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	398102096	4089	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	398102096	3253	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	398102096	3727	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	398102096	3573	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	398102096	3531	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	398102096	2709	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	398102096	4307	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	398102096	3611	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	398102096	2339	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	398102096	2625	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	398102096	2626	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	398102096	3241	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	398102096	2148	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	398102096	3247	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	398102096	2068	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	398102096	2761	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	398102096	2818	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	398102096	3034	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	398102096	4209	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	398102096	2969	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	398102096	3854	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	398102096	2959	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	398102096	2462	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	398102096	2867	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	398102096	3530	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	398102096	2484	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	398102096	4132	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	398102096	3626	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	398102096	3741	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	398102096	3394	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	398102096	4349	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	398102096	3681	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	398102096	3627	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	398102096	3236	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	398102096	2507	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	398102096	2337	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	398102096	2822	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	398102096	3092	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	398102096	3258	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	398102096	2803	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	398102096	1932	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	398102096	2520	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	398102096	1936	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	398102096	2445	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	398102096	4104	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	398102096	3086	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	398102096	3623	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	398102096	3891	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	398102096	2961	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	398102096	3492	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	398102096	3417	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	398102096	3589	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	398102096	3312	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	398102096	3039	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	398102096	3201	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	398102096	3147	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	398102096	2975	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	398102096	2595	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	398102096	3188	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	398102096	3346	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	398102096	2915	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	398102096	1992	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	398102096	2635	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	398102096	3589	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	398102096	2502	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	398102096	4045	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	398102096	3303	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	398102096	3433	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	398102096	3362	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	398102096	3474	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	398102096	4331	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	398102096	3956	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	398102096	4233	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	398102096	1847	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	398102096	2385	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	398102096	1926	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	398102096	3265	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	398102096	2604	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	398102096	3222	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	398102096	2888	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	398102096	3054	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	398102096	2021	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	398102096	2470	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	395323925	50	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	395323925	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	395323925	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	395323925	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	395323925	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	395323925	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	395323925	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	395323925	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	395323925	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	395323925	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	395323925	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	395323925	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	395323925	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	395323925	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	395323925	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	395323925	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	395323925	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	395323925	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	395323925	20	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	398102044	33215203	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	398102044	397183802	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	398102044	397183802	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	398102044	42746272	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	398102044	397183802	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	398102044	397183802	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
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