Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	239111	1		T1	7		T3	901		T4	15
auto[FlashEraseBank]	265357	1		T1	8		T3	824		T4	4

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	256211	1		T1	14		T3	1725		T4	7
auto[FlashOpProgram]	228588	1		T1	1		T4	5		T5	343
auto[FlashOpErase]	15669	1		T4	7		T5	343		T26	2
auto[FlashOpInvalid]	4000	1		T212	200		T213	200		T278	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	256211	1		T1	14		T3	1725		T4	7
op[FlashOpProgram]	228588	1		T1	1		T4	5		T5	343
op[FlashOpErase]	15669	1		T4	7		T5	343		T26	2
read_erase_read	557	1		T10	4		T30	1		T25	5
read_prog_read	827	1		T1	1		T4	1		T17	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	364269	1		T1	6		T3	1725		T4	18
auto[FlashPartInfo]	136523	1		T1	5		T4	1		T5	1375
auto[FlashPartInfo1]	868	1		T20	7		T39	4		T44	64
auto[FlashPartInfo2]	2808	1		T1	4		T16	8		T20	6

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	184227	1		T1	6		T3	1725		T4	7
auto[FlashPartData]	auto[FlashOpProgram]	172583	1		T4	4		T16	1314		T17	1
auto[FlashPartData]	auto[FlashOpErase]	3557	1		T4	7		T26	2		T20	2
auto[FlashPartData]	auto[FlashOpInvalid]	3902	1		T212	198		T213	198		T278	200
auto[FlashPartInfo]	auto[FlashOpRead]	69420	1		T1	5		T5	689		T6	531
auto[FlashPartInfo]	auto[FlashOpProgram]	54943	1		T4	1		T5	343		T16	207
auto[FlashPartInfo]	auto[FlashOpErase]	12078	1		T5	343		T20	1		T21	12
auto[FlashPartInfo]	auto[FlashOpInvalid]	82	1		T212	2		T213	2		T156	8
auto[FlashPartInfo1]	auto[FlashOpRead]	700	1		T20	7		T39	4		T44	32
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T44	32		T70	1		T130	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T132	1		T78	1		T419	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T419	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1864	1		T1	3		T20	2		T34	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	899	1		T1	1		T16	8		T20	4
auto[FlashPartInfo2]	auto[FlashOpErase]	31	1		T92	2		T261	3		T154	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	14	1		T156	2		T420	2		T421	2