Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30899	1		T4	4		T5	716		T19	2
auto[1]	44	1		T92	5		T93	3		T94	4
auto[2]	51	1		T92	1		T139	7		T55	4
auto[3]	232	1		T17	1		T34	1		T61	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7811	1		T4	1		T5	179		T19	1
evic_idx[1]	7804	1		T4	1		T5	179		T17	1
evic_idx[2]	7806	1		T4	1		T5	179		T34	1
evic_idx[3]	7805	1		T4	1		T5	179		T21	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30303	1		T5	716		T21	4		T103	232
evic_op[2]	347	1		T17	1		T19	2		T26	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[2]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7517	1		T5	179		T21	1		T103	58
evic_idx[0]	evic_op[1]	auto[1]	7	1		T92	2		T329	1		T330	2
evic_idx[0]	evic_op[1]	auto[2]	8	1		T139	3		T329	3		T331	2
evic_idx[0]	evic_op[1]	auto[3]	52	1		T92	4		T112	6		T140	7
evic_idx[0]	evic_op[2]	auto[0]	71	1		T19	1		T30	1		T208	1
evic_idx[0]	evic_op[2]	auto[1]	6	1		T94	1		T332	1		T333	1
evic_idx[0]	evic_op[2]	auto[2]	1	1		T334	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	5	1		T335	1		T336	1		T337	1
evic_idx[1]	evic_op[1]	auto[0]	7517	1		T5	179		T21	1		T103	58
evic_idx[1]	evic_op[1]	auto[1]	7	1		T92	1		T329	1		T330	2
evic_idx[1]	evic_op[1]	auto[2]	3	1		T92	1		T329	2		-	-
evic_idx[1]	evic_op[1]	auto[3]	41	1		T92	5		T112	3		T140	3
evic_idx[1]	evic_op[2]	auto[0]	72	1		T19	1		T26	1		T30	1
evic_idx[1]	evic_op[2]	auto[1]	7	1		T93	1		T94	1		T338	1
evic_idx[1]	evic_op[2]	auto[2]	1	1		T334	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	12	1		T17	1		T208	1		T265	1
evic_idx[2]	evic_op[1]	auto[0]	7517	1		T5	179		T21	1		T103	58
evic_idx[2]	evic_op[1]	auto[1]	4	1		T92	1		T330	1		T339	1
evic_idx[2]	evic_op[1]	auto[2]	7	1		T139	1		T329	2		T331	3
evic_idx[2]	evic_op[1]	auto[3]	47	1		T92	4		T112	3		T140	3
evic_idx[2]	evic_op[2]	auto[0]	69	1		T30	1		T208	1		T196	1
evic_idx[2]	evic_op[2]	auto[1]	5	1		T93	1		T94	1		T340	1
evic_idx[2]	evic_op[2]	auto[3]	13	1		T34	1		T61	1		T50	1
evic_idx[3]	evic_op[1]	auto[0]	7516	1		T5	179		T21	1		T103	58
evic_idx[3]	evic_op[1]	auto[1]	3	1		T92	1		T330	1		T339	1
evic_idx[3]	evic_op[1]	auto[2]	6	1		T139	3		T329	2		T331	1
evic_idx[3]	evic_op[1]	auto[3]	51	1		T92	4		T112	4		T140	5
evic_idx[3]	evic_op[2]	auto[0]	68	1		T30	1		T215	4		T70	1
evic_idx[3]	evic_op[2]	auto[1]	5	1		T93	1		T94	1		T341	1
evic_idx[3]	evic_op[2]	auto[2]	1	1		T334	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	11	1		T138	1		T342	1		T343	1