Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	1159	1		T318	1159		-	-		-	-
rd_lvl[2]	43385	1		T6	1139		T318	2579		T319	12339
rd_lvl[3]	14067	1		T6	717		T320	891		T318	715
rd_lvl[4]	21496	1		T6	141		T320	658		T318	1875
rd_lvl[5]	9300	1		T6	448		T33	159		T321	2144
rd_lvl[6]	16000	1		T6	465		T33	57		T217	557
rd_lvl[7]	9368	1		T6	74		T217	211		T297	587
rd_lvl[8]	17485	1		T6	72		T297	293		T322	847
rd_lvl[9]	5600	1		T6	72		T217	133		T323	569
rd_lvl[10]	6696	1		T217	132		T323	1020		T297	81
rd_lvl[11]	5566	1		T31	573		T324	319		T304	67
rd_lvl[12]	3128	1		T31	1103		T324	171		T304	21
rd_lvl[13]	4120	1		T325	173		T320	155		T326	443
rd_lvl[14]	10096	1		T3	1358		T31	1		T32	1463
rd_lvl[15]	3857	1		T3	367		T32	224		T327	548