Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	267510	1		T1	1		T2	1		T3	3451
all_pins[1]	267510	1		T1	1		T2	1		T3	3451
all_pins[2]	267510	1		T1	1		T2	1		T3	3451
all_pins[3]	267510	1		T1	1		T2	1		T3	3451
all_pins[4]	267510	1		T1	1		T2	1		T3	3451
all_pins[5]	267510	1		T1	1		T2	1		T3	3451

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1313417	1		T1	6		T2	6		T3	17256
values[0x1]	291643	1		T3	3450		T16	1529		T6	3673
transitions[0x0=>0x1]	260447	1		T3	3450		T16	1529		T6	3257
transitions[0x1=>0x0]	260433	1		T3	3450		T16	1529		T6	3257

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	267355	1		T1	1		T2	1		T3	3451
all_pins[0]	values[0x1]	155	1		T245	5		T246	4		T247	4
all_pins[0]	transitions[0x0=>0x1]	78	1		T246	2		T247	4		T313	3
all_pins[0]	transitions[0x1=>0x0]	81	1		T245	3		T247	1		T313	2
all_pins[1]	values[0x0]	267352	1		T1	1		T2	1		T3	3451
all_pins[1]	values[0x1]	158	1		T245	8		T246	2		T247	1
all_pins[1]	transitions[0x0=>0x1]	130	1		T245	7		T246	2		T312	1
all_pins[1]	transitions[0x1=>0x0]	4195	1		T327	1104		T308	3		T99	1087
all_pins[2]	values[0x0]	263287	1		T1	1		T2	1		T3	3451
all_pins[2]	values[0x1]	4223	1		T327	1104		T308	3		T99	1087
all_pins[2]	transitions[0x0=>0x1]	45	1		T245	1		T246	1		T247	1
all_pins[2]	transitions[0x1=>0x0]	171524	1		T3	1725		T6	3128		T33	216
all_pins[3]	values[0x0]	91808	1		T1	1		T2	1		T3	1726
all_pins[3]	values[0x1]	175702	1		T3	1725		T6	3128		T33	216
all_pins[3]	transitions[0x0=>0x1]	148849	1		T3	1725		T6	2712		T33	198
all_pins[3]	transitions[0x1=>0x0]	84482	1		T3	1725		T16	1529		T6	129
all_pins[4]	values[0x0]	156175	1		T1	1		T2	1		T3	1726
all_pins[4]	values[0x1]	111335	1		T3	1725		T16	1529		T6	545
all_pins[4]	transitions[0x0=>0x1]	111316	1		T3	1725		T16	1529		T6	545
all_pins[4]	transitions[0x1=>0x0]	51	1		T245	2		T246	1		T247	1
all_pins[5]	values[0x0]	267440	1		T1	1		T2	1		T3	3451
all_pins[5]	values[0x1]	70	1		T245	3		T246	1		T247	2
all_pins[5]	transitions[0x0=>0x1]	29	1		T245	2		T312	1		T313	1
all_pins[5]	transitions[0x1=>0x0]	100	1		T245	3		T246	3		T247	2