Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T245	7		T246	7		T247	4
all_values[1]	278	1		T245	7		T246	7		T247	4
all_values[2]	278	1		T245	7		T246	7		T247	4
all_values[3]	278	1		T245	7		T246	7		T247	4
all_values[4]	278	1		T245	7		T246	7		T247	4
all_values[5]	278	1		T245	7		T246	7		T247	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	910	1		T245	16		T246	25		T247	13
auto[1]	758	1		T245	26		T246	17		T247	11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	545	1		T245	12		T246	15		T247	7
auto[1]	1123	1		T245	30		T246	27		T247	17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	975	1		T245	24		T246	24		T247	15
auto[1]	693	1		T245	18		T246	18		T247	9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	88	1		T245	1		T246	1		T247	1
all_values[0]	auto[0]	auto[1]	auto[1]	70	1		T245	3		T246	2		T247	1
all_values[0]	auto[1]	auto[0]	auto[1]	65	1		T245	2		T246	2		T247	1
all_values[0]	auto[1]	auto[1]	auto[1]	55	1		T245	1		T246	2		T247	1
all_values[1]	auto[0]	auto[0]	auto[1]	74	1		T246	2		T247	2		T312	1
all_values[1]	auto[0]	auto[1]	auto[1]	80	1		T245	2		T246	1		T247	1
all_values[1]	auto[1]	auto[0]	auto[1]	78	1		T246	3		T247	1		T312	2
all_values[1]	auto[1]	auto[1]	auto[1]	46	1		T245	5		T246	1		T312	1
all_values[2]	auto[0]	auto[0]	auto[0]	101	1		T245	3		T246	2		T247	1
all_values[2]	auto[0]	auto[1]	auto[0]	69	1		T245	1		T246	1		T247	2
all_values[2]	auto[1]	auto[0]	auto[1]	52	1		T245	3		T246	3		T247	1
all_values[2]	auto[1]	auto[1]	auto[1]	56	1		T246	1		T312	2		T313	2
all_values[3]	auto[0]	auto[0]	auto[0]	89	1		T245	2		T246	1		T247	2
all_values[3]	auto[0]	auto[1]	auto[0]	81	1		T245	3		T246	5		T247	1
all_values[3]	auto[1]	auto[0]	auto[1]	68	1		T245	1		T246	1		T312	1
all_values[3]	auto[1]	auto[1]	auto[1]	40	1		T245	1		T247	1		T314	1
all_values[4]	auto[0]	auto[0]	auto[0]	61	1		T245	1		T246	2		T247	1
all_values[4]	auto[0]	auto[0]	auto[1]	26	1		T245	1		T246	1		T315	1
all_values[4]	auto[0]	auto[1]	auto[0]	56	1		T245	2		T246	1		T312	4
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T245	1		T246	1		T247	1
all_values[4]	auto[1]	auto[0]	auto[1]	63	1		T245	1		T246	2		T247	1
all_values[4]	auto[1]	auto[1]	auto[1]	42	1		T245	1		T247	1		T315	2
all_values[5]	auto[0]	auto[0]	auto[0]	41	1		T246	1		T312	2		T316	1
all_values[5]	auto[0]	auto[0]	auto[1]	32	1		T245	1		T246	1		T247	1
all_values[5]	auto[0]	auto[1]	auto[0]	47	1		T246	2		T313	1		T317	2
all_values[5]	auto[0]	auto[1]	auto[1]	30	1		T245	3		T247	1		T312	1
all_values[5]	auto[1]	auto[0]	auto[1]	72	1		T246	3		T247	1		T316	2
all_values[5]	auto[1]	auto[1]	auto[1]	56	1		T245	3		T247	1		T312	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal