Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23148855	1		T1	65		T2	502		T3	391
full_word	7822457	1		T1	43		T2	3		T3	168

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30971052	1		T1	108		T2	505		T3	559
auto[TlIntgErrCmd]	92	1		T101	3		T102	1		T255	5
auto[TlIntgErrData]	79	1		T101	4		T102	2		T255	2
auto[TlIntgErrBoth]	89	1		T101	3		T102	7		T255	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26440627	1		T1	58		T2	497		T3	471
auto[1]	4530685	1		T1	50		T2	8		T3	88

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22460034	1		T1	57		T2	496		T3	373
auto[TlIntgErrNone]	partial	auto[1]	688581	1		T1	8		T2	6		T3	18
auto[TlIntgErrNone]	full_word	auto[0]	3980478	1		T1	1		T2	1		T3	98
auto[TlIntgErrNone]	full_word	auto[1]	3841959	1		T1	42		T2	2		T3	70
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T101	1		T255	4		T274	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T102	1		T255	1		T274	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T368	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T101	2		T364	2		T367	1
auto[TlIntgErrData]	partial	auto[0]	34	1		T101	4		T102	2		T272	3
auto[TlIntgErrData]	partial	auto[1]	36	1		T255	2		T274	4		T268	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T272	1		T364	1		T369	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T272	1		T364	1		T363	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T101	2		T102	2		T274	1
auto[TlIntgErrBoth]	partial	auto[1]	43	1		T101	1		T102	4		T255	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T366	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T102	1		T370	2		T371	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18689	1		T61	83		T103	1105		T104	1230
full_word	3755644	1		T1	22		T3	7		T4	9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3774088	1		T1	22		T3	7		T4	9
auto[TlIntgErrCmd]	95	1		T101	4		T102	3		T255	3
auto[TlIntgErrData]	84	1		T101	2		T102	4		T255	2
auto[TlIntgErrBoth]	66	1		T101	4		T102	3		T255	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3750203	1		T1	22		T3	7		T4	9
auto[1]	24130	1		T61	98		T103	1233		T104	1437

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1317	1		T61	7		T103	95		T104	59
auto[TlIntgErrNone]	partial	auto[1]	17142	1		T61	76		T103	1010		T104	1171
auto[TlIntgErrNone]	full_word	auto[0]	3748787	1		T1	22		T3	7		T4	9
auto[TlIntgErrNone]	full_word	auto[1]	6842	1		T61	22		T103	223		T104	266
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T101	1		T102	1		T272	3
auto[TlIntgErrCmd]	partial	auto[1]	64	1		T101	2		T102	2		T255	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T363	1		T265	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T101	1		T274	1		-	-
auto[TlIntgErrData]	partial	auto[0]	36	1		T101	2		T102	2		T274	2
auto[TlIntgErrData]	partial	auto[1]	40	1		T102	2		T255	2		T274	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T364	1		T370	1		T368	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T274	1		T268	1		T272	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1		T101	2		T102	2		T255	2
auto[TlIntgErrBoth]	partial	auto[1]	35	1		T101	2		T255	2		T274	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T102	1		T364	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T272	1		-	-		-	-