Module Definition
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Module : flash_ctrl_erase
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_erase.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_ctrl_erase 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_ctrl_erase

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_erase
Line No.TotalCoveredPercent
TOTAL99100.00
CONT_ASSIGN4300
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_erase.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_erase.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 unreachable
46 1 1
49 1 1
50 1 1
51 1 1
56 1 1
57 1 1
58 1 1
62 1 1
66 1 1


Cond Coverage for Module : flash_ctrl_erase
TotalCoveredPercent
Conditions1616100.00
Logical1616100.00
Non-Logical00
Event00

 LINE       43
 EXPRESSION (op_start_i & op_addr_oob_i)
             -----1----   ------2------
-1--2-StatusTests
01Unreachable
10CoveredT2,T8,T5
11Unreachable

 LINE       46
 EXPRESSION (flash_req_o & (flash_done_i | oob_err))
             -----1-----   ------------2-----------
-1--2-StatusTests
01CoveredT6,T20,T28
10CoveredT2,T8,T5
11CoveredT8,T5,T9

 LINE       46
 SUB-EXPRESSION (flash_done_i | oob_err)
                 ------1-----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT8,T5,T9

 LINE       50
 EXPRESSION (op_done_o & oob_err)
             ----1----   ---2---
-1--2-StatusTests
01Unreachable
10CoveredT8,T5,T9
11Unreachable

 LINE       51
 EXPRESSION (op_done_o & flash_mp_err_i)
             ----1----   -------2------
-1--2-StatusTests
01CoveredT6,T20,T28
10CoveredT8,T5,T9
11CoveredT20,T7,T40

 LINE       56
 EXPRESSION (op_start_i & ((~op_addr_oob_i)))
             -----1----   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT2,T8,T5

 LINE       58
 EXPRESSION ((op_type_i == FlashErasePage) ? ((op_addr_i & PageAddrMask)) : ((op_addr_i & BankAddrMask)))
             --------------1--------------
-1-StatusTests
0CoveredT3,T4,T8
1CoveredT1,T2,T3

 LINE       58
 SUB-EXPRESSION (op_type_i == FlashErasePage)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : flash_ctrl_erase
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 58 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_erase.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_erase.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 58 ((op_type_i == FlashErasePage)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T8

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%