Unified Coverage Report :: Module :: flash_phy_core

Module : flash_phy_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.68	100.00	90.57		100.00	97.83	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core	96.55	100.00	84.91		100.00	97.83	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core	97.49	100.00	89.62		100.00	97.83	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	84.91		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.21	97.07	92.91	96.90	100.00	99.29	97.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.67	86.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	98.65	100.00	96.92	95.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	93.98	75.93	100.00			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.02	97.64	93.24	100.00		99.37	94.83
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.49	100.00	89.62		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.79	97.07	93.32	100.00	100.00	99.29	97.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.67	86.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	99.49	100.00	96.92	100.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	93.98	75.93	100.00			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.03	97.64	93.32	100.00		99.37	94.83
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	152	6	6	100.00
ALWAYS	165	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	203	4	4	100.00
ALWAYS	215	6	6	100.00
ALWAYS	229	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	325	29	29	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
165	3	3
196	1	1
200	1	1
203	1	1
204	1	1
205	1	1
206	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
277	1	1
280	1	1
281	1	1
282	1	1
287	1	1
317	1	1
321	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
			MISSING_ELSE
347	1	1
348	1	1
349	1	1
			MISSING_ELSE
356	1	1
357	1	1
358	1	1
359	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
374	1	1
375	1	1
388	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
415	1	1
428	1	1
523	1	1
550	1	1
551	1	1
552	1	1
553	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
568	1	1
585	1	1
586	1	1
587	1	1

---

Cond Coverage for Module : flash_phy_core

	Total	Covered	Percent
Conditions	106	96	90.57
Logical	106	96	90.57
Non-Logical	0	0
Event	0	0

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T205,T15,T217

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T205,T15,T217

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T8,T9
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T53,T54,T60
1	1	1	Covered	T1,T3,T4

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T70
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T69
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T9,T6

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T2,T8,T5
1	1	Covered	T3,T4,T8

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T54,T60
1	0	Not Covered

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T53,T54,T60

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T8

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T5,T9

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T64,T65
1	0	Covered	T2,T8,T5

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Not Covered

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T18,T19

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

---

FSM Coverage for Module : flash_phy_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	341	Covered	T2,T8,T5
StCtrlProg	339	Covered	T3,T4,T8
StCtrlRead	337	Covered	T1,T2,T3
StDisable	335	Covered	T1,T13,T14
StIdle	349	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	369	Covered	T2,T8,T5
StCtrlProg->StIdle	359	Covered	T3,T4,T8
StCtrlRead->StIdle	349	Covered	T1,T2,T3
StIdle->StCtrl	341	Covered	T2,T8,T5
StIdle->StCtrlProg	339	Covered	T3,T4,T8
StIdle->StCtrlRead	337	Covered	T1,T2,T3
StIdle->StDisable	335	Covered	T1,T13,T14

---

Branch Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	317	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	552	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	431	2	1	50.00
IF	152	4	4	100.00
IF	165	2	2	100.00
IF	203	3	3	100.00
IF	215	4	4	100.00
IF	229	4	4	100.00
CASE	331	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	317	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	552	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))
-2-:	154	if (ctrl_rsp_vld)
-3-:	156	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T8,T9,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if ((!rst_ni))
-2-:	205	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T205,T15,T217
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	217	if ((host_outstanding == '0))
-3-:	219	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T15,T16
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	229	if ((!rst_ni))
-2-:	231	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	233	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T15,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	case (state_q)
-2-:	334	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	336	if ((ctrl_gnt && rd_i))
-4-:	338	if ((ctrl_gnt && prog_i))
-5-:	340	if (ctrl_gnt)
-6-:	347	if (rd_stage_data_valid)
-7-:	357	if (prog_ack)
-8-:	367	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T1,T13,T14
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T3,T4,T8
StIdle	0	0	0	1	-	-	-	Covered	T2,T8,T5
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T3,T4,T8
StCtrlProg	-	-	-	-	-	0	-	Covered	T3,T4,T8
StCtrl	-	-	-	-	-	-	1	Covered	T8,T5,T9
StCtrl	-	-	-	-	-	-	0	Covered	T2,T8,T5
StDisable	-	-	-	-	-	-	-	Covered	T1,T13,T14
default	-	-	-	-	-	-	-	Covered	T17,T18,T19

---

Assert Coverage for Module : flash_phy_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	785669470	2933588	0	0
CtrlPrio_A	785669470	2933588	0	0
HostTransIdleChk_A	785669470	43850678	0	0
NoRemainder_A	2116	2116	0	0
OneHotReqs_A	785669470	783933280	0	0
Pow2Multiple_A	2116	2116	0	0
RdTxnCheck_A	785194294	783458104	0	0
u_state_regs_A	785669470	783933280	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785669470	2933588	0	0
T5	353826	0	0	0
T6	380354	7085	0	0
T7	360060	0	0	0
T8	136697	84	0	0
T9	5929	0	0	0
T13	1652	0	0	0
T20	17174	0	0	0
T23	0	7753	0	0
T24	2546	0	0	0
T28	115264	5059	0	0
T33	0	79001	0	0
T34	0	76838	0	0
T35	0	9162	0	0
T40	10692	0	0	0
T55	1794	0	0	0
T59	0	14105	0	0
T83	10592	0	0	0
T84	4683	0	0	0
T138	0	1471	0	0
T208	0	10980	0	0
T218	0	6733	0	0
T219	0	6107	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785669470	2933588	0	0
T5	353826	0	0	0
T6	380354	7085	0	0
T7	360060	0	0	0
T8	136697	84	0	0
T9	5929	0	0	0
T13	1652	0	0	0
T20	17174	0	0	0
T23	0	7753	0	0
T24	2546	0	0	0
T28	115264	5059	0	0
T33	0	79001	0	0
T34	0	76838	0	0
T35	0	9162	0	0
T40	10692	0	0	0
T55	1794	0	0	0
T59	0	14105	0	0
T83	10592	0	0	0
T84	4683	0	0	0
T138	0	1471	0	0
T208	0	10980	0	0
T218	0	6733	0	0
T219	0	6107	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785669470	43850678	0	0
T1	657	55	0	0
T2	3027	0	0	0
T3	3346	32	0	0
T4	5758	36	0	0
T5	707652	0	0	0
T6	380354	85421	0	0
T7	180030	0	0	0
T8	273394	621	0	0
T9	11858	331	0	0
T13	1652	0	0	0
T20	17174	36	0	0
T22	0	209	0	0
T24	0	20	0	0
T28	57632	58155	0	0
T40	0	69	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2116	2116	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T13	2	2	0	0
T20	2	2	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785669470	783933280	0	0
T1	1314	1116	0	0
T2	6054	4776	0	0
T3	3346	3116	0	0
T4	5758	5426	0	0
T5	707652	675758	0	0
T6	380354	380244	0	0
T8	273394	273264	0	0
T9	11858	11700	0	0
T13	1652	1460	0	0
T20	17174	16942	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2116	2116	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T13	2	2	0	0
T20	2	2	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785194294	783458104	0	0
T1	1314	1116	0	0
T2	6054	4776	0	0
T3	3346	3116	0	0
T4	5758	5426	0	0
T5	707652	675758	0	0
T6	380354	380244	0	0
T8	273394	273264	0	0
T9	11858	11700	0	0
T13	1652	1460	0	0
T20	17174	16942	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785669470	783933280	0	0
T1	1314	1116	0	0
T2	6054	4776	0	0
T3	3346	3116	0	0
T4	5758	5426	0	0
T5	707652	675758	0	0
T6	380354	380244	0	0
T8	273394	273264	0	0
T9	11858	11700	0	0
T13	1652	1460	0	0
T20	17174	16942	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	152	6	6	100.00
ALWAYS	165	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	203	4	4	100.00
ALWAYS	215	6	6	100.00
ALWAYS	229	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	325	29	29	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
165	3	3
196	1	1
200	1	1
203	1	1
204	1	1
205	1	1
206	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
277	1	1
280	1	1
281	1	1
282	1	1
287	1	1
317	1	1
321	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
			MISSING_ELSE
347	1	1
348	1	1
349	1	1
			MISSING_ELSE
356	1	1
357	1	1
358	1	1
359	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
374	1	1
375	1	1
388	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
415	1	1
428	1	1
523	1	1
550	1	1
551	1	1
552	1	1
553	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
568	1	1
585	1	1
586	1	1
587	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Covered	Percent
Conditions	106	90	84.91
Logical	106	90	84.91
Non-Logical	0	0
Event	0	0

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T8,T9
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T70
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T9
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T3,T4

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T4,T8
1	1	Covered	T8,T9,T6

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T6
1	1	Covered	T3,T4,T9

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T8,T20,T40
1	1	Covered	T8,T9,T6

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T6
1	1	Covered	T3,T4,T9

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T3,T4,T8
1	1	Covered	T8,T9,T6

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T5
1	0	Covered	T3,T4,T8
1	1	Covered	T8,T20,T40

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T64,T65
1	0	Covered	T2,T8,T5

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Not Covered

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T6
1	1	Covered	T1,T3,T4

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T18,T19

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T6,T23,T134

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T6,T23,T134

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T23,T134

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T23,T134

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	341	Covered	T8,T20,T40
StCtrlProg	339	Covered	T8,T9,T6
StCtrlRead	337	Covered	T3,T4,T9
StDisable	335	Covered	T1,T13,T14
StIdle	349	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	369	Covered	T8,T20,T40
StCtrlProg->StIdle	359	Covered	T8,T9,T6
StCtrlRead->StIdle	349	Covered	T3,T4,T9
StIdle->StCtrl	341	Covered	T8,T20,T40
StIdle->StCtrlProg	339	Covered	T8,T9,T6
StIdle->StCtrlRead	337	Covered	T3,T4,T9
StIdle->StDisable	335	Covered	T1,T13,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	317	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	552	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	431	2	1	50.00
IF	152	4	4	100.00
IF	165	2	2	100.00
IF	203	3	3	100.00
IF	215	4	4	100.00
IF	229	4	4	100.00
CASE	331	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	317	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	552	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T23,T134
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T23,T134
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))
-2-:	154	if (ctrl_rsp_vld)
-3-:	156	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T8
0	0	1	Covered	T8,T9,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if ((!rst_ni))
-2-:	205	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T15,T16
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	217	if ((host_outstanding == '0))
-3-:	219	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T15,T16
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	229	if ((!rst_ni))
-2-:	231	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	233	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T15,T16
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	331	case (state_q)
-2-:	334	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	336	if ((ctrl_gnt && rd_i))
-4-:	338	if ((ctrl_gnt && prog_i))
-5-:	340	if (ctrl_gnt)
-6-:	347	if (rd_stage_data_valid)
-7-:	357	if (prog_ack)
-8-:	367	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T1,T13,T14
StIdle	0	1	-	-	-	-	-	Covered	T3,T4,T9
StIdle	0	0	1	-	-	-	-	Covered	T8,T9,T6
StIdle	0	0	0	1	-	-	-	Covered	T8,T20,T40
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T3,T4,T9
StCtrlRead	-	-	-	-	0	-	-	Covered	T3,T4,T9
StCtrlProg	-	-	-	-	-	1	-	Covered	T8,T9,T6
StCtrlProg	-	-	-	-	-	0	-	Covered	T8,T9,T6
StCtrl	-	-	-	-	-	-	1	Covered	T8,T20,T40
StCtrl	-	-	-	-	-	-	0	Covered	T8,T20,T40
StDisable	-	-	-	-	-	-	-	Covered	T1,T13,T14
default	-	-	-	-	-	-	-	Covered	T17,T18,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	392834735	1329599	0	0
CtrlPrio_A	392834735	1329599	0	0
HostTransIdleChk_A	392834735	21516127	0	0
NoRemainder_A	1058	1058	0	0
OneHotReqs_A	392834735	391966640	0	0
Pow2Multiple_A	1058	1058	0	0
RdTxnCheck_A	392597147	391729052	0	0
u_state_regs_A	392834735	391966640	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	1329599	0	0
T6	190177	3095	0	0
T7	180030	0	0	0
T13	826	0	0	0
T20	8587	0	0	0
T23	0	2805	0	0
T24	2546	0	0	0
T28	57632	0	0	0
T33	0	32239	0	0
T34	0	29458	0	0
T35	0	4851	0	0
T40	5346	0	0	0
T55	1794	0	0	0
T59	0	8650	0	0
T83	5296	0	0	0
T84	4683	0	0	0
T138	0	1471	0	0
T208	0	10980	0	0
T218	0	5413	0	0
T219	0	2375	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	1329599	0	0
T6	190177	3095	0	0
T7	180030	0	0	0
T13	826	0	0	0
T20	8587	0	0	0
T23	0	2805	0	0
T24	2546	0	0	0
T28	57632	0	0	0
T33	0	32239	0	0
T34	0	29458	0	0
T35	0	4851	0	0
T40	5346	0	0	0
T55	1794	0	0	0
T59	0	8650	0	0
T83	5296	0	0	0
T84	4683	0	0	0
T138	0	1471	0	0
T208	0	10980	0	0
T218	0	5413	0	0
T219	0	2375	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	21516127	0	0
T1	657	55	0	0
T2	3027	0	0	0
T3	1673	12	0	0
T4	2879	16	0	0
T5	353826	0	0	0
T6	190177	40621	0	0
T8	136697	364	0	0
T9	5929	103	0	0
T13	826	0	0	0
T20	8587	24	0	0
T24	0	4	0	0
T28	0	30359	0	0
T40	0	31	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T20	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T20	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392597147	391729052	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	152	6	6	100.00
ALWAYS	165	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	203	4	4	100.00
ALWAYS	215	6	6	100.00
ALWAYS	229	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	325	29	29	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
165	3	3
196	1	1
200	1	1
203	1	1
204	1	1
205	1	1
206	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
277	1	1
280	1	1
281	1	1
282	1	1
287	1	1
317	1	1
321	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
			MISSING_ELSE
347	1	1
348	1	1
349	1	1
			MISSING_ELSE
356	1	1
357	1	1
358	1	1
359	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
374	1	1
375	1	1
388	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
415	1	1
428	1	1
523	1	1
550	1	1
551	1	1
552	1	1
553	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
568	1	1
585	1	1
586	1	1
587	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Covered	Percent
Conditions	106	95	89.62
Logical	106	95	89.62
Non-Logical	0	0
Event	0	0

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T205,T15,T217

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T205,T15,T217

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T8,T9,T6
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T8

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T9,T6
1	0	1	Covered	T3,T4,T8
1	1	0	Covered	T53,T54,T60
1	1	1	Covered	T3,T4,T8

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T8
1	1	Covered	T3,T4,T8

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T3,T4,T8

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T8

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T69
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T8

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T9,T6

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T9
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Covered	T2,T8,T5
1	1	Covered	T3,T4,T8

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T54,T60
1	0	Not Covered

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T53,T54,T60

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T8

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T8

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T8

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T8

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T8

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T5,T9

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T64,T65
1	0	Covered	T2,T8,T5

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Not Covered
1	1	Not Covered

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T8

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T18,T19

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	341	Covered	T2,T8,T5
StCtrlProg	339	Covered	T3,T4,T8
StCtrlRead	337	Covered	T1,T2,T3
StDisable	335	Covered	T1,T13,T14
StIdle	349	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	369	Covered	T2,T8,T5
StCtrlProg->StIdle	359	Covered	T3,T4,T8
StCtrlRead->StIdle	349	Covered	T1,T2,T3
StIdle->StCtrl	341	Covered	T2,T8,T5
StIdle->StCtrlProg	339	Covered	T3,T4,T8
StIdle->StCtrlRead	337	Covered	T1,T2,T3
StIdle->StDisable	335	Covered	T1,T13,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	317	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	552	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	431	2	1	50.00
IF	152	4	4	100.00
IF	165	2	2	100.00
IF	203	3	3	100.00
IF	215	4	4	100.00
IF	229	4	4	100.00
CASE	331	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	317	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	552	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))
-2-:	154	if (ctrl_rsp_vld)
-3-:	156	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T8,T9,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if ((!rst_ni))
-2-:	205	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T205,T15,T217
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	217	if ((host_outstanding == '0))
-3-:	219	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T15,T16
0	0	0	Covered	T3,T4,T8

	LineNo.	Expression
-1-:	229	if ((!rst_ni))
-2-:	231	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	233	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T15,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	case (state_q)
-2-:	334	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	336	if ((ctrl_gnt && rd_i))
-4-:	338	if ((ctrl_gnt && prog_i))
-5-:	340	if (ctrl_gnt)
-6-:	347	if (rd_stage_data_valid)
-7-:	357	if (prog_ack)
-8-:	367	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T1,T13,T14
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T3,T4,T8
StIdle	0	0	0	1	-	-	-	Covered	T2,T8,T5
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T3,T4,T8
StCtrlProg	-	-	-	-	-	0	-	Covered	T3,T4,T8
StCtrl	-	-	-	-	-	-	1	Covered	T8,T5,T9
StCtrl	-	-	-	-	-	-	0	Covered	T2,T8,T5
StDisable	-	-	-	-	-	-	-	Covered	T1,T13,T14
default	-	-	-	-	-	-	-	Covered	T17,T18,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	392834735	1603989	0	0
CtrlPrio_A	392834735	1603989	0	0
HostTransIdleChk_A	392834735	22334551	0	0
NoRemainder_A	1058	1058	0	0
OneHotReqs_A	392834735	391966640	0	0
Pow2Multiple_A	1058	1058	0	0
RdTxnCheck_A	392597147	391729052	0	0
u_state_regs_A	392834735	391966640	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	1603989	0	0
T5	353826	0	0	0
T6	190177	3990	0	0
T7	180030	0	0	0
T8	136697	84	0	0
T9	5929	0	0	0
T13	826	0	0	0
T20	8587	0	0	0
T23	0	4948	0	0
T28	57632	5059	0	0
T33	0	46762	0	0
T34	0	47380	0	0
T35	0	4311	0	0
T40	5346	0	0	0
T59	0	5455	0	0
T83	5296	0	0	0
T218	0	1320	0	0
T219	0	3732	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	1603989	0	0
T5	353826	0	0	0
T6	190177	3990	0	0
T7	180030	0	0	0
T8	136697	84	0	0
T9	5929	0	0	0
T13	826	0	0	0
T20	8587	0	0	0
T23	0	4948	0	0
T28	57632	5059	0	0
T33	0	46762	0	0
T34	0	47380	0	0
T35	0	4311	0	0
T40	5346	0	0	0
T59	0	5455	0	0
T83	5296	0	0	0
T218	0	1320	0	0
T219	0	3732	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	22334551	0	0
T3	1673	20	0	0
T4	2879	20	0	0
T5	353826	0	0	0
T6	190177	44800	0	0
T7	180030	0	0	0
T8	136697	257	0	0
T9	5929	228	0	0
T13	826	0	0	0
T20	8587	12	0	0
T22	0	209	0	0
T24	0	16	0	0
T28	57632	27796	0	0
T40	0	38	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T20	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T20	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392597147	391729052	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0