Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1571338940	1567866560	0	0
CheckNGreaterZero_A	4232	4232	0	0
GntImpliesReady_A	1571338940	396033708	0	0
GntImpliesValid_A	1571338940	396033708	0	0
GrantKnown_A	1571338940	1567866560	0	0
IdxKnown_A	1571338940	1567866560	0	0
IndexIsCorrect_A	1571338940	396033708	0	0
NoReadyValidNoGrant_A	1571338940	179112772	0	0
Priority_A	1571338940	419805702	0	0
ReadyAndValidImplyGrant_A	1571338940	396033708	0	0
ReqAndReadyImplyGrant_A	1571338940	396033708	0	0
ReqImpliesValid_A	1571338940	419805702	0	0
ValidKnown_A	1571338940	1567866560	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571338940	1567866560	0	0
T1	2628	2232	0	0
T2	12108	9552	0	0
T3	6692	6232	0	0
T4	11516	10852	0	0
T5	1415304	1351516	0	0
T6	760708	760488	0	0
T8	546788	546528	0	0
T9	23716	23400	0	0
T13	3304	2920	0	0
T20	34348	33884	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4232	4232	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T13	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571338940	396033708	0	0
T1	2628	108	0	0
T2	12108	212	0	0
T3	6692	460	0	0
T4	11516	420	0	0
T5	1415304	300798	0	0
T6	760708	239220	0	0
T8	546788	266424	0	0
T9	23716	5426	0	0
T13	3304	84	0	0
T20	34348	9490	0	0
T24	0	14	0	0
T28	0	16406	0	0
T40	0	1664	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571338940	396033708	0	0
T1	2628	108	0	0
T2	12108	212	0	0
T3	6692	460	0	0
T4	11516	420	0	0
T5	1415304	300798	0	0
T6	760708	239220	0	0
T8	546788	266424	0	0
T9	23716	5426	0	0
T13	3304	84	0	0
T20	34348	9490	0	0
T24	0	14	0	0
T28	0	16406	0	0
T40	0	1664	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571338940	1567866560	0	0
T1	2628	2232	0	0
T2	12108	9552	0	0
T3	6692	6232	0	0
T4	11516	10852	0	0
T5	1415304	1351516	0	0
T6	760708	760488	0	0
T8	546788	546528	0	0
T9	23716	23400	0	0
T13	3304	2920	0	0
T20	34348	33884	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571338940	1567866560	0	0
T1	2628	2232	0	0
T2	12108	9552	0	0
T3	6692	6232	0	0
T4	11516	10852	0	0
T5	1415304	1351516	0	0
T6	760708	760488	0	0
T8	546788	546528	0	0
T9	23716	23400	0	0
T13	3304	2920	0	0
T20	34348	33884	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571338940	396033708	0	0
T1	2628	108	0	0
T2	12108	212	0	0
T3	6692	460	0	0
T4	11516	420	0	0
T5	1415304	300798	0	0
T6	760708	239220	0	0
T8	546788	266424	0	0
T9	23716	5426	0	0
T13	3304	84	0	0
T20	34348	9490	0	0
T24	0	14	0	0
T28	0	16406	0	0
T40	0	1664	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571338940	179112772	0	0
T1	2628	366	0	0
T2	12108	796	0	0
T3	6692	1008	0	0
T4	11516	942	0	0
T5	1415304	80600	0	0
T6	760708	143794	0	0
T8	546788	1554	0	0
T9	23716	1110	0	0
T13	3304	312	0	0
T20	34348	1606	0	0
T24	0	38	0	0
T28	0	50534	0	0
T40	0	228	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571338940	419805702	0	0
T1	2628	108	0	0
T2	12108	212	0	0
T3	6692	460	0	0
T4	11516	420	0	0
T5	1415304	300798	0	0
T6	760708	268494	0	0
T8	546788	266788	0	0
T9	23716	5564	0	0
T13	3304	84	0	0
T20	34348	9490	0	0
T24	0	14	0	0
T28	0	18700	0	0
T40	0	1664	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571338940	396033708	0	0
T1	2628	108	0	0
T2	12108	212	0	0
T3	6692	460	0	0
T4	11516	420	0	0
T5	1415304	300798	0	0
T6	760708	239220	0	0
T8	546788	266424	0	0
T9	23716	5426	0	0
T13	3304	84	0	0
T20	34348	9490	0	0
T24	0	14	0	0
T28	0	16406	0	0
T40	0	1664	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571338940	396033708	0	0
T1	2628	108	0	0
T2	12108	212	0	0
T3	6692	460	0	0
T4	11516	420	0	0
T5	1415304	300798	0	0
T6	760708	239220	0	0
T8	546788	266424	0	0
T9	23716	5426	0	0
T13	3304	84	0	0
T20	34348	9490	0	0
T24	0	14	0	0
T28	0	16406	0	0
T40	0	1664	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571338940	419805702	0	0
T1	2628	108	0	0
T2	12108	212	0	0
T3	6692	460	0	0
T4	11516	420	0	0
T5	1415304	300798	0	0
T6	760708	268494	0	0
T8	546788	266788	0	0
T9	23716	5564	0	0
T13	3304	84	0	0
T20	34348	9490	0	0
T24	0	14	0	0
T28	0	18700	0	0
T40	0	1664	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571338940	1567866560	0	0
T1	2628	2232	0	0
T2	12108	9552	0	0
T3	6692	6232	0	0
T4	11516	10852	0	0
T5	1415304	1351516	0	0
T6	760708	760488	0	0
T8	546788	546528	0	0
T9	23716	23400	0	0
T13	3304	2920	0	0
T20	34348	33884	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	392834735	391966640	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	392834735	108411189	0	0
GntImpliesValid_A	392834735	108411189	0	0
GrantKnown_A	392834735	391966640	0	0
IdxKnown_A	392834735	391966640	0	0
IndexIsCorrect_A	392834735	108411189	0	0
NoReadyValidNoGrant_A	392834735	47084467	0	0
Priority_A	392834735	114503940	0	0
ReadyAndValidImplyGrant_A	392834735	108411189	0	0
ReqAndReadyImplyGrant_A	392834735	108411189	0	0
ReqImpliesValid_A	392834735	114503940	0	0
ValidKnown_A	392834735	391966640	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	108411189	0	0
T1	657	32	0	0
T2	3027	106	0	0
T3	1673	215	0	0
T4	2879	194	0	0
T5	353826	150399	0	0
T6	190177	39090	0	0
T8	136697	66655	0	0
T9	5929	1932	0	0
T13	826	42	0	0
T20	8587	4189	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	108411189	0	0
T1	657	32	0	0
T2	3027	106	0	0
T3	1673	215	0	0
T4	2879	194	0	0
T5	353826	150399	0	0
T6	190177	39090	0	0
T8	136697	66655	0	0
T9	5929	1932	0	0
T13	826	42	0	0
T20	8587	4189	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	108411189	0	0
T1	657	32	0	0
T2	3027	106	0	0
T3	1673	215	0	0
T4	2879	194	0	0
T5	353826	150399	0	0
T6	190177	39090	0	0
T8	136697	66655	0	0
T9	5929	1932	0	0
T13	826	42	0	0
T20	8587	4189	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	47084467	0	0
T1	657	128	0	0
T2	3027	398	0	0
T3	1673	462	0	0
T4	2879	425	0	0
T5	353826	40300	0	0
T6	190177	35480	0	0
T8	136697	413	0	0
T9	5929	400	0	0
T13	826	156	0	0
T20	8587	718	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	114503940	0	0
T1	657	32	0	0
T2	3027	106	0	0
T3	1673	215	0	0
T4	2879	194	0	0
T5	353826	150399	0	0
T6	190177	47424	0	0
T8	136697	66708	0	0
T9	5929	1967	0	0
T13	826	42	0	0
T20	8587	4189	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	108411189	0	0
T1	657	32	0	0
T2	3027	106	0	0
T3	1673	215	0	0
T4	2879	194	0	0
T5	353826	150399	0	0
T6	190177	39090	0	0
T8	136697	66655	0	0
T9	5929	1932	0	0
T13	826	42	0	0
T20	8587	4189	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	108411189	0	0
T1	657	32	0	0
T2	3027	106	0	0
T3	1673	215	0	0
T4	2879	194	0	0
T5	353826	150399	0	0
T6	190177	39090	0	0
T8	136697	66655	0	0
T9	5929	1932	0	0
T13	826	42	0	0
T20	8587	4189	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	114503940	0	0
T1	657	32	0	0
T2	3027	106	0	0
T3	1673	215	0	0
T4	2879	194	0	0
T5	353826	150399	0	0
T6	190177	47424	0	0
T8	136697	66708	0	0
T9	5929	1967	0	0
T13	826	42	0	0
T20	8587	4189	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	392834735	391966640	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	392834735	108411120	0	0
GntImpliesValid_A	392834735	108411120	0	0
GrantKnown_A	392834735	391966640	0	0
IdxKnown_A	392834735	391966640	0	0
IndexIsCorrect_A	392834735	108411120	0	0
NoReadyValidNoGrant_A	392834735	47084468	0	0
Priority_A	392834735	114503870	0	0
ReadyAndValidImplyGrant_A	392834735	108411120	0	0
ReqAndReadyImplyGrant_A	392834735	108411120	0	0
ReqImpliesValid_A	392834735	114503870	0	0
ValidKnown_A	392834735	391966640	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	108411120	0	0
T1	657	32	0	0
T2	3027	106	0	0
T3	1673	215	0	0
T4	2879	194	0	0
T5	353826	150399	0	0
T6	190177	39090	0	0
T8	136697	66655	0	0
T9	5929	1932	0	0
T13	826	42	0	0
T20	8587	4189	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	108411120	0	0
T1	657	32	0	0
T2	3027	106	0	0
T3	1673	215	0	0
T4	2879	194	0	0
T5	353826	150399	0	0
T6	190177	39090	0	0
T8	136697	66655	0	0
T9	5929	1932	0	0
T13	826	42	0	0
T20	8587	4189	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	108411120	0	0
T1	657	32	0	0
T2	3027	106	0	0
T3	1673	215	0	0
T4	2879	194	0	0
T5	353826	150399	0	0
T6	190177	39090	0	0
T8	136697	66655	0	0
T9	5929	1932	0	0
T13	826	42	0	0
T20	8587	4189	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	47084468	0	0
T1	657	128	0	0
T2	3027	398	0	0
T3	1673	462	0	0
T4	2879	425	0	0
T5	353826	40300	0	0
T6	190177	35480	0	0
T8	136697	413	0	0
T9	5929	400	0	0
T13	826	156	0	0
T20	8587	718	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	114503870	0	0
T1	657	32	0	0
T2	3027	106	0	0
T3	1673	215	0	0
T4	2879	194	0	0
T5	353826	150399	0	0
T6	190177	47424	0	0
T8	136697	66708	0	0
T9	5929	1967	0	0
T13	826	42	0	0
T20	8587	4189	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	108411120	0	0
T1	657	32	0	0
T2	3027	106	0	0
T3	1673	215	0	0
T4	2879	194	0	0
T5	353826	150399	0	0
T6	190177	39090	0	0
T8	136697	66655	0	0
T9	5929	1932	0	0
T13	826	42	0	0
T20	8587	4189	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	108411120	0	0
T1	657	32	0	0
T2	3027	106	0	0
T3	1673	215	0	0
T4	2879	194	0	0
T5	353826	150399	0	0
T6	190177	39090	0	0
T8	136697	66655	0	0
T9	5929	1932	0	0
T13	826	42	0	0
T20	8587	4189	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	114503870	0	0
T1	657	32	0	0
T2	3027	106	0	0
T3	1673	215	0	0
T4	2879	194	0	0
T5	353826	150399	0	0
T6	190177	47424	0	0
T8	136697	66708	0	0
T9	5929	1967	0	0
T13	826	42	0	0
T20	8587	4189	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T8

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	392834735	391966640	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	392834735	89605673	0	0
GntImpliesValid_A	392834735	89605673	0	0
GrantKnown_A	392834735	391966640	0	0
IdxKnown_A	392834735	391966640	0	0
IndexIsCorrect_A	392834735	89605673	0	0
NoReadyValidNoGrant_A	392834735	42471925	0	0
Priority_A	392834735	95398913	0	0
ReadyAndValidImplyGrant_A	392834735	89605673	0	0
ReqAndReadyImplyGrant_A	392834735	89605673	0	0
ReqImpliesValid_A	392834735	95398913	0	0
ValidKnown_A	392834735	391966640	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	89605673	0	0
T1	657	22	0	0
T2	3027	0	0	0
T3	1673	15	0	0
T4	2879	16	0	0
T5	353826	0	0	0
T6	190177	80520	0	0
T8	136697	66557	0	0
T9	5929	781	0	0
T13	826	0	0	0
T20	8587	556	0	0
T24	0	7	0	0
T28	0	8203	0	0
T40	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	89605673	0	0
T1	657	22	0	0
T2	3027	0	0	0
T3	1673	15	0	0
T4	2879	16	0	0
T5	353826	0	0	0
T6	190177	80520	0	0
T8	136697	66557	0	0
T9	5929	781	0	0
T13	826	0	0	0
T20	8587	556	0	0
T24	0	7	0	0
T28	0	8203	0	0
T40	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	89605673	0	0
T1	657	22	0	0
T2	3027	0	0	0
T3	1673	15	0	0
T4	2879	16	0	0
T5	353826	0	0	0
T6	190177	80520	0	0
T8	136697	66557	0	0
T9	5929	781	0	0
T13	826	0	0	0
T20	8587	556	0	0
T24	0	7	0	0
T28	0	8203	0	0
T40	0	832	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	42471925	0	0
T1	657	55	0	0
T2	3027	0	0	0
T3	1673	42	0	0
T4	2879	46	0	0
T5	353826	0	0	0
T6	190177	36417	0	0
T8	136697	364	0	0
T9	5929	155	0	0
T13	826	0	0	0
T20	8587	85	0	0
T24	0	19	0	0
T28	0	25267	0	0
T40	0	114	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	95398913	0	0
T1	657	22	0	0
T2	3027	0	0	0
T3	1673	15	0	0
T4	2879	16	0	0
T5	353826	0	0	0
T6	190177	86823	0	0
T8	136697	66686	0	0
T9	5929	815	0	0
T13	826	0	0	0
T20	8587	556	0	0
T24	0	7	0	0
T28	0	9350	0	0
T40	0	832	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	89605673	0	0
T1	657	22	0	0
T2	3027	0	0	0
T3	1673	15	0	0
T4	2879	16	0	0
T5	353826	0	0	0
T6	190177	80520	0	0
T8	136697	66557	0	0
T9	5929	781	0	0
T13	826	0	0	0
T20	8587	556	0	0
T24	0	7	0	0
T28	0	8203	0	0
T40	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	89605673	0	0
T1	657	22	0	0
T2	3027	0	0	0
T3	1673	15	0	0
T4	2879	16	0	0
T5	353826	0	0	0
T6	190177	80520	0	0
T8	136697	66557	0	0
T9	5929	781	0	0
T13	826	0	0	0
T20	8587	556	0	0
T24	0	7	0	0
T28	0	8203	0	0
T40	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	95398913	0	0
T1	657	22	0	0
T2	3027	0	0	0
T3	1673	15	0	0
T4	2879	16	0	0
T5	353826	0	0	0
T6	190177	86823	0	0
T8	136697	66686	0	0
T9	5929	815	0	0
T13	826	0	0	0
T20	8587	556	0	0
T24	0	7	0	0
T28	0	9350	0	0
T40	0	832	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T8

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	392834735	391966640	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	392834735	89605726	0	0
GntImpliesValid_A	392834735	89605726	0	0
GrantKnown_A	392834735	391966640	0	0
IdxKnown_A	392834735	391966640	0	0
IndexIsCorrect_A	392834735	89605726	0	0
NoReadyValidNoGrant_A	392834735	42471912	0	0
Priority_A	392834735	95398979	0	0
ReadyAndValidImplyGrant_A	392834735	89605726	0	0
ReqAndReadyImplyGrant_A	392834735	89605726	0	0
ReqImpliesValid_A	392834735	95398979	0	0
ValidKnown_A	392834735	391966640	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	89605726	0	0
T1	657	22	0	0
T2	3027	0	0	0
T3	1673	15	0	0
T4	2879	16	0	0
T5	353826	0	0	0
T6	190177	80520	0	0
T8	136697	66557	0	0
T9	5929	781	0	0
T13	826	0	0	0
T20	8587	556	0	0
T24	0	7	0	0
T28	0	8203	0	0
T40	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	89605726	0	0
T1	657	22	0	0
T2	3027	0	0	0
T3	1673	15	0	0
T4	2879	16	0	0
T5	353826	0	0	0
T6	190177	80520	0	0
T8	136697	66557	0	0
T9	5929	781	0	0
T13	826	0	0	0
T20	8587	556	0	0
T24	0	7	0	0
T28	0	8203	0	0
T40	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	89605726	0	0
T1	657	22	0	0
T2	3027	0	0	0
T3	1673	15	0	0
T4	2879	16	0	0
T5	353826	0	0	0
T6	190177	80520	0	0
T8	136697	66557	0	0
T9	5929	781	0	0
T13	826	0	0	0
T20	8587	556	0	0
T24	0	7	0	0
T28	0	8203	0	0
T40	0	832	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	42471912	0	0
T1	657	55	0	0
T2	3027	0	0	0
T3	1673	42	0	0
T4	2879	46	0	0
T5	353826	0	0	0
T6	190177	36417	0	0
T8	136697	364	0	0
T9	5929	155	0	0
T13	826	0	0	0
T20	8587	85	0	0
T24	0	19	0	0
T28	0	25267	0	0
T40	0	114	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	95398979	0	0
T1	657	22	0	0
T2	3027	0	0	0
T3	1673	15	0	0
T4	2879	16	0	0
T5	353826	0	0	0
T6	190177	86823	0	0
T8	136697	66686	0	0
T9	5929	815	0	0
T13	826	0	0	0
T20	8587	556	0	0
T24	0	7	0	0
T28	0	9350	0	0
T40	0	832	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	89605726	0	0
T1	657	22	0	0
T2	3027	0	0	0
T3	1673	15	0	0
T4	2879	16	0	0
T5	353826	0	0	0
T6	190177	80520	0	0
T8	136697	66557	0	0
T9	5929	781	0	0
T13	826	0	0	0
T20	8587	556	0	0
T24	0	7	0	0
T28	0	8203	0	0
T40	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	89605726	0	0
T1	657	22	0	0
T2	3027	0	0	0
T3	1673	15	0	0
T4	2879	16	0	0
T5	353826	0	0	0
T6	190177	80520	0	0
T8	136697	66557	0	0
T9	5929	781	0	0
T13	826	0	0	0
T20	8587	556	0	0
T24	0	7	0	0
T28	0	8203	0	0
T40	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	95398979	0	0
T1	657	22	0	0
T2	3027	0	0	0
T3	1673	15	0	0
T4	2879	16	0	0
T5	353826	0	0	0
T6	190177	86823	0	0
T8	136697	66686	0	0
T9	5929	815	0	0
T13	826	0	0	0
T20	8587	556	0	0
T24	0	7	0	0
T28	0	9350	0	0
T40	0	832	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392834735	391966640	0	0
T1	657	558	0	0
T2	3027	2388	0	0
T3	1673	1558	0	0
T4	2879	2713	0	0
T5	353826	337879	0	0
T6	190177	190122	0	0
T8	136697	136632	0	0
T9	5929	5850	0	0
T13	826	730	0	0
T20	8587	8471	0	0