Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24796347	1		T1	6747		T2	184472		T3	7078
full_word	7419204	1		T1	11682		T2	25819		T3	13422

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32215261	1		T1	18429		T2	210291		T3	20500
auto[TlIntgErrCmd]	85	1		T60	10		T93	4		T225	2
auto[TlIntgErrData]	102	1		T60	7		T93	5		T225	5
auto[TlIntgErrBoth]	103	1		T60	3		T93	1		T225	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27826729	1		T1	12282		T2	189193		T3	13143
auto[1]	4388822	1		T1	6147		T2	21098		T3	7357

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24138078	1		T1	6478		T2	182020		T3	6790
auto[TlIntgErrNone]	partial	auto[1]	658004	1		T1	269		T2	2452		T3	288
auto[TlIntgErrNone]	full_word	auto[0]	3688508	1		T1	5804		T2	7173		T3	6353
auto[TlIntgErrNone]	full_word	auto[1]	3730671	1		T1	5878		T2	18646		T3	7069
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T60	7		T93	4		T225	2
auto[TlIntgErrCmd]	partial	auto[1]	40	1		T60	3		T243	1		T338	5
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T337	1		T344	1		T339	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T345	1		T346	1		-	-
auto[TlIntgErrData]	partial	auto[0]	44	1		T93	2		T225	2		T243	2
auto[TlIntgErrData]	partial	auto[1]	50	1		T60	5		T93	2		T225	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T60	1		T225	1		T337	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T60	1		T93	1		T338	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1		T60	1		T225	2		T243	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T60	2		T93	1		T225	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T338	1		T347	2		T342	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T339	1		T348	1		T343	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21179	1		T60	15		T92	678		T62	82
full_word	3779277	1		T2	27501		T10	9		T5	9070

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3800193	1		T2	27501		T10	9		T5	9070
auto[TlIntgErrCmd]	91	1		T60	8		T93	3		T243	2
auto[TlIntgErrData]	88	1		T60	6		T93	2		T225	6
auto[TlIntgErrBoth]	84	1		T60	4		T93	3		T225	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3774229	1		T2	27501		T10	9		T5	9070
auto[1]	26227	1		T60	11		T92	774		T62	108

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1459	1		T92	64		T62	3		T206	81
auto[TlIntgErrNone]	partial	auto[1]	19480	1		T92	614		T62	79		T206	880
auto[TlIntgErrNone]	full_word	auto[0]	3772668	1		T2	27501		T10	9		T5	9070
auto[TlIntgErrNone]	full_word	auto[1]	6586	1		T92	160		T62	29		T206	191
auto[TlIntgErrCmd]	partial	auto[0]	23	1		T60	1		T243	1		T338	2
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T60	7		T93	3		T243	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T344	1		T347	1		T345	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T337	1		T344	1		T339	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T60	2		T93	1		T225	2
auto[TlIntgErrData]	partial	auto[1]	39	1		T60	1		T225	3		T243	1
auto[TlIntgErrData]	full_word	auto[0]	6	1		T60	2		T93	1		T225	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T60	1		T243	1		T336	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T60	2		T225	1		T243	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T60	2		T93	3		T225	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T349	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T243	1		T342	1		-	-