Module Definition
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Module : flash_phy_rd_buf_dep
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.65 100.00 90.61 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.43 100.00 89.74 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable

Cond Coverage for Module : flash_phy_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T10 

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T10
110Not Covered
111CoveredT1,T2,T10 

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T10
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10,T24,T50
11CoveredT1,T2,T10 

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T10
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT10,T24,T50
10CoveredT1,T2,T3
11CoveredT1,T2,T10
Branch Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T10 



	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T10 



	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T2,T10
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T2,T10
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T10
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T10
0 - 0 Covered T1,T2,T3

Assert Coverage for Module : flash_phy_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 722781634 6626007 0 0
BufferDepRsp_A 722781634 721048492 0 0
BufferIncrOverFlow_A 722781634 6626020 0 0
DepBufferRspOrder_A 722781635 17178803 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 722781634 6626007 0 0
T1 37893 1024 0 0
T2 857992 45947 0 0
T3 433062 0 0 0
T4 3516 0 0 0
T5 129316 21775 0 0
T6 2920 45 0 0
T10 1526 9 0 0
T11 802540 0 0 0
T16 20840 0 0 0
T17 3194 20 0 0
T20 129201 46262 0 0
T21 0 67 0 0
T24 0 21757 0 0
T28 0 1662 0 0
T38 0 158 0 0
T41 0 2372 0 0
T52 0 19 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 722781634 721048492 0 0
T1 75786 75658 0 0
T2 857992 857844 0 0
T3 433062 432880 0 0
T4 3516 3258 0 0
T5 129316 129168 0 0
T6 2920 2668 0 0
T10 1526 1400 0 0
T11 802540 802514 0 0
T16 20840 20662 0 0
T17 3194 3048 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 722781634 6626020 0 0
T1 37893 1024 0 0
T2 857992 45947 0 0
T3 433062 0 0 0
T4 3516 0 0 0
T5 129316 21775 0 0
T6 2920 45 0 0
T10 1526 9 0 0
T11 802540 0 0 0
T16 20840 0 0 0
T17 3194 20 0 0
T20 129201 46262 0 0
T21 0 67 0 0
T24 0 21757 0 0
T28 0 1662 0 0
T38 0 158 0 0
T41 0 2372 0 0
T52 0 19 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 722781635 17178803 0 0
T1 37893 1056 0 0
T2 857992 45979 0 0
T3 433062 32 0 0
T4 3516 64 0 0
T5 129316 21807 0 0
T6 2920 109 0 0
T10 1526 41 0 0
T11 802540 263744 0 0
T16 20840 32 0 0
T17 3194 52 0 0
T20 129201 24654 0 0
T21 0 3 0 0
T24 0 21757 0 0
T38 0 83 0 0
T41 0 1260 0 0
T52 0 19 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T10 

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T10
110Not Covered
111CoveredT1,T2,T10 

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T10
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10,T32,T18
11CoveredT1,T2,T10 

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T10
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT10,T32,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T10
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T10 



	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T10 



	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T2,T10
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T2,T10
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T10
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T10
0 - 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 361390817 3677071 0 0
BufferDepRsp_A 361390817 360524246 0 0
BufferIncrOverFlow_A 361390817 3677078 0 0
DepBufferRspOrder_A 361390818 9548033 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361390817 3677071 0 0
T1 37893 1024 0 0
T2 428996 23426 0 0
T3 216531 0 0 0
T4 1758 0 0 0
T5 64658 11253 0 0
T6 1460 6 0 0
T10 763 9 0 0
T11 401270 0 0 0
T16 10420 0 0 0
T17 1597 20 0 0
T20 0 21608 0 0
T21 0 64 0 0
T38 0 75 0 0
T41 0 1112 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361390817 360524246 0 0
T1 37893 37829 0 0
T2 428996 428922 0 0
T3 216531 216440 0 0
T4 1758 1629 0 0
T5 64658 64584 0 0
T6 1460 1334 0 0
T10 763 700 0 0
T11 401270 401257 0 0
T16 10420 10331 0 0
T17 1597 1524 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361390817 3677078 0 0
T1 37893 1024 0 0
T2 428996 23426 0 0
T3 216531 0 0 0
T4 1758 0 0 0
T5 64658 11253 0 0
T6 1460 6 0 0
T10 763 9 0 0
T11 401270 0 0 0
T16 10420 0 0 0
T17 1597 20 0 0
T20 0 21608 0 0
T21 0 64 0 0
T38 0 75 0 0
T41 0 1112 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361390818 9548033 0 0
T1 37893 1056 0 0
T2 428996 23458 0 0
T3 216531 32 0 0
T4 1758 64 0 0
T5 64658 11285 0 0
T6 1460 70 0 0
T10 763 41 0 0
T11 401270 132672 0 0
T16 10420 32 0 0
T17 1597 52 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT11,T94,T95
101CoveredT1,T2,T3
110Not Covered
111CoveredT2,T5,T6 

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T5,T6
110Not Covered
111CoveredT2,T5,T6 

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT2,T5,T6
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T50,T58
11CoveredT2,T5,T6 

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT2,T5,T6
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT24,T50,T58
10CoveredT1,T2,T3
11CoveredT2,T5,T6
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T5,T6 



	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T5,T6 



	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T2,T5,T6
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T2,T5,T6
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T5,T6
0 0 - Covered T1,T2,T3
0 - 1 Covered T2,T5,T6
0 - 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 361390817 2948936 0 0
BufferDepRsp_A 361390817 360524246 0 0
BufferIncrOverFlow_A 361390817 2948942 0 0
DepBufferRspOrder_A 361390817 7630770 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361390817 2948936 0 0
T2 428996 22521 0 0
T3 216531 0 0 0
T4 1758 0 0 0
T5 64658 10522 0 0
T6 1460 39 0 0
T10 763 0 0 0
T11 401270 0 0 0
T16 10420 0 0 0
T17 1597 0 0 0
T20 129201 24654 0 0
T21 0 3 0 0
T24 0 21757 0 0
T28 0 1662 0 0
T38 0 83 0 0
T41 0 1260 0 0
T52 0 19 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361390817 360524246 0 0
T1 37893 37829 0 0
T2 428996 428922 0 0
T3 216531 216440 0 0
T4 1758 1629 0 0
T5 64658 64584 0 0
T6 1460 1334 0 0
T10 763 700 0 0
T11 401270 401257 0 0
T16 10420 10331 0 0
T17 1597 1524 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361390817 2948942 0 0
T2 428996 22521 0 0
T3 216531 0 0 0
T4 1758 0 0 0
T5 64658 10522 0 0
T6 1460 39 0 0
T10 763 0 0 0
T11 401270 0 0 0
T16 10420 0 0 0
T17 1597 0 0 0
T20 129201 24654 0 0
T21 0 3 0 0
T24 0 21757 0 0
T28 0 1662 0 0
T38 0 83 0 0
T41 0 1260 0 0
T52 0 19 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 361390817 7630770 0 0
T2 428996 22521 0 0
T3 216531 0 0 0
T4 1758 0 0 0
T5 64658 10522 0 0
T6 1460 39 0 0
T10 763 0 0 0
T11 401270 131072 0 0
T16 10420 0 0 0
T17 1597 0 0 0
T20 129201 24654 0 0
T21 0 3 0 0
T24 0 21757 0 0
T38 0 83 0 0
T41 0 1260 0 0
T52 0 19 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%