Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T10,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T10,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T10,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T10,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1445563268	1442096984	0	0
CheckNGreaterZero_A	4232	4232	0	0
GntImpliesReady_A	1445563268	405664338	0	0
GntImpliesValid_A	1445563268	405664338	0	0
GrantKnown_A	1445563268	1442096984	0	0
IdxKnown_A	1445563268	1442096984	0	0
IndexIsCorrect_A	1445563268	405664338	0	0
NoReadyValidNoGrant_A	1445563268	178423852	0	0
Priority_A	1445563268	429897660	0	0
ReadyAndValidImplyGrant_A	1445563268	405664338	0	0
ReqAndReadyImplyGrant_A	1445563268	405664338	0	0
ReqImpliesValid_A	1445563268	429897660	0	0
ValidKnown_A	1445563268	1442096984	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1445563268	1442096984	0	0
T1	151572	151316	0	0
T2	1715984	1715688	0	0
T3	866124	865760	0	0
T4	7032	6516	0	0
T5	258632	258336	0	0
T6	5840	5336	0	0
T10	3052	2800	0	0
T11	1605080	1605028	0	0
T16	41680	41324	0	0
T17	6388	6096	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4232	4232	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1445563268	405664338	0	0
T1	75786	3152	0	0
T2	1715984	622502	0	0
T3	866124	584	0	0
T4	7032	176	0	0
T5	258632	43614	0	0
T6	5840	220	0	0
T10	3052	82	0	0
T11	1605080	514652	0	0
T16	41680	64	0	0
T17	6388	1178	0	0
T20	258402	49308	0	0
T37	0	170352	0	0
T38	0	4792	0	0
T41	0	57426	0	0
T52	0	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1445563268	405664338	0	0
T1	75786	3152	0	0
T2	1715984	622502	0	0
T3	866124	584	0	0
T4	7032	176	0	0
T5	258632	43614	0	0
T6	5840	220	0	0
T10	3052	82	0	0
T11	1605080	514652	0	0
T16	41680	64	0	0
T17	6388	1178	0	0
T20	258402	49308	0	0
T37	0	170352	0	0
T38	0	4792	0	0
T41	0	57426	0	0
T52	0	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1445563268	1442096984	0	0
T1	151572	151316	0	0
T2	1715984	1715688	0	0
T3	866124	865760	0	0
T4	7032	6516	0	0
T5	258632	258336	0	0
T6	5840	5336	0	0
T10	3052	2800	0	0
T11	1605080	1605028	0	0
T16	41680	41324	0	0
T17	6388	6096	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1445563268	1442096984	0	0
T1	151572	151316	0	0
T2	1715984	1715688	0	0
T3	866124	865760	0	0
T4	7032	6516	0	0
T5	258632	258336	0	0
T6	5840	5336	0	0
T10	3052	2800	0	0
T11	1605080	1605028	0	0
T16	41680	41324	0	0
T17	6388	6096	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1445563268	405664338	0	0
T1	75786	3152	0	0
T2	1715984	622502	0	0
T3	866124	584	0	0
T4	7032	176	0	0
T5	258632	43614	0	0
T6	5840	220	0	0
T10	3052	82	0	0
T11	1605080	514652	0	0
T16	41680	64	0	0
T17	6388	1178	0	0
T20	258402	49308	0	0
T37	0	170352	0	0
T38	0	4792	0	0
T41	0	57426	0	0
T52	0	38	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1445563268	178423852	0	0
T1	75786	3200	0	0
T2	1715984	178210	0	0
T3	866124	128	0	0
T4	7032	512	0	0
T5	258632	128014	0	0
T6	5840	650	0	0
T10	3052	304	0	0
T11	1605080	2109952	0	0
T16	41680	256	0	0
T17	6388	316	0	0
T20	258402	1505254	0	0
T21	0	10	0	0
T24	0	1298756	0	0
T38	0	258	0	0
T41	0	3780	0	0
T52	0	58	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1445563268	429897660	0	0
T1	75786	3152	0	0
T2	1715984	714200	0	0
T3	866124	584	0	0
T4	7032	176	0	0
T5	258632	46760	0	0
T6	5840	232	0	0
T10	3052	82	0	0
T11	1605080	514652	0	0
T16	41680	64	0	0
T17	6388	1178	0	0
T20	258402	277028	0	0
T37	0	170352	0	0
T38	0	4792	0	0
T41	0	57426	0	0
T52	0	38	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1445563268	405664338	0	0
T1	75786	3152	0	0
T2	1715984	622502	0	0
T3	866124	584	0	0
T4	7032	176	0	0
T5	258632	43614	0	0
T6	5840	220	0	0
T10	3052	82	0	0
T11	1605080	514652	0	0
T16	41680	64	0	0
T17	6388	1178	0	0
T20	258402	49308	0	0
T37	0	170352	0	0
T38	0	4792	0	0
T41	0	57426	0	0
T52	0	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1445563268	405664338	0	0
T1	75786	3152	0	0
T2	1715984	622502	0	0
T3	866124	584	0	0
T4	7032	176	0	0
T5	258632	43614	0	0
T6	5840	220	0	0
T10	3052	82	0	0
T11	1605080	514652	0	0
T16	41680	64	0	0
T17	6388	1178	0	0
T20	258402	49308	0	0
T37	0	170352	0	0
T38	0	4792	0	0
T41	0	57426	0	0
T52	0	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1445563268	429897660	0	0
T1	75786	3152	0	0
T2	1715984	714200	0	0
T3	866124	584	0	0
T4	7032	176	0	0
T5	258632	46760	0	0
T6	5840	232	0	0
T10	3052	82	0	0
T11	1605080	514652	0	0
T16	41680	64	0	0
T17	6388	1178	0	0
T20	258402	277028	0	0
T37	0	170352	0	0
T38	0	4792	0	0
T41	0	57426	0	0
T52	0	38	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1445563268	1442096984	0	0
T1	151572	151316	0	0
T2	1715984	1715688	0	0
T3	866124	865760	0	0
T4	7032	6516	0	0
T5	258632	258336	0	0
T6	5840	5336	0	0
T10	3052	2800	0	0
T11	1605080	1605028	0	0
T16	41680	41324	0	0
T17	6388	6096	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T10,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T10,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T10,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T10,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	361390817	360524246	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	361390817	109613445	0	0
GntImpliesValid_A	361390817	109613445	0	0
GrantKnown_A	361390817	360524246	0	0
IdxKnown_A	361390817	360524246	0	0
IndexIsCorrect_A	361390817	109613445	0	0
NoReadyValidNoGrant_A	361390817	47220231	0	0
Priority_A	361390817	115687171	0	0
ReadyAndValidImplyGrant_A	361390817	109613445	0	0
ReqAndReadyImplyGrant_A	361390817	109613445	0	0
ReqImpliesValid_A	361390817	115687171	0	0
ValidKnown_A	361390817	360524246	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	109613445	0	0
T1	37893	1576	0	0
T2	428996	159034	0	0
T3	216531	292	0	0
T4	1758	64	0	0
T5	64658	11285	0	0
T6	1460	70	0	0
T10	763	41	0	0
T11	401270	129429	0	0
T16	10420	32	0	0
T17	1597	589	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	109613445	0	0
T1	37893	1576	0	0
T2	428996	159034	0	0
T3	216531	292	0	0
T4	1758	64	0	0
T5	64658	11285	0	0
T6	1460	70	0	0
T10	763	41	0	0
T11	401270	129429	0	0
T16	10420	32	0	0
T17	1597	589	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	109613445	0	0
T1	37893	1576	0	0
T2	428996	159034	0	0
T3	216531	292	0	0
T4	1758	64	0	0
T5	64658	11285	0	0
T6	1460	70	0	0
T10	763	41	0	0
T11	401270	129429	0	0
T16	10420	32	0	0
T17	1597	589	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	47220231	0	0
T1	37893	1600	0	0
T2	428996	50662	0	0
T3	216531	64	0	0
T4	1758	256	0	0
T5	64658	32861	0	0
T6	1460	265	0	0
T10	763	152	0	0
T11	401270	530688	0	0
T16	10420	128	0	0
T17	1597	158	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	115687171	0	0
T1	37893	1576	0	0
T2	428996	186526	0	0
T3	216531	292	0	0
T4	1758	64	0	0
T5	64658	11986	0	0
T6	1460	75	0	0
T10	763	41	0	0
T11	401270	129429	0	0
T16	10420	32	0	0
T17	1597	589	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	109613445	0	0
T1	37893	1576	0	0
T2	428996	159034	0	0
T3	216531	292	0	0
T4	1758	64	0	0
T5	64658	11285	0	0
T6	1460	70	0	0
T10	763	41	0	0
T11	401270	129429	0	0
T16	10420	32	0	0
T17	1597	589	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	109613445	0	0
T1	37893	1576	0	0
T2	428996	159034	0	0
T3	216531	292	0	0
T4	1758	64	0	0
T5	64658	11285	0	0
T6	1460	70	0	0
T10	763	41	0	0
T11	401270	129429	0	0
T16	10420	32	0	0
T17	1597	589	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	115687171	0	0
T1	37893	1576	0	0
T2	428996	186526	0	0
T3	216531	292	0	0
T4	1758	64	0	0
T5	64658	11986	0	0
T6	1460	75	0	0
T10	763	41	0	0
T11	401270	129429	0	0
T16	10420	32	0	0
T17	1597	589	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T10,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T10,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T10,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T10,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	361390817	360524246	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	361390817	109613445	0	0
GntImpliesValid_A	361390817	109613445	0	0
GrantKnown_A	361390817	360524246	0	0
IdxKnown_A	361390817	360524246	0	0
IndexIsCorrect_A	361390817	109613445	0	0
NoReadyValidNoGrant_A	361390817	47220231	0	0
Priority_A	361390817	115687171	0	0
ReadyAndValidImplyGrant_A	361390817	109613445	0	0
ReqAndReadyImplyGrant_A	361390817	109613445	0	0
ReqImpliesValid_A	361390817	115687171	0	0
ValidKnown_A	361390817	360524246	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	109613445	0	0
T1	37893	1576	0	0
T2	428996	159034	0	0
T3	216531	292	0	0
T4	1758	64	0	0
T5	64658	11285	0	0
T6	1460	70	0	0
T10	763	41	0	0
T11	401270	129429	0	0
T16	10420	32	0	0
T17	1597	589	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	109613445	0	0
T1	37893	1576	0	0
T2	428996	159034	0	0
T3	216531	292	0	0
T4	1758	64	0	0
T5	64658	11285	0	0
T6	1460	70	0	0
T10	763	41	0	0
T11	401270	129429	0	0
T16	10420	32	0	0
T17	1597	589	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	109613445	0	0
T1	37893	1576	0	0
T2	428996	159034	0	0
T3	216531	292	0	0
T4	1758	64	0	0
T5	64658	11285	0	0
T6	1460	70	0	0
T10	763	41	0	0
T11	401270	129429	0	0
T16	10420	32	0	0
T17	1597	589	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	47220231	0	0
T1	37893	1600	0	0
T2	428996	50662	0	0
T3	216531	64	0	0
T4	1758	256	0	0
T5	64658	32861	0	0
T6	1460	265	0	0
T10	763	152	0	0
T11	401270	530688	0	0
T16	10420	128	0	0
T17	1597	158	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	115687171	0	0
T1	37893	1576	0	0
T2	428996	186526	0	0
T3	216531	292	0	0
T4	1758	64	0	0
T5	64658	11986	0	0
T6	1460	75	0	0
T10	763	41	0	0
T11	401270	129429	0	0
T16	10420	32	0	0
T17	1597	589	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	109613445	0	0
T1	37893	1576	0	0
T2	428996	159034	0	0
T3	216531	292	0	0
T4	1758	64	0	0
T5	64658	11285	0	0
T6	1460	70	0	0
T10	763	41	0	0
T11	401270	129429	0	0
T16	10420	32	0	0
T17	1597	589	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	109613445	0	0
T1	37893	1576	0	0
T2	428996	159034	0	0
T3	216531	292	0	0
T4	1758	64	0	0
T5	64658	11285	0	0
T6	1460	70	0	0
T10	763	41	0	0
T11	401270	129429	0	0
T16	10420	32	0	0
T17	1597	589	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	115687171	0	0
T1	37893	1576	0	0
T2	428996	186526	0	0
T3	216531	292	0	0
T4	1758	64	0	0
T5	64658	11986	0	0
T6	1460	75	0	0
T10	763	41	0	0
T11	401270	129429	0	0
T16	10420	32	0	0
T17	1597	589	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T11
1	0	Covered	T2,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T4,T11
1	1	Covered	T2,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T11

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T11

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	361390817	360524246	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	361390817	93218769	0	0
GntImpliesValid_A	361390817	93218769	0	0
GrantKnown_A	361390817	360524246	0	0
IdxKnown_A	361390817	360524246	0	0
IndexIsCorrect_A	361390817	93218769	0	0
NoReadyValidNoGrant_A	361390817	41991695	0	0
Priority_A	361390817	99261704	0	0
ReadyAndValidImplyGrant_A	361390817	93218769	0	0
ReqAndReadyImplyGrant_A	361390817	93218769	0	0
ReqImpliesValid_A	361390817	99261704	0	0
ValidKnown_A	361390817	360524246	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	93218769	0	0
T2	428996	152217	0	0
T3	216531	0	0	0
T4	1758	24	0	0
T5	64658	10522	0	0
T6	1460	40	0	0
T10	763	0	0	0
T11	401270	127897	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	24654	0	0
T37	0	85176	0	0
T38	0	2396	0	0
T41	0	28713	0	0
T52	0	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	93218769	0	0
T2	428996	152217	0	0
T3	216531	0	0	0
T4	1758	24	0	0
T5	64658	10522	0	0
T6	1460	40	0	0
T10	763	0	0	0
T11	401270	127897	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	24654	0	0
T37	0	85176	0	0
T38	0	2396	0	0
T41	0	28713	0	0
T52	0	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	93218769	0	0
T2	428996	152217	0	0
T3	216531	0	0	0
T4	1758	24	0	0
T5	64658	10522	0	0
T6	1460	40	0	0
T10	763	0	0	0
T11	401270	127897	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	24654	0	0
T37	0	85176	0	0
T38	0	2396	0	0
T41	0	28713	0	0
T52	0	19	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	41991695	0	0
T2	428996	38443	0	0
T3	216531	0	0	0
T4	1758	0	0	0
T5	64658	31146	0	0
T6	1460	60	0	0
T10	763	0	0	0
T11	401270	524288	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	752627	0	0
T21	0	5	0	0
T24	0	649378	0	0
T38	0	129	0	0
T41	0	1890	0	0
T52	0	29	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	99261704	0	0
T2	428996	170574	0	0
T3	216531	0	0	0
T4	1758	24	0	0
T5	64658	11394	0	0
T6	1460	41	0	0
T10	763	0	0	0
T11	401270	127897	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	138514	0	0
T37	0	85176	0	0
T38	0	2396	0	0
T41	0	28713	0	0
T52	0	19	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	93218769	0	0
T2	428996	152217	0	0
T3	216531	0	0	0
T4	1758	24	0	0
T5	64658	10522	0	0
T6	1460	40	0	0
T10	763	0	0	0
T11	401270	127897	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	24654	0	0
T37	0	85176	0	0
T38	0	2396	0	0
T41	0	28713	0	0
T52	0	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	93218769	0	0
T2	428996	152217	0	0
T3	216531	0	0	0
T4	1758	24	0	0
T5	64658	10522	0	0
T6	1460	40	0	0
T10	763	0	0	0
T11	401270	127897	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	24654	0	0
T37	0	85176	0	0
T38	0	2396	0	0
T41	0	28713	0	0
T52	0	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	99261704	0	0
T2	428996	170574	0	0
T3	216531	0	0	0
T4	1758	24	0	0
T5	64658	11394	0	0
T6	1460	41	0	0
T10	763	0	0	0
T11	401270	127897	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	138514	0	0
T37	0	85176	0	0
T38	0	2396	0	0
T41	0	28713	0	0
T52	0	19	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T11
1	0	Covered	T2,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T4,T11
1	1	Covered	T2,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T11

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T11

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	361390817	360524246	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	361390817	93218679	0	0
GntImpliesValid_A	361390817	93218679	0	0
GrantKnown_A	361390817	360524246	0	0
IdxKnown_A	361390817	360524246	0	0
IndexIsCorrect_A	361390817	93218679	0	0
NoReadyValidNoGrant_A	361390817	41991695	0	0
Priority_A	361390817	99261614	0	0
ReadyAndValidImplyGrant_A	361390817	93218679	0	0
ReqAndReadyImplyGrant_A	361390817	93218679	0	0
ReqImpliesValid_A	361390817	99261614	0	0
ValidKnown_A	361390817	360524246	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	93218679	0	0
T2	428996	152217	0	0
T3	216531	0	0	0
T4	1758	24	0	0
T5	64658	10522	0	0
T6	1460	40	0	0
T10	763	0	0	0
T11	401270	127897	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	24654	0	0
T37	0	85176	0	0
T38	0	2396	0	0
T41	0	28713	0	0
T52	0	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	93218679	0	0
T2	428996	152217	0	0
T3	216531	0	0	0
T4	1758	24	0	0
T5	64658	10522	0	0
T6	1460	40	0	0
T10	763	0	0	0
T11	401270	127897	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	24654	0	0
T37	0	85176	0	0
T38	0	2396	0	0
T41	0	28713	0	0
T52	0	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	93218679	0	0
T2	428996	152217	0	0
T3	216531	0	0	0
T4	1758	24	0	0
T5	64658	10522	0	0
T6	1460	40	0	0
T10	763	0	0	0
T11	401270	127897	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	24654	0	0
T37	0	85176	0	0
T38	0	2396	0	0
T41	0	28713	0	0
T52	0	19	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	41991695	0	0
T2	428996	38443	0	0
T3	216531	0	0	0
T4	1758	0	0	0
T5	64658	31146	0	0
T6	1460	60	0	0
T10	763	0	0	0
T11	401270	524288	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	752627	0	0
T21	0	5	0	0
T24	0	649378	0	0
T38	0	129	0	0
T41	0	1890	0	0
T52	0	29	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	99261614	0	0
T2	428996	170574	0	0
T3	216531	0	0	0
T4	1758	24	0	0
T5	64658	11394	0	0
T6	1460	41	0	0
T10	763	0	0	0
T11	401270	127897	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	138514	0	0
T37	0	85176	0	0
T38	0	2396	0	0
T41	0	28713	0	0
T52	0	19	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	93218679	0	0
T2	428996	152217	0	0
T3	216531	0	0	0
T4	1758	24	0	0
T5	64658	10522	0	0
T6	1460	40	0	0
T10	763	0	0	0
T11	401270	127897	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	24654	0	0
T37	0	85176	0	0
T38	0	2396	0	0
T41	0	28713	0	0
T52	0	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	93218679	0	0
T2	428996	152217	0	0
T3	216531	0	0	0
T4	1758	24	0	0
T5	64658	10522	0	0
T6	1460	40	0	0
T10	763	0	0	0
T11	401270	127897	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	24654	0	0
T37	0	85176	0	0
T38	0	2396	0	0
T41	0	28713	0	0
T52	0	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	99261614	0	0
T2	428996	170574	0	0
T3	216531	0	0	0
T4	1758	24	0	0
T5	64658	11394	0	0
T6	1460	41	0	0
T10	763	0	0	0
T11	401270	127897	0	0
T16	10420	0	0	0
T17	1597	0	0	0
T20	129201	138514	0	0
T37	0	85176	0	0
T38	0	2396	0	0
T41	0	28713	0	0
T52	0	19	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361390817	360524246	0	0
T1	37893	37829	0	0
T2	428996	428922	0	0
T3	216531	216440	0	0
T4	1758	1629	0	0
T5	64658	64584	0	0
T6	1460	1334	0	0
T10	763	700	0	0
T11	401270	401257	0	0
T16	10420	10331	0	0
T17	1597	1524	0	0