Unified Coverage Report

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmEflashReqFifoRptrCheck_A	0	0	392152562	0	0	0
tb.dut.FpvSecCmEflashReqFifoWptrCheck_A	0	0	392152562	0	0	0
tb.dut.FpvSecCmEflashRspFifoRptrCheck_A	0	0	392152562	0	0	0
tb.dut.FpvSecCmEflashRspFifoWptrCheck_A	0	0	392152562	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoRptrCheck_A	0	0	392152562	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoWptrCheck_A	0	0	392152562	0	0	0
tb.dut.FpvSecCmRdReqFifoRptrCheck_A	0	0	392152562	0	0	0
tb.dut.FpvSecCmRdReqFifoWptrCheck_A	0	0	392152562	0	0	0
tb.dut.FpvSecCmRdSramReqFifoRptrCheck_A	0	0	392152562	0	0	0
tb.dut.FpvSecCmRdSramReqFifoWptrCheck_A	0	0	392152562	0	0	0
tb.dut.PrimRspPayLoad_A	0	0	392152562	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	392152562	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	392152562	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	392152562	0	0	1058
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	392152562	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	392152562	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	392152562	0	0	1058
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	392152562	0	0	1058
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	392152562	0	0	1058
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	392152562	0	0	1058
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	392152562	0	0	1058
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	392152562	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	392152562	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	392152562	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	392152562	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	392152562	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	392152562	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	392152562	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	392152562	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	1063	1063	0	0
tb.dut.FlashAddrKnown_A	0	0	392152562	265929980	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	392152562	391345016	0	0
tb.dut.FlashKnownO_A	0	0	392152562	391345016	0	0
tb.dut.FlashProgKnown_A	0	0	392152562	160975823	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	392152562	391345016	0	0
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	392152562	50	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	392152562	50	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	392152562	50	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	392152562	50	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	392152562	50	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	392152562	50	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	392152562	50	0	0
tb.dut.FpvSecCmRdRspFifoRptrCheck_A	0	0	392152562	50	0	0
tb.dut.FpvSecCmRdRspFifoWptrCheck_A	0	0	392152562	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	392152562	50	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	392152562	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	392152562	50	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	392152562	50	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	392152562	50	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	392152562	50	0	0
tb.dut.IntrErrO_A	0	0	392152562	391345016	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	392152562	391345016	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	392152562	391345016	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	392152562	391345016	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	392152562	391345016	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	392152562	391345016	0	0
tb.dut.MemRspPayLoad_A	0	0	392152562	5268202	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	392152562	391345016	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	392152562	391345016	0	0
tb.dut.MemTlDValidKnownO_A	0	0	392152562	391345016	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	392152562	391345016	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	392152562	391345016	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	392152562	391345016	0	0
tb.dut.RspPayLoad_A	0	0	391954062	45878397	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	392152562	391345016	0	0
tb.dut.TdoEnIsOne_A	0	0	392152562	391345016	0	0
tb.dut.TdoKnown_A	0	0	392152562	391345016	0	0
tb.dut.TlAReadyKnownO_A	0	0	392152562	391345016	0	0
tb.dut.TlDValidKnownO_A	0	0	392152562	391345016	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	394427675	4333	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	394427675	1951	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	394427675	1527	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	394427675	2146	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	394427675	1573	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	394427675	2619	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	394427675	2650	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	394427675	2259	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	394427675	2208	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	394427675	1860	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	394427675	2467	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	394427675	2413	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	394427675	1444	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	394427675	1834	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	394427675	1357	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	394427675	1421	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	394427675	1324	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	394427675	1489	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	394427675	1993	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	394427675	1457	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	394427675	1354	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	394427675	1793	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	394427675	2071	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	394427675	1914	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	394427675	2774	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	394427675	2564	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	394427675	1288	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	394427675	1417	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	394427675	2693	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	394427675	2649	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	394427675	1703	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	394427675	2601	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	394427675	2243	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	394427675	1586	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	394427675	2247	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	394427675	2699	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	394427675	2367	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	394427675	2512	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	394427675	869	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	394427675	1773	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	394427675	843	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	394427675	1011	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	394427675	1883	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	394427675	1923	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	394427675	1438	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	394427675	937	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	394427675	1847	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	394427675	1337	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	394427675	2267	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	394427675	1845	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	394427675	2590	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	394427675	2613	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	394427675	1813	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	394427675	1378	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	394427675	1411	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	394427675	2584	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	394427675	1900	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	394427675	1617	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	394427675	1970	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	394427675	2057	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	394427675	2488	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	394427675	1981	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	394427675	1110	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	394427675	2044	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	394427675	2050	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	394427675	1466	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	394427675	988	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	394427675	2092	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	394427675	1584	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	394427675	2000	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	394427675	2109	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	394427675	2626	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	394427675	1583	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	394427675	2614	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	394427675	2099	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	394427675	2575	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	394427675	2690	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	394427675	1085	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	394427675	1828	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	394427675	1381	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	394427675	1858	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	394427675	989	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	394427675	1882	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	394427675	1418	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	394427675	1750	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	394427675	1873	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	394427675	1296	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	392152562	50	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	392152562	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	392152562	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	392152562	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	392152562	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	392152562	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	392152562	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	392152562	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	392152562	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	392152562	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	392152562	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	392152562	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	392152562	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	392152562	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	392152562	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	392152562	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	392152562	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	392152562	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	392152562	25	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	394427645	34318919	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	394427645	393538186	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	394427645	393538186	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	394427645	46538513	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	394427645	393538186	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	394427645	393538186	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
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tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
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tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
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tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
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tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
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tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
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tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
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tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
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tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
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tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
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tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
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tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
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tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
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tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
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tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	1273	1273	0	0

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	ASSERT	PROPERTIES	SEQUENCES
Total	1020	0	10
Category 0	1020	0	10

	ASSERT	PROPERTIES	SEQUENCES
Total	1020	0	10
Severity 0	1020	0	10

	NUMBER	PERCENT
Total Number	1020	100.00
Uncovered	29	2.84
Success	991	97.16
Failure	0	0.00
Incomplete	15	1.47
Without Attempts	0	0.00

	NUMBER	PERCENT
Total Number	10	100.00
Uncovered	4	40.00
All Matches	6	60.00
First Matches	6	60.00