Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	338515	1		T1	1		T2	2		T3	2
all_values[1]	338515	1		T1	1		T2	2		T3	2
all_values[2]	338515	1		T1	1		T2	2		T3	2
all_values[3]	338515	1		T1	1		T2	2		T3	2
all_values[4]	338515	1		T1	1		T2	2		T3	2
all_values[5]	338515	1		T1	1		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	683412	1		T1	6		T2	12		T3	12
auto[1]	1347678	1		T4	147520		T5	4576		T36	19656

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	997064	1		T1	4		T2	7		T3	7
auto[1]	1034026	1		T1	2		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	338355	1		T1	1		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	160	1		T280	3		T281	4		T339	2
all_values[1]	auto[0]	auto[1]	338351	1		T1	1		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	164	1		T280	4		T281	2		T339	6
all_values[2]	auto[0]	auto[0]	1604	1		T1	1		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	53	1		T279	1		T280	1		T281	1
all_values[2]	auto[1]	auto[0]	336797	1		T4	36880		T5	1144		T36	4914
all_values[2]	auto[1]	auto[1]	61	1		T279	2		T280	1		T281	1
all_values[3]	auto[0]	auto[0]	1620	1		T1	1		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	61	1		T280	1		T281	1		T339	1
all_values[3]	auto[1]	auto[0]	78061	1		T5	572		T36	1638		T26	1477
all_values[3]	auto[1]	auto[1]	258773	1		T4	36880		T5	572		T36	3276
all_values[4]	auto[0]	auto[0]	1142	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	541	1		T2	1		T3	1		T10	1
all_values[4]	auto[1]	auto[0]	239494	1		T4	35366		T5	572		T36	3276
all_values[4]	auto[1]	auto[1]	97338	1		T4	1514		T5	572		T36	1638
all_values[5]	auto[0]	auto[0]	1585	1		T1	1		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	100	1		T38	1		T39	1		T40	1
all_values[5]	auto[1]	auto[0]	336761	1		T4	36880		T5	1144		T36	4914
all_values[5]	auto[1]	auto[1]	69	1		T279	2		T280	1		T339	2