Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
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Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv



Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00
Crosses 16 0 16 100.00


Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
erase_cp 2 0 2 100.00 100 1 1 0
op_cp 4 0 4 100.00 100 1 1 0
op_evict_cp 5 0 5 100.00 100 1 1 0
part_cp 4 0 4 100.00 100 1 1 0


Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
op_part_cross 16 0 16 100.00 100 1 1 0


Summary for Variable erase_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for erase_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashErasePage] 237982 1 T2 600 T4 835 T5 308
auto[FlashEraseBank] 265710 1 T3 3 T4 679 T5 264



Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for op_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashOpRead] 248286 1 T2 200 T3 3 T4 1514
auto[FlashOpProgram] 236524 1 T2 100 T10 2 T6 2164
auto[FlashOpErase] 14882 1 T2 100 T46 130 T76 100
auto[FlashOpInvalid] 4000 1 T2 200 T76 200 T153 200



Summary for Variable op_evict_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for op_evict_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
op[FlashOpRead] 248286 1 T2 200 T3 3 T4 1514
op[FlashOpProgram] 236524 1 T2 100 T10 2 T6 2164
op[FlashOpErase] 14882 1 T2 100 T46 130 T76 100
read_erase_read 552 1 T65 2 T31 1 T33 1
read_prog_read 845 1 T6 3 T25 1 T43 3



Summary for Variable part_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for part_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashPartData] 364901 1 T2 588 T3 3 T4 1514
auto[FlashPartInfo] 135234 1 T2 12 T5 572 T10 3
auto[FlashPartInfo1] 770 1 T6 4 T43 1 T137 3
auto[FlashPartInfo2] 2787 1 T6 8 T26 5 T43 4



Summary for Cross op_part_cross

Samples crossed: part_cp op_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for op_part_cross

Bins
part_cpop_cpCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashPartData] auto[FlashOpRead] 178345 1 T2 196 T3 3 T4 1514
auto[FlashPartData] auto[FlashOpProgram] 178991 1 T2 98 T6 1925 T59 1
auto[FlashPartData] auto[FlashOpErase] 3635 1 T2 98 T76 96 T47 1
auto[FlashPartData] auto[FlashOpInvalid] 3930 1 T2 196 T76 192 T153 194
auto[FlashPartInfo] auto[FlashOpRead] 67639 1 T2 4 T5 572 T10 1
auto[FlashPartInfo] auto[FlashOpProgram] 56322 1 T2 2 T10 2 T6 236
auto[FlashPartInfo] auto[FlashOpErase] 11217 1 T2 2 T46 130 T76 3
auto[FlashPartInfo] auto[FlashOpInvalid] 56 1 T2 4 T76 6 T153 6
auto[FlashPartInfo1] auto[FlashOpRead] 592 1 T6 4 T43 1 T137 3
auto[FlashPartInfo1] auto[FlashOpProgram] 166 1 T157 32 T158 32 T413 1
auto[FlashPartInfo1] auto[FlashOpErase] 4 1 T129 1 T414 1 T415 1
auto[FlashPartInfo1] auto[FlashOpInvalid] 8 1 T129 2 T414 2 T415 2
auto[FlashPartInfo2] auto[FlashOpRead] 1710 1 T6 5 T43 1 T76 2
auto[FlashPartInfo2] auto[FlashOpProgram] 1045 1 T6 3 T26 5 T43 3
auto[FlashPartInfo2] auto[FlashOpErase] 26 1 T76 1 T139 2 T140 1
auto[FlashPartInfo2] auto[FlashOpInvalid] 6 1 T76 2 T416 2 T129 2

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