Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29225	1		T2	400		T46	264		T76	400
auto[1]	48	1		T37	1		T139	5		T140	1
auto[2]	72	1		T139	2		T140	9		T417	1
auto[3]	259	1		T6	1		T27	1		T152	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7411	1		T2	100		T46	66		T76	100
evic_idx[1]	7397	1		T2	100		T46	66		T76	100
evic_idx[2]	7404	1		T2	100		T6	1		T46	66
evic_idx[3]	7392	1		T2	100		T46	66		T76	100

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28708	1		T2	400		T46	264		T76	400
evic_op[2]	288	1		T6	1		T27	1		T65	16

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7102	1		T2	100		T46	66		T76	100
evic_idx[0]	evic_op[1]	auto[1]	11	1		T139	2		T156	2		T111	1
evic_idx[0]	evic_op[1]	auto[2]	12	1		T140	3		T111	1		T418	2
evic_idx[0]	evic_op[1]	auto[3]	60	1		T139	5		T140	4		T143	5
evic_idx[0]	evic_op[2]	auto[0]	59	1		T65	4		T37	1		T365	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T81	1		T419	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	4	1		T420	1		T421	1		T422	1
evic_idx[0]	evic_op[2]	auto[3]	9	1		T421	1		T134	1		T423	1
evic_idx[1]	evic_op[1]	auto[0]	7097	1		T2	100		T46	66		T76	100
evic_idx[1]	evic_op[1]	auto[1]	13	1		T139	2		T140	1		T156	3
evic_idx[1]	evic_op[1]	auto[2]	12	1		T140	3		T111	2		T418	3
evic_idx[1]	evic_op[1]	auto[3]	53	1		T139	4		T140	4		T143	1
evic_idx[1]	evic_op[2]	auto[0]	56	1		T65	4		T365	1		T72	4
evic_idx[1]	evic_op[2]	auto[1]	1	1		T424	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	3	1		T417	1		T425	2		-	-
evic_idx[1]	evic_op[2]	auto[3]	10	1		T27	1		T426	1		T226	1
evic_idx[2]	evic_op[1]	auto[0]	7102	1		T2	100		T46	66		T76	100
evic_idx[2]	evic_op[1]	auto[1]	8	1		T139	1		T225	1		T156	1
evic_idx[2]	evic_op[1]	auto[2]	11	1		T139	1		T140	2		T111	1
evic_idx[2]	evic_op[1]	auto[3]	57	1		T139	4		T140	4		T143	3
evic_idx[2]	evic_op[2]	auto[0]	56	1		T65	4		T365	1		T72	4
evic_idx[2]	evic_op[2]	auto[1]	4	1		T37	1		T417	1		T427	1
evic_idx[2]	evic_op[2]	auto[2]	3	1		T226	1		T428	1		T429	1
evic_idx[2]	evic_op[2]	auto[3]	11	1		T6	1		T428	1		T135	1
evic_idx[3]	evic_op[1]	auto[0]	7101	1		T2	100		T46	66		T76	100
evic_idx[3]	evic_op[1]	auto[1]	7	1		T156	1		T111	1		T430	2
evic_idx[3]	evic_op[1]	auto[2]	12	1		T139	1		T140	1		T156	1
evic_idx[3]	evic_op[1]	auto[3]	50	1		T139	3		T140	4		T143	3
evic_idx[3]	evic_op[2]	auto[0]	56	1		T65	4		T365	1		T72	4
evic_idx[3]	evic_op[2]	auto[1]	2	1		T81	1		T431	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	3	1		T134	1		T422	1		T432	1
evic_idx[3]	evic_op[2]	auto[3]	9	1		T152	1		T164	1		T165	1