Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	36012	1		T4	14171		T173	15951		T346	2365
rd_lvl[2]	53997	1		T4	10053		T173	11681		T241	12598
rd_lvl[3]	14296	1		T241	425		T229	2367		T346	351
rd_lvl[4]	30633	1		T229	196		T346	431		T347	237
rd_lvl[5]	17393	1		T229	1632		T346	256		T347	55
rd_lvl[6]	17302	1		T229	266		T346	7		T348	576
rd_lvl[7]	10803	1		T36	1778		T229	1379		T346	224
rd_lvl[8]	7119	1		T36	1497		T229	1378		T346	223
rd_lvl[9]	4538	1		T229	1378		T346	350		T348	149
rd_lvl[10]	5193	1		T346	96		T348	152		T349	2
rd_lvl[11]	5101	1		T346	89		T350	276		T351	122
rd_lvl[12]	3852	1		T5	328		T350	272		T136	47
rd_lvl[13]	2793	1		T5	177		T145	573		T352	55
rd_lvl[14]	5837	1		T145	1065		T34	1294		T346	89
rd_lvl[15]	3824	1		T5	67		T34	266		T35	397