Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	338515	1		T1	1		T2	2		T3	2
all_pins[1]	338515	1		T1	1		T2	2		T3	2
all_pins[2]	338515	1		T1	1		T2	2		T3	2
all_pins[3]	338515	1		T1	1		T2	2		T3	2
all_pins[4]	338515	1		T1	1		T2	2		T3	2
all_pins[5]	338515	1		T1	1		T2	2		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1696887	1		T1	6		T2	12		T3	12
values[0x1]	334203	1		T4	26702		T5	1144		T36	4913
transitions[0x0=>0x1]	301378	1		T4	24224		T5	1144		T36	4913
transitions[0x1=>0x0]	301359	1		T4	24224		T5	1144		T36	4913

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	338355	1		T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	160	1		T280	3		T281	4		T339	2
all_pins[0]	transitions[0x0=>0x1]	78	1		T281	2		T339	1		T340	5
all_pins[0]	transitions[0x1=>0x0]	82	1		T280	1		T339	5		T340	2
all_pins[1]	values[0x0]	338351	1		T1	1		T2	2		T3	2
all_pins[1]	values[0x1]	164	1		T280	4		T281	2		T339	6
all_pins[1]	transitions[0x0=>0x1]	128	1		T280	3		T281	1		T339	4
all_pins[1]	transitions[0x1=>0x0]	3906	1		T35	1132		T355	1241		T356	1056
all_pins[2]	values[0x0]	334573	1		T1	1		T2	2		T3	2
all_pins[2]	values[0x1]	3942	1		T35	1132		T355	1241		T356	1056
all_pins[2]	transitions[0x0=>0x1]	42	1		T279	1		T281	1		T339	1
all_pins[2]	transitions[0x1=>0x0]	219011	1		T4	24224		T5	572		T36	3275
all_pins[3]	values[0x0]	115604	1		T1	1		T2	2		T3	2
all_pins[3]	values[0x1]	222911	1		T4	24224		T5	572		T36	3275
all_pins[3]	transitions[0x0=>0x1]	194156	1		T4	21746		T5	572		T36	3275
all_pins[3]	transitions[0x1=>0x0]	78202	1		T5	572		T36	1638		T26	1476
all_pins[4]	values[0x0]	231558	1		T1	1		T2	2		T3	2
all_pins[4]	values[0x1]	106957	1		T4	2478		T5	572		T36	1638
all_pins[4]	transitions[0x0=>0x1]	106939	1		T4	2478		T5	572		T36	1638
all_pins[4]	transitions[0x1=>0x0]	51	1		T279	2		T280	1		T339	2
all_pins[5]	values[0x0]	338446	1		T1	1		T2	2		T3	2
all_pins[5]	values[0x1]	69	1		T279	2		T280	1		T339	2
all_pins[5]	transitions[0x0=>0x1]	35	1		T279	2		T280	1		T339	2
all_pins[5]	transitions[0x1=>0x0]	107	1		T280	2		T281	3		T339	2