Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::sw_error_cg
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Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::sw_error_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
85.71 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv



Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::sw_error_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 1 6 85.71


Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::sw_error_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mp_err 1 0 1 100.00 100 1 1 0
cp_op_err 1 0 1 100.00 100 1 1 0
cp_prog_err 1 0 1 100.00 100 1 1 0
cp_prog_type_err 1 0 1 100.00 100 1 1 0
cp_prog_win_err 1 0 1 100.00 100 1 1 0
cp_rd_err 1 0 1 100.00 100 1 1 0
cp_update_err 1 1 0 0.00 100 1 1 0


Summary for Variable cp_mp_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mp_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
seen 97773 1 T43 5124 T27 1 T44 5



Summary for Variable cp_op_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_op_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
seen 4000 1 T2 200 T76 200 T153 200



Summary for Variable cp_prog_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_prog_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
seen 15 1 T7 5 T8 5 T9 5



Summary for Variable cp_prog_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_prog_type_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
seen 535 1 T64 95 T85 110 T86 107



Summary for Variable cp_prog_win_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_prog_win_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
seen 301 1 T44 17 T45 18 T215 25



Summary for Variable cp_rd_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_rd_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
seen 70076 1 T25 1 T43 2096 T27 1



Summary for Variable cp_update_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_update_err

Uncovered bins
NAMECOUNTAT LEASTNUMBER
seen 0 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%