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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.16 95.71 94.01 98.31 91.84 98.25 96.80 98.18


Total test records in report: 1278
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T1085 /workspace/coverage/default/61.flash_ctrl_otp_reset.801399747 Jul 28 07:33:33 PM PDT 24 Jul 28 07:35:43 PM PDT 24 157346300 ps
T1086 /workspace/coverage/default/17.flash_ctrl_invalid_op.3805433101 Jul 28 07:30:26 PM PDT 24 Jul 28 07:31:43 PM PDT 24 2229478300 ps
T1087 /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.1431665942 Jul 28 07:29:34 PM PDT 24 Jul 28 07:32:26 PM PDT 24 4159670600 ps
T1088 /workspace/coverage/default/2.flash_ctrl_ro_derr.2833212140 Jul 28 07:26:25 PM PDT 24 Jul 28 07:28:56 PM PDT 24 733779500 ps
T1089 /workspace/coverage/default/4.flash_ctrl_smoke_hw.2132382783 Jul 28 07:27:05 PM PDT 24 Jul 28 07:27:29 PM PDT 24 25845500 ps
T1090 /workspace/coverage/default/12.flash_ctrl_smoke.83710493 Jul 28 07:29:15 PM PDT 24 Jul 28 07:30:52 PM PDT 24 76153400 ps
T1091 /workspace/coverage/default/3.flash_ctrl_error_prog_type.953667615 Jul 28 07:26:34 PM PDT 24 Jul 28 08:09:36 PM PDT 24 3032741500 ps
T1092 /workspace/coverage/default/14.flash_ctrl_alert_test.264506189 Jul 28 07:29:55 PM PDT 24 Jul 28 07:30:09 PM PDT 24 86949800 ps
T222 /workspace/coverage/default/0.flash_ctrl_rd_intg.3128078946 Jul 28 07:26:02 PM PDT 24 Jul 28 07:26:34 PM PDT 24 279035800 ps
T1093 /workspace/coverage/default/6.flash_ctrl_otp_reset.321094647 Jul 28 07:27:38 PM PDT 24 Jul 28 07:29:52 PM PDT 24 727579200 ps
T1094 /workspace/coverage/default/24.flash_ctrl_intr_rd.2870732189 Jul 28 07:31:30 PM PDT 24 Jul 28 07:35:38 PM PDT 24 1364307600 ps
T1095 /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.65042817 Jul 28 07:26:22 PM PDT 24 Jul 28 07:26:36 PM PDT 24 16683100 ps
T1096 /workspace/coverage/default/3.flash_ctrl_fetch_code.1890479835 Jul 28 07:26:31 PM PDT 24 Jul 28 07:26:57 PM PDT 24 313459400 ps
T1097 /workspace/coverage/default/6.flash_ctrl_intr_rd.2056572523 Jul 28 07:27:45 PM PDT 24 Jul 28 07:29:53 PM PDT 24 2095413400 ps
T1098 /workspace/coverage/default/17.flash_ctrl_rw_evict.3748947691 Jul 28 07:30:30 PM PDT 24 Jul 28 07:31:01 PM PDT 24 29206800 ps
T1099 /workspace/coverage/default/38.flash_ctrl_rw_evict.3303505750 Jul 28 07:32:42 PM PDT 24 Jul 28 07:33:13 PM PDT 24 46172900 ps
T412 /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.343717970 Jul 28 07:30:35 PM PDT 24 Jul 28 07:32:59 PM PDT 24 5869803200 ps
T1100 /workspace/coverage/default/0.flash_ctrl_connect.675944566 Jul 28 07:26:03 PM PDT 24 Jul 28 07:26:17 PM PDT 24 42878500 ps
T1101 /workspace/coverage/default/1.flash_ctrl_prog_reset.3268575334 Jul 28 07:26:17 PM PDT 24 Jul 28 07:26:30 PM PDT 24 56901100 ps
T1102 /workspace/coverage/default/10.flash_ctrl_ro.4010357727 Jul 28 07:28:54 PM PDT 24 Jul 28 07:30:45 PM PDT 24 2277609400 ps
T1103 /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.2685507024 Jul 28 07:32:05 PM PDT 24 Jul 28 07:32:36 PM PDT 24 27903100 ps
T1104 /workspace/coverage/default/37.flash_ctrl_rw_evict.1689834627 Jul 28 07:32:43 PM PDT 24 Jul 28 07:33:14 PM PDT 24 268330600 ps
T1105 /workspace/coverage/default/9.flash_ctrl_re_evict.2036437197 Jul 28 07:28:50 PM PDT 24 Jul 28 07:29:24 PM PDT 24 122873500 ps
T1106 /workspace/coverage/default/1.flash_ctrl_full_mem_access.804105915 Jul 28 07:26:08 PM PDT 24 Jul 28 08:10:37 PM PDT 24 143371872200 ps
T377 /workspace/coverage/default/4.flash_ctrl_sec_info_access.1517541281 Jul 28 07:27:28 PM PDT 24 Jul 28 07:28:24 PM PDT 24 4220393000 ps
T220 /workspace/coverage/default/3.flash_ctrl_ro_derr.1230597954 Jul 28 07:26:50 PM PDT 24 Jul 28 07:29:18 PM PDT 24 2428686600 ps
T1107 /workspace/coverage/default/72.flash_ctrl_otp_reset.3246625024 Jul 28 07:33:43 PM PDT 24 Jul 28 07:35:55 PM PDT 24 305050800 ps
T388 /workspace/coverage/default/36.flash_ctrl_sec_info_access.348379130 Jul 28 07:32:33 PM PDT 24 Jul 28 07:33:28 PM PDT 24 406977500 ps
T1108 /workspace/coverage/default/42.flash_ctrl_sec_info_access.1154462490 Jul 28 07:33:01 PM PDT 24 Jul 28 07:33:53 PM PDT 24 737166600 ps
T1109 /workspace/coverage/default/49.flash_ctrl_alert_test.1391657208 Jul 28 07:33:23 PM PDT 24 Jul 28 07:33:37 PM PDT 24 22832100 ps
T1110 /workspace/coverage/default/2.flash_ctrl_error_mp.1583777270 Jul 28 07:26:26 PM PDT 24 Jul 28 08:08:48 PM PDT 24 10012834200 ps
T1111 /workspace/coverage/default/11.flash_ctrl_otp_reset.1605921998 Jul 28 07:29:02 PM PDT 24 Jul 28 07:31:12 PM PDT 24 115996100 ps
T1112 /workspace/coverage/default/14.flash_ctrl_re_evict.3312448557 Jul 28 07:29:51 PM PDT 24 Jul 28 07:30:25 PM PDT 24 282477600 ps
T1113 /workspace/coverage/default/2.flash_ctrl_ro.3726491501 Jul 28 07:26:28 PM PDT 24 Jul 28 07:28:30 PM PDT 24 576274500 ps
T1114 /workspace/coverage/default/3.flash_ctrl_rw_serr.1585345467 Jul 28 07:26:45 PM PDT 24 Jul 28 07:29:54 PM PDT 24 1591679300 ps
T1115 /workspace/coverage/default/28.flash_ctrl_sec_info_access.3875802349 Jul 28 07:31:50 PM PDT 24 Jul 28 07:33:08 PM PDT 24 2612308100 ps
T1116 /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.2192200058 Jul 28 07:26:31 PM PDT 24 Jul 28 07:26:45 PM PDT 24 15441200 ps
T1117 /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.2527849493 Jul 28 07:30:22 PM PDT 24 Jul 28 07:30:36 PM PDT 24 15655700 ps
T1118 /workspace/coverage/default/21.flash_ctrl_alert_test.852698086 Jul 28 07:31:11 PM PDT 24 Jul 28 07:31:25 PM PDT 24 40643400 ps
T415 /workspace/coverage/default/1.flash_ctrl_invalid_op.2826434384 Jul 28 07:26:10 PM PDT 24 Jul 28 07:27:23 PM PDT 24 18203246000 ps
T1119 /workspace/coverage/default/6.flash_ctrl_rw.3498773651 Jul 28 07:27:44 PM PDT 24 Jul 28 07:37:37 PM PDT 24 14858136200 ps
T1120 /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.760483571 Jul 28 07:26:36 PM PDT 24 Jul 28 07:28:12 PM PDT 24 3060720300 ps
T117 /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.2028452955 Jul 28 07:27:21 PM PDT 24 Jul 28 07:27:39 PM PDT 24 707216000 ps
T1121 /workspace/coverage/default/2.flash_ctrl_sec_info_access.3129145145 Jul 28 07:26:31 PM PDT 24 Jul 28 07:27:46 PM PDT 24 2234310900 ps
T1122 /workspace/coverage/default/18.flash_ctrl_invalid_op.4227057573 Jul 28 07:30:40 PM PDT 24 Jul 28 07:31:49 PM PDT 24 6696029100 ps
T1123 /workspace/coverage/default/4.flash_ctrl_connect.194152988 Jul 28 07:27:21 PM PDT 24 Jul 28 07:27:37 PM PDT 24 40923900 ps
T1124 /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.2505436600 Jul 28 07:26:24 PM PDT 24 Jul 28 07:27:02 PM PDT 24 747485600 ps
T1125 /workspace/coverage/default/28.flash_ctrl_intr_rd.2228736590 Jul 28 07:31:52 PM PDT 24 Jul 28 07:36:16 PM PDT 24 16518886600 ps
T1126 /workspace/coverage/default/6.flash_ctrl_error_prog_win.1997646594 Jul 28 07:27:45 PM PDT 24 Jul 28 07:45:24 PM PDT 24 792297300 ps
T1127 /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.3376779286 Jul 28 07:31:32 PM PDT 24 Jul 28 07:33:40 PM PDT 24 28665740900 ps
T1128 /workspace/coverage/default/10.flash_ctrl_rw.683917110 Jul 28 07:28:58 PM PDT 24 Jul 28 07:38:21 PM PDT 24 7805491500 ps
T1129 /workspace/coverage/default/1.flash_ctrl_smoke_hw.1022653167 Jul 28 07:26:11 PM PDT 24 Jul 28 07:26:37 PM PDT 24 17644100 ps
T1130 /workspace/coverage/default/45.flash_ctrl_connect.1247802602 Jul 28 07:33:10 PM PDT 24 Jul 28 07:33:26 PM PDT 24 43440800 ps
T1131 /workspace/coverage/default/43.flash_ctrl_sec_info_access.2660231442 Jul 28 07:33:13 PM PDT 24 Jul 28 07:34:05 PM PDT 24 669824200 ps
T1132 /workspace/coverage/default/39.flash_ctrl_disable.3149666976 Jul 28 07:32:45 PM PDT 24 Jul 28 07:33:07 PM PDT 24 13724800 ps
T1133 /workspace/coverage/default/57.flash_ctrl_connect.3403547863 Jul 28 07:33:30 PM PDT 24 Jul 28 07:33:46 PM PDT 24 15801900 ps
T1134 /workspace/coverage/default/36.flash_ctrl_disable.310752997 Jul 28 07:32:34 PM PDT 24 Jul 28 07:32:56 PM PDT 24 40493200 ps
T1135 /workspace/coverage/default/7.flash_ctrl_error_prog_win.1765371674 Jul 28 07:27:57 PM PDT 24 Jul 28 07:39:58 PM PDT 24 4097191100 ps
T1136 /workspace/coverage/default/33.flash_ctrl_alert_test.3716758138 Jul 28 07:32:23 PM PDT 24 Jul 28 07:32:37 PM PDT 24 23622800 ps
T1137 /workspace/coverage/default/11.flash_ctrl_invalid_op.1513605299 Jul 28 07:29:03 PM PDT 24 Jul 28 07:30:25 PM PDT 24 2027174400 ps
T1138 /workspace/coverage/default/23.flash_ctrl_otp_reset.4144968736 Jul 28 07:31:18 PM PDT 24 Jul 28 07:33:29 PM PDT 24 65502900 ps
T1139 /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.459267733 Jul 28 07:27:12 PM PDT 24 Jul 28 07:27:34 PM PDT 24 24516600 ps
T1140 /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.3172582256 Jul 28 07:28:31 PM PDT 24 Jul 28 07:40:55 PM PDT 24 80132147700 ps
T279 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.261446787 Jul 28 07:23:41 PM PDT 24 Jul 28 07:23:55 PM PDT 24 45535300 ps
T68 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1789124987 Jul 28 07:23:12 PM PDT 24 Jul 28 07:23:28 PM PDT 24 335417600 ps
T69 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3534475776 Jul 28 07:23:32 PM PDT 24 Jul 28 07:23:47 PM PDT 24 194884800 ps
T280 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.862221117 Jul 28 07:23:49 PM PDT 24 Jul 28 07:24:02 PM PDT 24 146303200 ps
T70 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1610345918 Jul 28 07:23:18 PM PDT 24 Jul 28 07:23:35 PM PDT 24 66945400 ps
T99 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.839419824 Jul 28 07:22:59 PM PDT 24 Jul 28 07:23:38 PM PDT 24 1264459100 ps
T100 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.250584062 Jul 28 07:22:50 PM PDT 24 Jul 28 07:23:08 PM PDT 24 64703000 ps
T235 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2879571587 Jul 28 07:22:52 PM PDT 24 Jul 28 07:23:10 PM PDT 24 367993000 ps
T260 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.948458180 Jul 28 07:23:30 PM PDT 24 Jul 28 07:23:47 PM PDT 24 215972000 ps
T281 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2924453912 Jul 28 07:23:37 PM PDT 24 Jul 28 07:23:51 PM PDT 24 51145600 ps
T339 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1835192097 Jul 28 07:22:47 PM PDT 24 Jul 28 07:23:01 PM PDT 24 55570400 ps
T233 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2454073494 Jul 28 07:23:18 PM PDT 24 Jul 28 07:38:21 PM PDT 24 1565063200 ps
T234 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2638451565 Jul 28 07:23:39 PM PDT 24 Jul 28 07:31:19 PM PDT 24 5796828600 ps
T236 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.607629544 Jul 28 07:23:17 PM PDT 24 Jul 28 07:23:37 PM PDT 24 267110300 ps
T1141 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3680250092 Jul 28 07:22:50 PM PDT 24 Jul 28 07:23:06 PM PDT 24 41780700 ps
T255 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.322076714 Jul 28 07:23:06 PM PDT 24 Jul 28 07:23:20 PM PDT 24 76991000 ps
T338 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3376641840 Jul 28 07:22:55 PM PDT 24 Jul 28 07:23:36 PM PDT 24 1678327000 ps
T261 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2546191945 Jul 28 07:22:53 PM PDT 24 Jul 28 07:23:11 PM PDT 24 83124000 ps
T1142 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.4189712954 Jul 28 07:23:40 PM PDT 24 Jul 28 07:23:55 PM PDT 24 34481000 ps
T340 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3954662035 Jul 28 07:22:43 PM PDT 24 Jul 28 07:22:57 PM PDT 24 18647800 ps
T1143 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1966778662 Jul 28 07:23:19 PM PDT 24 Jul 28 07:23:35 PM PDT 24 37465000 ps
T341 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3564325962 Jul 28 07:23:45 PM PDT 24 Jul 28 07:23:58 PM PDT 24 55064800 ps
T249 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.98727766 Jul 28 07:23:41 PM PDT 24 Jul 28 07:24:01 PM PDT 24 571959900 ps
T262 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2219323145 Jul 28 07:23:33 PM PDT 24 Jul 28 07:23:49 PM PDT 24 343707800 ps
T342 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1150695755 Jul 28 07:23:40 PM PDT 24 Jul 28 07:23:53 PM PDT 24 241829000 ps
T250 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2186333037 Jul 28 07:23:17 PM PDT 24 Jul 28 07:38:24 PM PDT 24 1580971400 ps
T251 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2655292326 Jul 28 07:22:48 PM PDT 24 Jul 28 07:23:04 PM PDT 24 40869400 ps
T263 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3211764017 Jul 28 07:23:42 PM PDT 24 Jul 28 07:23:59 PM PDT 24 37585900 ps
T252 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2815498732 Jul 28 07:22:52 PM PDT 24 Jul 28 07:29:24 PM PDT 24 585337700 ps
T1144 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.394554148 Jul 28 07:23:24 PM PDT 24 Jul 28 07:23:40 PM PDT 24 36304800 ps
T1145 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.456109748 Jul 28 07:22:53 PM PDT 24 Jul 28 07:23:09 PM PDT 24 104384800 ps
T343 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1562231862 Jul 28 07:23:46 PM PDT 24 Jul 28 07:24:00 PM PDT 24 18002100 ps
T264 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1625726514 Jul 28 07:23:06 PM PDT 24 Jul 28 07:24:14 PM PDT 24 1634123500 ps
T1146 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.4246411062 Jul 28 07:23:38 PM PDT 24 Jul 28 07:23:54 PM PDT 24 15756300 ps
T1147 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1647017773 Jul 28 07:22:47 PM PDT 24 Jul 28 07:23:03 PM PDT 24 19809100 ps
T1148 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.310805772 Jul 28 07:23:06 PM PDT 24 Jul 28 07:23:22 PM PDT 24 13481600 ps
T1149 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1156536304 Jul 28 07:23:06 PM PDT 24 Jul 28 07:23:20 PM PDT 24 29577900 ps
T345 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3488455285 Jul 28 07:23:44 PM PDT 24 Jul 28 07:23:58 PM PDT 24 268236800 ps
T253 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2054528228 Jul 28 07:22:54 PM PDT 24 Jul 28 07:23:10 PM PDT 24 138707500 ps
T265 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1591308931 Jul 28 07:23:16 PM PDT 24 Jul 28 07:23:33 PM PDT 24 62200300 ps
T254 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1547646672 Jul 28 07:23:35 PM PDT 24 Jul 28 07:23:55 PM PDT 24 540205700 ps
T294 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1283891559 Jul 28 07:23:23 PM PDT 24 Jul 28 07:23:42 PM PDT 24 513336600 ps
T266 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2826745521 Jul 28 07:23:13 PM PDT 24 Jul 28 07:23:31 PM PDT 24 430574500 ps
T344 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.570001064 Jul 28 07:23:09 PM PDT 24 Jul 28 07:23:22 PM PDT 24 30519900 ps
T267 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3803599776 Jul 28 07:23:32 PM PDT 24 Jul 28 07:23:49 PM PDT 24 58694600 ps
T1150 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3311818694 Jul 28 07:23:11 PM PDT 24 Jul 28 07:23:25 PM PDT 24 67946100 ps
T299 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.718280550 Jul 28 07:23:35 PM PDT 24 Jul 28 07:31:16 PM PDT 24 180173700 ps
T318 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2391568789 Jul 28 07:23:08 PM PDT 24 Jul 28 07:23:40 PM PDT 24 239742000 ps
T1151 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2990061372 Jul 28 07:23:16 PM PDT 24 Jul 28 07:23:33 PM PDT 24 119489000 ps
T319 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1062686379 Jul 28 07:23:19 PM PDT 24 Jul 28 07:23:38 PM PDT 24 272669800 ps
T1152 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3849812796 Jul 28 07:23:23 PM PDT 24 Jul 28 07:23:36 PM PDT 24 38826900 ps
T1153 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2067884856 Jul 28 07:23:45 PM PDT 24 Jul 28 07:23:59 PM PDT 24 46419700 ps
T1154 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1926305296 Jul 28 07:23:37 PM PDT 24 Jul 28 07:23:52 PM PDT 24 35800900 ps
T1155 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2319236436 Jul 28 07:23:03 PM PDT 24 Jul 28 07:23:19 PM PDT 24 20105400 ps
T283 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.923856878 Jul 28 07:23:20 PM PDT 24 Jul 28 07:36:12 PM PDT 24 3280362500 ps
T1156 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.4128190337 Jul 28 07:23:06 PM PDT 24 Jul 28 07:23:58 PM PDT 24 897748000 ps
T1157 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2432440843 Jul 28 07:23:30 PM PDT 24 Jul 28 07:23:47 PM PDT 24 34572300 ps
T320 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.273747257 Jul 28 07:23:25 PM PDT 24 Jul 28 07:23:40 PM PDT 24 320179200 ps
T287 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.4066170432 Jul 28 07:23:26 PM PDT 24 Jul 28 07:36:11 PM PDT 24 786006500 ps
T1158 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1883563249 Jul 28 07:23:16 PM PDT 24 Jul 28 07:23:32 PM PDT 24 18356800 ps
T1159 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.244979142 Jul 28 07:23:15 PM PDT 24 Jul 28 07:23:31 PM PDT 24 15246300 ps
T1160 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1600712406 Jul 28 07:23:22 PM PDT 24 Jul 28 07:23:58 PM PDT 24 675139800 ps
T321 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1255104634 Jul 28 07:23:12 PM PDT 24 Jul 28 07:23:29 PM PDT 24 212777500 ps
T277 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2279227120 Jul 28 07:23:37 PM PDT 24 Jul 28 07:23:53 PM PDT 24 65543000 ps
T285 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1912628227 Jul 28 07:23:35 PM PDT 24 Jul 28 07:23:53 PM PDT 24 78352200 ps
T322 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1269624238 Jul 28 07:22:51 PM PDT 24 Jul 28 07:23:37 PM PDT 24 95931300 ps
T1161 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.401561596 Jul 28 07:23:46 PM PDT 24 Jul 28 07:24:00 PM PDT 24 49111300 ps
T1162 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.365681961 Jul 28 07:23:32 PM PDT 24 Jul 28 07:23:46 PM PDT 24 168592200 ps
T278 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.844689202 Jul 28 07:23:16 PM PDT 24 Jul 28 07:23:32 PM PDT 24 64740000 ps
T323 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1310417249 Jul 28 07:23:37 PM PDT 24 Jul 28 07:38:54 PM PDT 24 862632600 ps
T324 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1380757511 Jul 28 07:23:40 PM PDT 24 Jul 28 07:23:56 PM PDT 24 243247200 ps
T1163 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.933652670 Jul 28 07:23:45 PM PDT 24 Jul 28 07:23:58 PM PDT 24 69025500 ps
T1164 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1405674861 Jul 28 07:23:39 PM PDT 24 Jul 28 07:23:52 PM PDT 24 72833400 ps
T1165 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2925664146 Jul 28 07:23:03 PM PDT 24 Jul 28 07:23:19 PM PDT 24 31673400 ps
T325 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3125556785 Jul 28 07:23:12 PM PDT 24 Jul 28 07:23:32 PM PDT 24 220079500 ps
T1166 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2610445085 Jul 28 07:23:42 PM PDT 24 Jul 28 07:23:55 PM PDT 24 66137000 ps
T1167 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3643488165 Jul 28 07:23:39 PM PDT 24 Jul 28 07:23:53 PM PDT 24 28283400 ps
T1168 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2950485369 Jul 28 07:23:39 PM PDT 24 Jul 28 07:23:53 PM PDT 24 48817300 ps
T282 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1498463875 Jul 28 07:23:24 PM PDT 24 Jul 28 07:23:44 PM PDT 24 62303900 ps
T1169 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.695583455 Jul 28 07:23:31 PM PDT 24 Jul 28 07:23:47 PM PDT 24 24236500 ps
T326 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.658697001 Jul 28 07:23:05 PM PDT 24 Jul 28 07:23:23 PM PDT 24 58727000 ps
T1170 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2742322091 Jul 28 07:22:57 PM PDT 24 Jul 28 07:23:43 PM PDT 24 24825000 ps
T1171 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2308205224 Jul 28 07:23:11 PM PDT 24 Jul 28 07:23:28 PM PDT 24 118301400 ps
T1172 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.4260041733 Jul 28 07:23:20 PM PDT 24 Jul 28 07:23:36 PM PDT 24 148425100 ps
T1173 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3679871698 Jul 28 07:23:31 PM PDT 24 Jul 28 07:23:47 PM PDT 24 12878300 ps
T1174 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1415443625 Jul 28 07:22:45 PM PDT 24 Jul 28 07:23:23 PM PDT 24 335722600 ps
T1175 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1764944038 Jul 28 07:23:19 PM PDT 24 Jul 28 07:23:36 PM PDT 24 34391300 ps
T1176 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.858596837 Jul 28 07:23:31 PM PDT 24 Jul 28 07:23:45 PM PDT 24 39654300 ps
T1177 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2067301077 Jul 28 07:23:44 PM PDT 24 Jul 28 07:23:58 PM PDT 24 14655300 ps
T1178 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.4266977294 Jul 28 07:23:07 PM PDT 24 Jul 28 07:23:21 PM PDT 24 29757800 ps
T286 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.361181217 Jul 28 07:23:32 PM PDT 24 Jul 28 07:23:49 PM PDT 24 140456500 ps
T1179 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1681493861 Jul 28 07:23:31 PM PDT 24 Jul 28 07:23:51 PM PDT 24 65718500 ps
T1180 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1910749362 Jul 28 07:23:09 PM PDT 24 Jul 28 07:23:53 PM PDT 24 1237657100 ps
T1181 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4116202736 Jul 28 07:22:57 PM PDT 24 Jul 28 07:23:11 PM PDT 24 17093900 ps
T1182 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3179053499 Jul 28 07:23:45 PM PDT 24 Jul 28 07:23:58 PM PDT 24 14595100 ps
T1183 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.717622093 Jul 28 07:22:42 PM PDT 24 Jul 28 07:22:56 PM PDT 24 50528800 ps
T359 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.4274138967 Jul 28 07:22:57 PM PDT 24 Jul 28 07:30:35 PM PDT 24 344081600 ps
T256 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2569987290 Jul 28 07:22:59 PM PDT 24 Jul 28 07:23:13 PM PDT 24 45989700 ps
T1184 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2173175990 Jul 28 07:22:57 PM PDT 24 Jul 28 07:23:12 PM PDT 24 249995600 ps
T1185 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.197595861 Jul 28 07:23:28 PM PDT 24 Jul 28 07:23:46 PM PDT 24 84216500 ps
T1186 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2236603235 Jul 28 07:23:06 PM PDT 24 Jul 28 07:24:13 PM PDT 24 662879000 ps
T284 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1851139899 Jul 28 07:23:34 PM PDT 24 Jul 28 07:23:54 PM PDT 24 334823100 ps
T290 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3502012312 Jul 28 07:23:37 PM PDT 24 Jul 28 07:30:14 PM PDT 24 3423115700 ps
T257 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3957622489 Jul 28 07:23:02 PM PDT 24 Jul 28 07:23:16 PM PDT 24 53799500 ps
T1187 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2513681303 Jul 28 07:23:39 PM PDT 24 Jul 28 07:23:52 PM PDT 24 24592900 ps
T327 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.372694263 Jul 28 07:23:31 PM PDT 24 Jul 28 07:24:06 PM PDT 24 200308300 ps
T1188 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.789248938 Jul 28 07:22:44 PM PDT 24 Jul 28 07:23:01 PM PDT 24 47934500 ps
T1189 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.251046312 Jul 28 07:23:41 PM PDT 24 Jul 28 07:23:55 PM PDT 24 47292600 ps
T291 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3823914134 Jul 28 07:23:41 PM PDT 24 Jul 28 07:23:57 PM PDT 24 356767900 ps
T1190 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1160943515 Jul 28 07:23:22 PM PDT 24 Jul 28 07:23:38 PM PDT 24 28001600 ps
T1191 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3028188115 Jul 28 07:23:47 PM PDT 24 Jul 28 07:24:00 PM PDT 24 17734800 ps
T1192 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2755006538 Jul 28 07:23:46 PM PDT 24 Jul 28 07:24:00 PM PDT 24 26167900 ps
T358 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1971004702 Jul 28 07:23:09 PM PDT 24 Jul 28 07:30:42 PM PDT 24 1501521600 ps
T1193 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1015045168 Jul 28 07:23:38 PM PDT 24 Jul 28 07:23:52 PM PDT 24 16201900 ps
T1194 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.627595790 Jul 28 07:23:21 PM PDT 24 Jul 28 07:23:38 PM PDT 24 35374100 ps
T1195 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1214329512 Jul 28 07:23:32 PM PDT 24 Jul 28 07:23:48 PM PDT 24 14158700 ps
T1196 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2915314820 Jul 28 07:23:40 PM PDT 24 Jul 28 07:23:54 PM PDT 24 52171100 ps
T1197 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.978808931 Jul 28 07:23:16 PM PDT 24 Jul 28 07:23:39 PM PDT 24 1021757400 ps
T1198 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2047175129 Jul 28 07:23:15 PM PDT 24 Jul 28 07:23:31 PM PDT 24 46930700 ps
T361 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.911667153 Jul 28 07:23:22 PM PDT 24 Jul 28 07:31:00 PM PDT 24 956028500 ps
T258 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3734957917 Jul 28 07:22:50 PM PDT 24 Jul 28 07:23:04 PM PDT 24 35712700 ps
T288 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3986858553 Jul 28 07:23:14 PM PDT 24 Jul 28 07:23:30 PM PDT 24 33259000 ps
T1199 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2736001243 Jul 28 07:23:38 PM PDT 24 Jul 28 07:23:53 PM PDT 24 12022700 ps
T1200 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3769804885 Jul 28 07:22:53 PM PDT 24 Jul 28 07:23:10 PM PDT 24 321914200 ps
T1201 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2704297172 Jul 28 07:23:14 PM PDT 24 Jul 28 07:23:28 PM PDT 24 15993500 ps
T1202 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1905839472 Jul 28 07:23:11 PM PDT 24 Jul 28 07:23:29 PM PDT 24 76505800 ps
T1203 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3545752651 Jul 28 07:23:17 PM PDT 24 Jul 28 07:23:33 PM PDT 24 13774100 ps
T1204 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2968683302 Jul 28 07:23:06 PM PDT 24 Jul 28 07:23:21 PM PDT 24 135499900 ps
T1205 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2088300067 Jul 28 07:22:46 PM PDT 24 Jul 28 07:23:04 PM PDT 24 124870100 ps
T1206 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3253159173 Jul 28 07:23:38 PM PDT 24 Jul 28 07:23:53 PM PDT 24 87349100 ps
T1207 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3230140929 Jul 28 07:23:26 PM PDT 24 Jul 28 07:23:42 PM PDT 24 48220800 ps
T1208 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2451042958 Jul 28 07:23:24 PM PDT 24 Jul 28 07:23:40 PM PDT 24 16315800 ps
T1209 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3344495216 Jul 28 07:22:42 PM PDT 24 Jul 28 07:22:56 PM PDT 24 13256100 ps
T1210 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2668551102 Jul 28 07:23:35 PM PDT 24 Jul 28 07:23:51 PM PDT 24 21665900 ps
T1211 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.187016140 Jul 28 07:23:35 PM PDT 24 Jul 28 07:23:55 PM PDT 24 188951300 ps
T362 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.470551645 Jul 28 07:23:17 PM PDT 24 Jul 28 07:29:44 PM PDT 24 881113600 ps
T1212 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2483935787 Jul 28 07:23:39 PM PDT 24 Jul 28 07:23:55 PM PDT 24 141256100 ps
T1213 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3690277878 Jul 28 07:23:06 PM PDT 24 Jul 28 07:23:24 PM PDT 24 295995400 ps
T1214 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1865653215 Jul 28 07:23:17 PM PDT 24 Jul 28 07:23:36 PM PDT 24 205023100 ps
T1215 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1903686895 Jul 28 07:23:39 PM PDT 24 Jul 28 07:24:14 PM PDT 24 161354200 ps
T1216 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1485456099 Jul 28 07:23:36 PM PDT 24 Jul 28 07:23:52 PM PDT 24 23042300 ps
T295 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3454499683 Jul 28 07:23:26 PM PDT 24 Jul 28 07:23:46 PM PDT 24 113666300 ps
T1217 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.197796307 Jul 28 07:23:35 PM PDT 24 Jul 28 07:23:49 PM PDT 24 15766300 ps
T1218 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2600245911 Jul 28 07:23:40 PM PDT 24 Jul 28 07:23:54 PM PDT 24 44527900 ps
T296 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1741314206 Jul 28 07:23:12 PM PDT 24 Jul 28 07:23:29 PM PDT 24 54116000 ps
T289 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2728391190 Jul 28 07:23:08 PM PDT 24 Jul 28 07:23:26 PM PDT 24 190865100 ps
T1219 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3624351062 Jul 28 07:23:29 PM PDT 24 Jul 28 07:23:45 PM PDT 24 20777600 ps
T1220 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1899831403 Jul 28 07:23:17 PM PDT 24 Jul 28 07:23:32 PM PDT 24 35451900 ps
T1221 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.4031866680 Jul 28 07:23:01 PM PDT 24 Jul 28 07:23:16 PM PDT 24 12800900 ps
T1222 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1277231222 Jul 28 07:22:59 PM PDT 24 Jul 28 07:23:47 PM PDT 24 2615799100 ps
T363 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.4116481965 Jul 28 07:23:12 PM PDT 24 Jul 28 07:30:53 PM PDT 24 696758900 ps
T1223 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1458391375 Jul 28 07:23:19 PM PDT 24 Jul 28 07:23:36 PM PDT 24 62279000 ps
T1224 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.610494495 Jul 28 07:23:01 PM PDT 24 Jul 28 07:23:15 PM PDT 24 19232000 ps
T357 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1181332356 Jul 28 07:23:30 PM PDT 24 Jul 28 07:38:24 PM PDT 24 4534652000 ps
T297 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.62781066 Jul 28 07:23:19 PM PDT 24 Jul 28 07:23:38 PM PDT 24 58072000 ps
T292 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.811182195 Jul 28 07:23:31 PM PDT 24 Jul 28 07:23:51 PM PDT 24 94603600 ps
T1225 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.814715964 Jul 28 07:23:25 PM PDT 24 Jul 28 07:23:39 PM PDT 24 16171000 ps
T1226 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2078309574 Jul 28 07:23:39 PM PDT 24 Jul 28 07:23:53 PM PDT 24 60027600 ps
T1227 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.601506373 Jul 28 07:23:44 PM PDT 24 Jul 28 07:23:58 PM PDT 24 104404300 ps
T1228 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2153098776 Jul 28 07:23:41 PM PDT 24 Jul 28 07:24:00 PM PDT 24 148576800 ps
T1229 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2614235506 Jul 28 07:23:39 PM PDT 24 Jul 28 07:23:53 PM PDT 24 25197500 ps
T1230 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.566255572 Jul 28 07:23:21 PM PDT 24 Jul 28 07:23:39 PM PDT 24 42509700 ps
T293 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.309499619 Jul 28 07:22:40 PM PDT 24 Jul 28 07:22:59 PM PDT 24 89578400 ps
T1231 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1597693953 Jul 28 07:23:19 PM PDT 24 Jul 28 07:23:34 PM PDT 24 133706900 ps
T1232 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3907280420 Jul 28 07:23:47 PM PDT 24 Jul 28 07:24:00 PM PDT 24 29682200 ps
T1233 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3574536387 Jul 28 07:22:58 PM PDT 24 Jul 28 07:23:12 PM PDT 24 105979300 ps
T1234 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1052880820 Jul 28 07:23:41 PM PDT 24 Jul 28 07:23:55 PM PDT 24 146744900 ps
T1235 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1140092644 Jul 28 07:23:16 PM PDT 24 Jul 28 07:23:32 PM PDT 24 11506200 ps
T1236 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3312717406 Jul 28 07:23:27 PM PDT 24 Jul 28 07:38:22 PM PDT 24 1311947200 ps
T1237 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2134059885 Jul 28 07:23:42 PM PDT 24 Jul 28 07:23:55 PM PDT 24 51370600 ps
T1238 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2259733150 Jul 28 07:23:39 PM PDT 24 Jul 28 07:23:55 PM PDT 24 21632400 ps
T1239 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.409746758 Jul 28 07:23:24 PM PDT 24 Jul 28 07:23:42 PM PDT 24 632841700 ps
T1240 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3108302991 Jul 28 07:23:31 PM PDT 24 Jul 28 07:23:49 PM PDT 24 53711700 ps
T1241 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3994040689 Jul 28 07:23:46 PM PDT 24 Jul 28 07:24:00 PM PDT 24 25288800 ps
T1242 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.423750109 Jul 28 07:22:49 PM PDT 24 Jul 28 07:23:02 PM PDT 24 57671700 ps
T1243 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.279619386 Jul 28 07:23:17 PM PDT 24 Jul 28 07:23:31 PM PDT 24 34130000 ps
T1244 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1578401272 Jul 28 07:23:38 PM PDT 24 Jul 28 07:23:56 PM PDT 24 114416100 ps
T1245 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1377557547 Jul 28 07:23:46 PM PDT 24 Jul 28 07:23:59 PM PDT 24 26893800 ps
T1246 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1099367073 Jul 28 07:23:19 PM PDT 24 Jul 28 07:23:33 PM PDT 24 41291900 ps
T1247 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.989803092 Jul 28 07:22:47 PM PDT 24 Jul 28 07:23:28 PM PDT 24 12364695200 ps
T1248 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1836602625 Jul 28 07:22:55 PM PDT 24 Jul 28 07:23:12 PM PDT 24 180954400 ps
T1249 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3978150172 Jul 28 07:23:40 PM PDT 24 Jul 28 07:23:54 PM PDT 24 54016000 ps
T1250 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.583424803 Jul 28 07:23:02 PM PDT 24 Jul 28 07:23:33 PM PDT 24 72342400 ps
T1251 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1524886375 Jul 28 07:23:22 PM PDT 24 Jul 28 07:23:42 PM PDT 24 549713700 ps
T1252 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3538509734 Jul 28 07:23:44 PM PDT 24 Jul 28 07:23:57 PM PDT 24 17235400 ps
T1253 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2457254844 Jul 28 07:23:27 PM PDT 24 Jul 28 07:23:41 PM PDT 24 15145400 ps
T1254 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1197569233 Jul 28 07:22:52 PM PDT 24 Jul 28 07:23:26 PM PDT 24 485035900 ps
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